<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22238">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Install common i2c<br><br>Add common i2c support for cannonlake.<br><br>TEST=N/A<br><br>Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/chip.h<br>A src/soc/intel/cannonlake/i2c.c<br>4 files changed, 80 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/22238/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig<br>index 5f24ab0..7c4918b 100644<br>--- a/src/soc/intel/cannonlake/Kconfig<br>+++ b/src/soc/intel/cannonlake/Kconfig<br>@@ -52,6 +52,7 @@<br> select SOC_INTEL_COMMON_BLOCK_GPIO<br> select SOC_INTEL_COMMON_BLOCK_GSPI<br> select SOC_INTEL_COMMON_BLOCK_ITSS<br>+ select SOC_INTEL_COMMON_BLOCK_I2C<br> select SOC_INTEL_COMMON_BLOCK_LPC<br> select SOC_INTEL_COMMON_BLOCK_LPSS<br> select SOC_INTEL_COMMON_BLOCK_P2SB<br>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 8dfff91..9c2e422 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -15,12 +15,14 @@<br> bootblock-y += bootblock/report_platform.c<br> bootblock-y += gpio.c<br> bootblock-y += gspi.c<br>+bootblock-y += i2c.c<br> bootblock-y += memmap.c<br> bootblock-y += spi.c<br> bootblock-$(CONFIG_UART_DEBUG) += uart.c<br> <br> romstage-y += gpio.c<br> romstage-y += gspi.c<br>+romstage-y += i2c.c<br> romstage-y += memmap.c<br> romstage-y += pmutil.c<br> romstage-y += reset.c<br>@@ -35,6 +37,7 @@<br> ramstage-y += graphics.c<br> ramstage-y += gspi.c<br> ramstage-y += gpio.c<br>+ramstage-y += i2c.c<br> ramstage-y += lpc.c<br> ramstage-y += memmap.c<br> ramstage-y += pmc.c<br>@@ -60,6 +63,7 @@<br> postcar-$(CONFIG_UART_DEBUG) += uart.c<br> <br> verstage-y += gspi.c<br>+verstage-y += i2c.c<br> verstage-y += pmutil.c<br> verstage-y += spi.c<br> verstage-$(CONFIG_UART_DEBUG) += uart.c<br>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h<br>index dbe211d..e2a3000 100644<br>--- a/src/soc/intel/cannonlake/chip.h<br>+++ b/src/soc/intel/cannonlake/chip.h<br>@@ -19,11 +19,14 @@<br> #define _SOC_CHIP_H_<br> <br> #include <intelblocks/gspi.h><br>+#include <intelblocks/lpss_i2c.h><br> #include <stdint.h><br> #include <soc/pch.h><br> #include <soc/serialio.h><br> #include <soc/usb.h><br> #include <soc/vr_config.h><br>+<br>+#define CANNONLAKE_I2C_DEV_MAX 6<br> <br> struct soc_intel_cannonlake_config {<br> /* GSPI */<br>@@ -245,6 +248,9 @@<br> * PchSerialIoHidden<br> */<br> uint8_t SerialIoDevMode[PchSerialIoIndexMAX];<br>+<br>+ /* I2C bus configuration */<br>+ struct lpss_i2c_bus_config i2c[CANNONLAKE_I2C_DEV_MAX];<br> };<br> <br> typedef struct soc_intel_cannonlake_config config_t;<br>diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/cannonlake/i2c.c<br>new file mode 100644<br>index 0000000..dcba483<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/i2c.c<br>@@ -0,0 +1,69 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2016 Google Inc.<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <device/device.h><br>+#include <device/pci_def.h><br>+#include <intelblocks/lpss_i2c.h><br>+#include <soc/iomap.h><br>+#include <soc/pci_devs.h><br>+#include "chip.h"<br>+<br>+const struct lpss_i2c_bus_config *i2c_get_soc_cfg(unsigned int bus,<br>+ const struct device *dev)<br>+{<br>+ const struct soc_intel_cannonlake_config *config;<br>+ if (!dev || !dev->chip_info) {<br>+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",<br>+ __func__);<br>+ return NULL;<br>+ }<br>+<br>+ config = dev->chip_info;<br>+<br>+ return &config->i2c[bus];<br>+}<br>+<br>+uintptr_t i2c_get_soc_early_base(unsigned int bus)<br>+{<br>+ return EARLY_I2C_BASE(bus);<br>+}<br>+<br>+int i2c_soc_devfn_to_bus(unsigned int devfn)<br>+{<br>+ switch (devfn) {<br>+ case PCH_DEVFN_I2C0: return 0;<br>+ case PCH_DEVFN_I2C1: return 1;<br>+ case PCH_DEVFN_I2C2: return 2;<br>+ case PCH_DEVFN_I2C3: return 3;<br>+ case PCH_DEVFN_I2C4: return 4;<br>+ case PCH_DEVFN_I2C5: return 5;<br>+ }<br>+ return -1;<br>+}<br>+<br>+int i2c_soc_bus_to_devfn(unsigned int bus)<br>+{<br>+ switch (bus) {<br>+ case 0: return PCH_DEVFN_I2C0;<br>+ case 1: return PCH_DEVFN_I2C1;<br>+ case 2: return PCH_DEVFN_I2C2;<br>+ case 3: return PCH_DEVFN_I2C3;<br>+ case 4: return PCH_DEVFN_I2C4;<br>+ case 5: return PCH_DEVFN_I2C5;<br>+ }<br>+ return -1;<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/22238">change 22238</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22238"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b </div>
<div style="display:none"> Gerrit-Change-Number: 22238 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>