<p>Lubomir Rintel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22258">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vx900: map the SPI controller<br><br>This is required for Flashrom to work well.<br><br>Change-Id: Id756d86a7f3b34f816ea7a7ed78f159512f550d5<br>Signed-off-by: Lubomir Rintel <lkundrak@v3.sk><br>---<br>M src/northbridge/via/vx900/lpc.c<br>M src/northbridge/via/vx900/vx900.h<br>2 files changed, 53 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/22258/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c<br>index b36aaed..822e9ac 100644<br>--- a/src/northbridge/via/vx900/lpc.c<br>+++ b/src/northbridge/via/vx900/lpc.c<br>@@ -184,9 +184,58 @@<br> dump_pci_device(dev);<br> }<br> <br>+static void vx900_lpc_read_resources(device_t dev)<br>+{<br>+ struct resource *res;<br>+ pci_dev_read_resources(dev);<br>+<br>+ /* MMIO space */<br>+ res = new_resource(dev, VX900_MMCONFIG_MBAR);<br>+ res->base = 0xfed03000;<br>+ res->size = 0x1000;<br>+ res->align = 12;<br>+ res->gran = 12;<br>+ res->limit = 0xffffffff;<br>+ res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE;<br>+<br>+ /* SPI controller */<br>+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));<br>+ res->base = 0xfed02000;<br>+ res->size = 0x8;<br>+ res->align = 12;<br>+ res->gran = 12;<br>+ res->limit = 0xffffffff;<br>+ res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE;<br>+}<br>+<br>+static void vx900_lpc_set_resources(device_t dev)<br>+{<br>+ struct resource *mmio, *spi;<br>+ u32 reg;<br>+<br>+ mmio = find_resource(dev, VX900_MMCONFIG_MBAR);<br>+ if (mmio) {<br>+ report_resource_stored(dev, mmio, "<mmconfig>");<br>+ mmio->flags |= IORESOURCE_STORED;<br>+ reg = pci_read_config32(dev, VX900_MMCONFIG_MBAR);<br>+ reg &= 0xff000000;<br>+ reg |= mmio->base >> 8;<br>+ pci_write_config32(dev, VX900_MMCONFIG_MBAR, reg);<br>+<br>+ spi = find_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));<br>+ if (spi) {<br>+ report_resource_stored(dev, spi, "<spi>");<br>+ spi->flags |= IORESOURCE_STORED;<br>+ /* Set base and the enable bit. */<br>+ ((u32*)(uintptr_t)mmio->base)[0] = (spi->base | 0x01);<br>+ }<br>+ }<br>+ pci_dev_set_resources(dev);<br>+}<br>+<br> static struct device_operations vx900_lpc_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>+ .read_resources = vx900_lpc_read_resources,<br>+ .set_resources = vx900_lpc_set_resources,<br> .enable_resources = pci_dev_enable_resources,<br> .init = vx900_lpc_init,<br> .scan_bus = scan_lpc_bus,<br>diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h<br>index 12e5733..216f637 100644<br>--- a/src/northbridge/via/vx900/vx900.h<br>+++ b/src/northbridge/via/vx900/vx900.h<br>@@ -26,6 +26,8 @@<br> <br> #define SMBUS_IO_BASE 0x500<br> <br>+#define VX900_MMCONFIG_MBAR 0xbc<br>+<br> /* The maximum number of DIMM slots that the VX900 supports */<br> #define VX900_MAX_DIMM_SLOTS 2<br> #define VX900_MAX_MEM_RANKS 4<br></pre><p>To view, visit <a href="https://review.coreboot.org/22258">change 22258</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22258"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id756d86a7f3b34f816ea7a7ed78f159512f550d5 </div>
<div style="display:none"> Gerrit-Change-Number: 22258 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lubomir Rintel <lkundrak@v3.sk> </div>