<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22245">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Add pci_dev macros<br><br>Add #defines that will allow easy use of PCI devices across stages.<br>Future work can convert soc/amd/stoneyridge to use these and clean<br>up the DEV_D18F4 macro still in place.<br><br>Change-Id: I78c297d9610009e7b9e2233984e1a167f0ab88c7<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/pci_devs.h<br>1 file changed, 32 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/22245/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h<br>index c02727b..723899b 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h<br>@@ -19,107 +19,132 @@<br> #include <device/pci_def.h><br> #include <rules.h><br> <br>+#if !defined(__SIMPLE_DEVICE__)<br>+#include <device/device.h><br>+#define _SOC_DEV(slot, func) dev_find_slot(0, PCI_DEVFN(slot, func))<br>+#else<br>+#include <arch/io.h><br>+#define _SOC_DEV(slot, func) PCI_DEV(0, slot, func)<br>+#endif<br>+<br> /* GNB Root Complex */<br> #define GNB_DEV 0x0<br> #define GNB_FUNC 0<br> #define GNB_DEVID 0x1576<br> #define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC)<br>+#define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC)<br> <br> /* IOMMU */<br> #define IOMMU_DEV 0x0<br> #define IOMMU_FUNC 2<br> #define IOMMU_DEVID 0x1577<br> #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)<br>+#define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC)<br> <br> /* Internal Graphics */<br> #define GFX_DEV 0x1<br> #define GFX_FUNC 0<br> #define GFX_DEVID 098e4 /* subject to SKU/OPN variation */<br> #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC)<br>+#define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC)<br> <br> /* HD Audio 0 */<br> #define HDA0_DEV 0x1<br> #define HDA0_FUNC 1<br> #define HDA0_DEVID 015b3<br> #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC)<br>+#define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC)<br> <br> /* Host Bridge */<br> #define HOST_DEV 0x2<br> #define HOST_FUNC 0<br> #define HOST_DEVID 0x157b<br> #define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC)<br>+#define SOC_HOST_DEV _SOC_DEV(HOST_DEV, HOST_FUNC)<br> <br> /* PCIe GPP Bridge 0 */<br> #define PCIE0_DEV 0x2<br> #define PCIE0_FUNC 1<br> #define PCIE0_DEVID 0x157c<br> #define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC)<br>+#define SOC_PCIE0_DEV _SOC_DEV(PCIE0_DEV, PCIE0_FUNC)<br> <br> /* PCIe GPP Bridge 1 */<br> #define PCIE1_DEV 0x2<br> #define PCIE1_FUNC 2<br> #define PCIE1_DEVID 0x157c<br> #define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC)<br>+#define SOC_PCIE1_DEV _SOC_DEV(PCIE1_DEV, PCIE1_FUNC)<br> <br> /* PCIe GPP Bridge 2 */<br> #define PCIE2_DEV 0x2<br> #define PCIE2_FUNC 3<br> #define PCIE2_DEVID 0x157c<br> #define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC)<br>+#define SOC_PCIE2_DEV _SOC_DEV(PCIE2_DEV, PCIE2_FUNC)<br> <br> /* PCIe GPP Bridge 3 */<br> #define PCIE3_DEV 0x2<br> #define PCIE3_FUNC 4<br> #define PCIE3_DEVID 0x157c<br> #define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC)<br>+#define SOC_PCIE3_DEV _SOC_DEV(PCIE3_DEV, PCIE3_FUNC)<br> <br> /* PCIe GPP Bridge 4 */<br> #define PCIE4_DEV 0x2<br> #define PCIE4_FUNC 5<br> #define PCIE4_DEVID 0x157c<br> #define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC)<br>+#define SOC_PCIE4_DEV _SOC_DEV(PCIE4_DEV, PCIE4_FUNC)<br> <br> /* Platform Security Processor */<br> #define PSP_DEV 0x8<br> #define PSP_FUNC 0<br> #define PSP_DEVID 0x1578<br> #define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC)<br>+#define SOC_PSP_DEV _SOC_DEV(PSP_DEV, PSP_FUNC)<br> <br> /* HD Audio 1 */<br> #define HDA1_DEV 0x9<br> #define HDA1_FUNC 2<br> #define HDA1_DEVID 0x157a<br> #define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC)<br>+#define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC)<br> <br> /* HT Configuration */<br> #define HT_DEV 0x18<br> #define HT_FUNC 0<br> #define HT_DEVID 0x15b0<br> #define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC)<br>+#define SOC_HT_DEV _SOC_DEV(HT_DEV, HT_FUNC)<br> <br> /* Address Maps */<br> #define ADDR_DEV 0x18<br> #define ADDR_FUNC 1<br> #define ADDR_DEVID 0x15b1<br> #define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC)<br>+#define SOC_ADDR_DEV _SOC_DEV(ADDR_DEV, ADDR_FUNC)<br> <br> /* DRAM Configuration */<br> #define DCT_DEV 0x18<br> #define DCT_FUNC 2<br> #define DCT_DEVID 0x15b2<br> #define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC)<br>+#define SOC_DCT_DEV _SOC_DEV(DCT_DEV, DCT_FUNC)<br> <br> /* Misc. Configuration */<br> #define MISC_DEV 0x18<br> #define MISC_FUNC 3<br> #define MISC_DEVID 0x15b3<br> #define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC)<br>+#define SOC_MISC_DEV _SOC_DEV(MISC_DEV, MISC_FUNC)<br> <br> /* PM Configuration */<br> #define PM_DEV 0x18<br> #define PM_FUNC 4<br> #define PM_DEVID 0x15b4<br> #define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC)<br>+#define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC)<br> #if !defined(__SIMPLE_DEVICE__)<br> #include <device/device.h><br> #define DEV_D18F4 dev_find_slot(0, PM_DEVFN)<br>@@ -132,12 +157,14 @@<br> #define NB_FUNC 5<br> #define NB_DEVID 0x15b5<br> #define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC)<br>+#define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC)<br> <br> /* XHCI */<br> #define XHCI_DEV 0x10<br> #define XHCI_FUNC 0<br> #define XHCI_DEVID 0x7914<br> #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC)<br>+#define SOC_XHCI_DEV _SOC_DEV(XHCI_DEV, XHCI_FUNC)<br> <br> /* SATA */<br> #define SATA_DEV 0x11<br>@@ -146,29 +173,34 @@<br> #define AHCI_DEVID_MS 0x7901<br> #define AHCI_DEVID_AMD 0x7904<br> #define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC)<br>+#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC)<br> <br> /* EHCI */<br> #define EHCI_DEV 0x12<br> #define EHCI_FUNC 0<br> #define EHCI_DEVID 0x7908<br> #define EHCI1_DEVFN PCI_DEVFN(EHCI_DEV, EHCI_FUNC)<br>+#define SOC_EHCI1_DEV _SOC_DEV(EHCI_DEV, EHCI_FUNC)<br> <br> /* SMBUS */<br> #define SMBUS_DEV 0x14<br> #define SMBUS_FUNC 0<br> #define SMBUS_DEVID 0x790b<br> #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)<br>+#define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC)<br> <br> /* LPC BUS */<br> #define PCU_DEV 0x14<br> #define LPC_FUNC 3<br> #define LPC_DEVID 0x790e<br> #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC)<br>+#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC)<br> <br> /* SD Controller */<br> #define SD_DEV 0x14<br> #define SD_FUNC 7<br> #define SD_DEVID 0x7906<br> #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC)<br>+#define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC)<br> <br> #endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */<br></pre><p>To view, visit <a href="https://review.coreboot.org/22245">change 22245</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22245"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I78c297d9610009e7b9e2233984e1a167f0ab88c7 </div>
<div style="display:none"> Gerrit-Change-Number: 22245 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>