<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22220">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[HACK] G45 update<br><br>VGACNTRL is at a different location, PFIT_CONTROL vanished with Ironlake?<br>Do not use on anything newer.<br><br>Change-Id: Ida58e8dd10a4b430d815f388ddd9155ce40d3789<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M common/hw-gfx-gma-pipe_setup.adb<br>M common/hw-gfx-gma-registers.ads<br>2 files changed, 7 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/20/22220/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/common/hw-gfx-gma-pipe_setup.adb b/common/hw-gfx-gma-pipe_setup.adb<br>index 256c7f5..a98e38f 100644<br>--- a/common/hw-gfx-gma-pipe_setup.adb<br>+++ b/common/hw-gfx-gma-pipe_setup.adb<br>@@ -235,7 +235,8 @@<br> VGA_CONTROL_BLINK_DUTY_CYCLE_MASK or<br> VGA_CONTROL_VSYNC_BLINK_RATE_MASK,<br> Mask_Set => VGA_CONTROL_BLINK_DUTY_CYCLE_50 or<br>- VGA_CONTROL_VSYNC_BLINK_RATE (30));<br>+ VGA_CONTROL_VSYNC_BLINK_RATE (30) or<br>+ 16#4_0000#);<br> <br> Port_IO.OutB (VGA_SR_INDEX, VGA_SR01);<br> Port_IO.InB (Reg8, VGA_SR_DATA);<br>@@ -377,6 +378,7 @@<br> Registers.Write<br> (Register => Controller.PF_WIN_SZ,<br> Value => Shift_Left (Word32 (Width), 16) or Word32 (Height));<br>+ Registers.Write (Registers.GMCH_PFIT_CONTROL, 16#8000_0000#);<br> end Setup_Ironlake_Panel_Fitter;<br> <br> procedure Setup_Scaling<br>diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads<br>index d061b2a..75fecd4 100644<br>--- a/common/hw-gfx-gma-registers.ads<br>+++ b/common/hw-gfx-gma-registers.ads<br>@@ -76,7 +76,6 @@<br> BCS_PP_DCLV_HIGH,<br> BCS_PP_DCLV_LOW,<br> GAB_CTL_REG,<br>- VGACNTRL,<br> FUSE_STATUS,<br> ILK_DISPLAY_CHICKEN2,<br> DSPCLK_GATE_D,<br>@@ -170,6 +169,7 @@<br> GMCH_PP_ON_DELAYS,<br> GMCH_PP_OFF_DELAYS,<br> GMCH_PP_DIVISOR,<br>+ GMCH_PFIT_CONTROL,<br> PIPEB_DDI_FUNC_CTL,<br> PIPEB_MSA_MISC,<br> SRD_CTL_B,<br>@@ -498,6 +498,7 @@<br> PLANE_WM_1_B_7,<br> PLANE_BUF_CFG_1_B,<br> SPBCNTR,<br>+ VGACNTRL,<br> PIPE_SCANLINE_C,<br> PIPECCONF,<br> PIPECMISC,<br>@@ -1313,6 +1314,7 @@<br> GMCH_PP_ON_DELAYS => 16#06_1208# / Register_Width,<br> GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width,<br> GMCH_PP_DIVISOR => 16#06_1210# / Register_Width,<br>+ GMCH_PFIT_CONTROL => 16#06_1230# / Register_Width,<br> PCH_PP_STATUS => 16#0c_7200# / Register_Width,<br> PCH_PP_CONTROL => 16#0c_7204# / Register_Width,<br> PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,<br>@@ -1349,7 +1351,7 @@<br> PCH_HDMID => 16#0e_1160# / Register_Width,<br> <br> -- Intel Registers<br>- VGACNTRL => 16#04_1000# / Register_Width,<br>+ VGACNTRL => 16#07_1400# / Register_Width,<br> FUSE_STATUS => 16#04_2000# / Register_Width,<br> FBA_CFB_BASE => 16#04_3200# / Register_Width,<br> IPS_CTL => 16#04_3408# / Register_Width,<br></pre><p>To view, visit <a href="https://review.coreboot.org/22220">change 22220</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22220"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: libgfxinit </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ida58e8dd10a4b430d815f388ddd9155ce40d3789 </div>
<div style="display:none"> Gerrit-Change-Number: 22220 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>