<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22214">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/sandybridge/raminit: Add ECC detection support<br><br>Add support for detection ECC capability and forced ECC mode.<br>Print the ECC mode in verbose debugging mode.<br><br>Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/northbridge/intel/sandybridge/raminit.c<br>M src/northbridge/intel/sandybridge/raminit_common.c<br>M src/northbridge/intel/sandybridge/raminit_common.h<br>3 files changed, 51 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/22214/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c<br>index 2dbfeee..8e8c457 100644<br>--- a/src/northbridge/intel/sandybridge/raminit.c<br>+++ b/src/northbridge/intel/sandybridge/raminit.c<br>@@ -398,6 +398,13 @@<br>                 cpu = cpures.eax;<br>             ctrl.sandybridge = IS_SANDY_CPU(cpu);<br> <br>+             /* Get ECC support and mode */<br>+               ctrl.ecc_supported = get_host_ecc_cap();<br>+             ctrl.ecc_forced = ctrl.ecc_supported ? get_host_ecc_mode() : 0;<br>+              printk(BIOS_DEBUG, "ECC supported: %s ECC forced: %s\n",<br>+                           ctrl.ecc_supported ? "yes" : "no",<br>+                               ctrl.ecc_forced ? "yes" : "no");<br>+<br>               /* Get DDR3 SPD data */<br>               memset(spds, 0, sizeof(spds));<br>                mainboard_get_spd(spds, 0);<br>@@ -421,6 +428,13 @@<br>             cpu = cpures.eax;<br>             ctrl.sandybridge = IS_SANDY_CPU(cpu);<br> <br>+             /* Get ECC support and mode */<br>+               ctrl.ecc_supported = get_host_ecc_cap();<br>+             ctrl.ecc_forced = ctrl.ecc_supported ? get_host_ecc_mode() : 0;<br>+              printk(BIOS_DEBUG, "ECC supported: %s ECC forced: %s\n",<br>+                           ctrl.ecc_supported ? "yes" : "no",<br>+                               ctrl.ecc_forced ? "yes" : "no");<br>+<br>               /* Reset DDR3 frequency */<br>            dram_find_spds_ddr3(spds, &ctrl);<br> <br>diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c<br>index eaef5f7..00bb513 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_common.c<br>+++ b/src/northbridge/intel/sandybridge/raminit_common.c<br>@@ -463,6 +463,38 @@<br>               return cfg->pci_mmio_size;<br> }<br> <br>+/*<br>+ * Returns the ECC capability.<br>+ * Return 0: ECC isn't supported<br>+ * Return 1: ECC is supported<br>+ */<br>+unsigned int get_host_ecc_cap(void)<br>+{<br>+    const struct device *dev = dev_find_slot(0, HOST_BRIDGE);<br>+    if (!dev)<br>+            return 0;<br>+<br>+ /* read Capabilities A Register */<br>+   const u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);<br>+     return !!(reg32 & (1<<25));<br>+}<br>+<br>+/*<br>+ * Returns the ECC mode the NB is running at.<br>+ * Return 0: ECC is optional<br>+ * Return 1: ECC is enabled and can't be disabled<br>+ */<br>+unsigned int get_host_ecc_mode(void)<br>+{<br>+    const struct device *dev = dev_find_slot(0, HOST_BRIDGE);<br>+    if (!dev)<br>+            return 0;<br>+<br>+ /* read Capabilities A Register */<br>+   const u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);<br>+     return !!(reg32 & (1<<24));<br>+}<br>+<br> void dram_memorymap(ramctr_timing * ctrl, int me_uma_size)<br> {<br>         u32 reg, val, reclaim;<br>diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h<br>index ab6e592..cd8310d 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_common.h<br>+++ b/src/northbridge/intel/sandybridge/raminit_common.h<br>@@ -119,6 +119,8 @@<br>  int reg_c14_offset;<br>   int reg_320c_range_threshold;<br> <br>+     int ecc_supported;<br>+   int ecc_forced;<br>       int edge_offset[3];<br>   int timC_offset[3];<br> <br>@@ -186,4 +188,7 @@<br> int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot,<br>          int s3_resume, int me_uma_size);<br> <br>+unsigned int get_host_ecc_cap(void);<br>+unsigned int get_host_ecc_mode(void);<br>+<br> #endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/22214">change 22214</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22214"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a </div>
<div style="display:none"> Gerrit-Change-Number: 22214 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>