<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22189">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/common/p2sb: Add common p2sb driver<br><br>Add common p2sb device driver that will use fixed resource instead<br>dynamic assigned by PCI enumeration.<br><br>TEST=None<br><br>Change-Id: Ie3f7036a5956e3db1662678aaf43023ff79ae10e<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>A src/soc/intel/common/block/include/intelblocks/p2sb.h<br>A src/soc/intel/common/block/p2sb/Kconfig<br>A src/soc/intel/common/block/p2sb/Makefile.inc<br>A src/soc/intel/common/block/p2sb/p2sb.c<br>4 files changed, 109 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/22189/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h<br>new file mode 100644<br>index 0000000..8139a69<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h<br>@@ -0,0 +1,22 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef SOC_INTEL_COMMON_BLOCK_P2SB_H<br>+#define SOC_INTEL_COMMON_BLOCK_P2SB_H<br>+<br>+void p2sb_unhide(void);<br>+void p2sb_hide(void);<br>+<br>+#endif /* SOC_INTEL_COMMON_BLOCK_P2SB_H */<br>diff --git a/src/soc/intel/common/block/p2sb/Kconfig b/src/soc/intel/common/block/p2sb/Kconfig<br>new file mode 100644<br>index 0000000..196f349<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/p2sb/Kconfig<br>@@ -0,0 +1,6 @@<br>+config SOC_INTEL_COMMON_BLOCK_P2SB<br>+ bool<br>+ depends on SOC_INTEL_COMMON_BLOCK_PCR<br>+ help<br>+ Intel Processor common P2SB driver<br>+<br>diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc<br>new file mode 100644<br>index 0000000..d78714b<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/p2sb/Makefile.inc<br>@@ -0,0 +1 @@<br>+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c<br>diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c<br>new file mode 100644<br>index 0000000..aa66467<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/p2sb/p2sb.c<br>@@ -0,0 +1,80 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2016 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <console/console.h><br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <device/pci_ids.h><br>+#include <rules.h><br>+#include <soc/iomap.h><br>+#include <soc/pci_devs.h><br>+#include <intelblocks/p2sb.h><br>+<br>+#define P2SB_E0 0xe0<br>+#define HIDE_BIT (1 << 0)<br>+<br>+static void p2sb_set_hide_bit(int hide)<br>+{<br>+ struct device *dev;<br>+ const uint16_t reg = P2SB_E0 + 1;<br>+ const uint8_t mask = HIDE_BIT;<br>+ uint8_t val;<br>+<br>+ dev = PCH_DEV_P2SB;<br>+<br>+ val = pci_read_config8(dev, reg);<br>+ val &= ~mask;<br>+ if (hide)<br>+ val |= mask;<br>+ pci_write_config8(dev, reg, val);<br>+}<br>+<br>+void p2sb_unhide(void)<br>+{<br>+ p2sb_set_hide_bit(0);<br>+}<br>+<br>+void p2sb_hide(void)<br>+{<br>+ p2sb_set_hide_bit(HIDE_BIT);<br>+}<br>+<br>+static void read_resources(struct device *dev)<br>+{<br>+ /*<br>+ * There's only one resource on the P2SB device. It's also already<br>+ * manually set to a fixed address in earlier boot stages.<br>+ */<br>+ mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB);<br>+}<br>+<br>+static const struct device_operations device_ops = {<br>+ .read_resources = read_resources,<br>+ .set_resources = DEVICE_NOOP,<br>+};<br>+<br>+static const unsigned short pci_device_ids[] = {<br>+ PCI_DEVICE_ID_INTEL_APL_P2SB,<br>+ PCI_DEVICE_ID_INTEL_GLK_P2SB,<br>+ PCI_DEVICE_ID_INTEL_CNL_P2SB,<br>+ 0,<br>+};<br>+<br>+static const struct pci_driver pmc __pci_driver = {<br>+ .ops = &device_ops,<br>+ .vendor = PCI_VENDOR_ID_INTEL,<br>+ .devices = pci_device_ids,<br>+};<br></pre><p>To view, visit <a href="https://review.coreboot.org/22189">change 22189</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie3f7036a5956e3db1662678aaf43023ff79ae10e </div>
<div style="display:none"> Gerrit-Change-Number: 22189 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>