<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22132">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[TEST]drivers/ati/ragexl: Remove dead code<br><br>Seems unused in the three.<br><br>Change-Id: I8a5308b6c7773d791d47832e620558394f1d727e<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>D src/drivers/ati/ragexl/Kconfig<br>D src/drivers/ati/ragexl/Makefile.inc<br>D src/drivers/ati/ragexl/atyfb.h<br>D src/drivers/ati/ragexl/fb.h<br>D src/drivers/ati/ragexl/fbcon.h<br>D src/drivers/ati/ragexl/mach64.h<br>D src/drivers/ati/ragexl/mach64_ct.c<br>D src/drivers/ati/ragexl/xlinit.c<br>8 files changed, 0 insertions(+), 3,950 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/22132/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/drivers/ati/ragexl/Kconfig b/src/drivers/ati/ragexl/Kconfig<br>deleted file mode 100644<br>index 86109b1..0000000<br>--- a/src/drivers/ati/ragexl/Kconfig<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config DRIVERS_ATI_RAGEXL<br>- bool<br>diff --git a/src/drivers/ati/ragexl/Makefile.inc b/src/drivers/ati/ragexl/Makefile.inc<br>deleted file mode 100644<br>index fbec414..0000000<br>--- a/src/drivers/ati/ragexl/Makefile.inc<br>+++ /dev/null<br>@@ -1 +0,0 @@<br>-ramstage-$(CONFIG_DRIVERS_ATI_RAGEXL) += xlinit.c<br>diff --git a/src/drivers/ati/ragexl/atyfb.h b/src/drivers/ati/ragexl/atyfb.h<br>deleted file mode 100644<br>index df8dd3d..0000000<br>--- a/src/drivers/ati/ragexl/atyfb.h<br>+++ /dev/null<br>@@ -1,407 +0,0 @@<br>-/*<br>- * ATI Frame Buffer Device Driver Core Definitions<br>- */<br>-<br>-#define PLL_CRTC_DECODE 0<br>-<br>-#define EINVAL -1<br>-<br>-#if CONFIG_CONSOLE_BTEXT<br>- /*<br>- * Elements of the hardware specific atyfb_par structure<br>- */<br>-struct crtc {<br>- u32 vxres;<br>- u32 vyres;<br>- u32 xoffset;<br>- u32 yoffset;<br>- u32 bpp;<br>- u32 h_tot_disp;<br>- u32 h_sync_strt_wid;<br>- u32 v_tot_disp;<br>- u32 v_sync_strt_wid;<br>- u32 off_pitch;<br>- u32 gen_cntl;<br>- u32 dp_pix_width; /* acceleration */<br>- u32 dp_chain_mask; /* acceleration */<br>-};<br>-#endif /* CONFIG_CONSOLE_BTEXT */<br>-#if 0<br>-struct pll_514 {<br>- u8 m;<br>- u8 n;<br>-};<br>-<br>-struct pll_18818<br>-{<br>- u32 program_bits;<br>- u32 locationAddr;<br>- u32 period_in_ps;<br>- u32 post_divider;<br>-};<br>-#endif<br>-struct pll_ct {<br>- u8 pll_ref_div;<br>- u8 pll_gen_cntl;<br>- u8 mclk_fb_div;<br>- u8 mclk_fb_mult; /* 2 or 4 */<br>- u8 sclk_fb_div;<br>- u8 pll_vclk_cntl;<br>- u8 vclk_post_div;<br>- u8 vclk_fb_div;<br>- u8 pll_ext_cntl;<br>- u8 spll_cntl2;<br>- u32 dsp_config; /* Mach64 GTB DSP */<br>- u32 dsp_on_off; /* Mach64 GTB DSP */<br>- u8 mclk_post_div_real;<br>- u8 xclk_post_div_real;<br>- u8 vclk_post_div_real;<br>-};<br>-<br>-union aty_pll {<br>- struct pll_ct ct;<br>-#if 0<br>- struct pll_514 ibm514;<br>- struct pll_18818 ics2595;<br>-#endif<br>-};<br>-<br>-<br>- /*<br>- * The hardware parameters for each card<br>- */<br>-struct atyfb_par {<br>-#if CONFIG_CONSOLE_BTEXT<br>- struct crtc crtc;<br>-#endif<br>- union aty_pll pll;<br>- u32 accel_flags;<br>-};<br>-#if 0<br>-struct aty_cursor {<br>- int enable;<br>- int on;<br>- int vbl_cnt;<br>- int blink_rate;<br>- u32 offset;<br>- struct {<br>- u16 x, y;<br>- } pos, hot, size;<br>- u32 color[2];<br>- u8 bits[8][64];<br>- u8 mask[8][64];<br>- u8 *ram;<br>- struct timer_list *timer;<br>-};<br>-#endif<br>-struct fb_info_aty {<br>-#if CONFIG_CONSOLE_BTEXT<br>-#if PLL_CRTC_DECODE==1<br>- struct fb_info fb_info;<br>-#endif<br>-#endif<br>-#if 0<br>- struct fb_info_aty *next;<br>- unsigned long ati_regbase_phys;<br>-#endif<br>- u8 *ati_regbase;<br>-#if 0<br>- unsigned long frame_buffer_phys;<br>-#endif<br>- unsigned long frame_buffer;<br>- unsigned long clk_wr_offset;<br>-#if 0<br>- struct pci_mmap_map *mmap_map;<br>- struct aty_cursor *cursor;<br>-#endif<br>- struct aty_cmap_regs *aty_cmap_regs;<br>-#if 0<br>- struct { u8 red, green, blue, pad; } palette[256];<br>-#endif<br>- struct atyfb_par default_par;<br>-#if PLL_CRTC_DECODE==1<br>- struct atyfb_par current_par;<br>-#endif<br>-<br>- u32 features;<br>- u32 total_vram;<br>- u32 ref_clk_per;<br>- u32 pll_per;<br>- u32 mclk_per;<br>- u32 xclk_per;<br>- u8 bus_type;<br>- u8 ram_type;<br>- u8 mem_refresh_rate;<br>-#if 0<br>- struct aty_dac_ops *dac_ops;<br>- struct aty_pll_ops *pll_ops;<br>- struct display disp;<br>- struct display_switch dispsw;<br>-#endif<br>-<br>-#if 0<br>- union {<br>-#ifdef FBCON_HAS_CFB16<br>- u16 cfb16[16];<br>-#endif<br>-#ifdef FBCON_HAS_CFB24<br>- u32 cfb24[16];<br>-#endif<br>-#ifdef FBCON_HAS_CFB32<br>- u32 cfb32[16];<br>-#endif<br>- } fbcon_cmap;<br>-#endif<br>- u8 blitter_may_be_busy;<br>-#if 0<br>-#ifdef __sparc__<br>- u8 mmaped;<br>- int open;<br>- int vtconsole;<br>- int consolecnt;<br>-#endif<br>-#ifdef CONFIG_PMAC_PBOOK<br>- unsigned char *save_framebuffer;<br>- unsigned long save_pll[64];<br>-#endif<br>-#endif<br>-};<br>-<br>-<br>- /*<br>- * ATI Mach64 features<br>- */<br>-<br>-#define M64_HAS(feature) ((info)->features & (M64F_##feature))<br>-<br>-#define M64F_RESET_3D 0x00000001<br>-#define M64F_MAGIC_FIFO 0x00000002<br>-#define M64F_GTB_DSP 0x00000004<br>-#define M64F_FIFO_24 0x00000008<br>-#define M64F_SDRAM_MAGIC_PLL 0x00000010<br>-#define M64F_MAGIC_POSTDIV 0x00000020<br>-#define M64F_INTEGRATED 0x00000040<br>-#define M64F_CT_BUS 0x00000080<br>-#define M64F_VT_BUS 0x00000100<br>-#define M64F_MOBIL_BUS 0x00000200<br>-#define M64F_GX 0x00000400<br>-#define M64F_CT 0x00000800<br>-#define M64F_VT 0x00001000<br>-#define M64F_GT 0x00002000<br>-#define M64F_MAGIC_VRAM_SIZE 0x00004000<br>-#define M64F_G3_PB_1_1 0x00008000<br>-#define M64F_G3_PB_1024x768 0x00010000<br>-#define M64F_EXTRA_BRIGHT 0x00020000<br>-#define M64F_LT_SLEEP 0x00040000<br>-#define M64F_XL_DLL 0x00080000<br>-#define M64F_MFB_TIMES_4 0x00100000<br>-<br>-<br>- /*<br>- * Register access<br>- */<br>-<br>-static inline u32 aty_ld_le32(int regindex,<br>- const struct fb_info_aty *info)<br>-{<br>- /* Hack for bloc 1, should be cleanly optimized by compiler */<br>- if (regindex >= 0x400)<br>- regindex -= 0x800;<br>-<br>-#ifdef ATARI<br>- return in_le32((volatile u32 *)(info->ati_regbase+regindex));<br>-#else<br>- return read32 (info->ati_regbase + regindex);<br>-#endif<br>-}<br>-<br>-static inline void aty_st_le32(int regindex, u32 val,<br>- const struct fb_info_aty *info)<br>-{<br>- /* Hack for bloc 1, should be cleanly optimized by compiler */<br>- if (regindex >= 0x400)<br>- regindex -= 0x800;<br>-<br>-#ifdef ATARI<br>- out_le32 (info->ati_regbase+regindex, val);<br>-#else<br>- write32 (info->ati_regbase + regindex, val);<br>-#endif<br>-}<br>-<br>-static inline u16 aty_ld_le16(int regindex,<br>- const struct fb_info_aty *info)<br>-{<br>- /* Hack for bloc 1, should be cleanly optimized by compiler */<br>- if (regindex >= 0x400)<br>- regindex -= 0x800;<br>-<br>-#if defined(__mc68000__)<br>- return le16_to_cpu(*((volatile u16 *)(info->ati_regbase+regindex)));<br>-#else<br>- return read16 (info->ati_regbase + regindex);<br>-#endif<br>-}<br>-<br>-static inline void aty_st_le16(int regindex, u16 val,<br>- const struct fb_info_aty *info)<br>-{<br>- /* Hack for bloc 1, should be cleanly optimized by compiler */<br>- if (regindex >= 0x400)<br>- regindex -= 0x800;<br>-<br>-#if defined(__mc68000__)<br>- *((volatile u16 *)(info->ati_regbase+regindex)) = cpu_to_le16(val);<br>-#else<br>- write16 (info->ati_regbase + regindex, val);<br>-#endif<br>-}<br>-<br>-static inline u8 aty_ld_8(int regindex,<br>- const struct fb_info_aty *info)<br>-{<br>- /* Hack for bloc 1, should be cleanly optimized by compiler */<br>- if (regindex >= 0x400)<br>- regindex -= 0x800;<br>-<br>-#ifdef ATARI<br>- return in_8 (info->ati_regbase + regindex);<br>-#else<br>- return read8 (info->ati_regbase + regindex);<br>-#endif<br>-}<br>-<br>-static inline void aty_st_8(int regindex, u8 val,<br>- const struct fb_info_aty *info)<br>-{<br>- /* Hack for bloc 1, should be cleanly optimized by compiler */<br>- if (regindex >= 0x400)<br>- regindex -= 0x800;<br>-<br>-#ifdef ATARI<br>- out_8 (info->ati_regbase + regindex, val);<br>-#else<br>- write8 (info->ati_regbase + regindex, val);<br>-#endif<br>-}<br>-<br>-static inline u8 aty_ld_pll(int offset, const struct fb_info_aty *info)<br>-{<br>- u8 res;<br>-<br>- /* write addr byte */<br>- aty_st_8(CLOCK_CNTL + 1, (offset << 2), info);<br>- /* read the register value */<br>- res = aty_ld_8(CLOCK_CNTL + 2, info);<br>- return res;<br>-}<br>-<br>-/*<br>- * CT family only.<br>- */<br>-static inline void aty_st_pll(int offset, u8 val,<br>- const struct fb_info_aty *info)<br>-{<br>- /* write addr byte */<br>- aty_st_8(CLOCK_CNTL + 1, (offset << 2) | PLL_WR_EN, info);<br>- /* write the register value */<br>- aty_st_8(CLOCK_CNTL + 2, val, info);<br>- aty_st_8(CLOCK_CNTL + 1, (offset << 2) & ~PLL_WR_EN, info);<br>-}<br>-<br>-<br>- /*<br>- * DAC operations<br>- */<br>-<br>-#if 0<br>-<br>-struct aty_dac_ops {<br>- int (*set_dac)(const struct fb_info_aty *info, const union aty_pll *pll,<br>- u32 bpp, u32 accel);<br>-};<br>-extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */<br>-extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */<br>-extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */<br>-extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */<br>-static struct aty_dac_ops aty_dac_ct; /* Integrated */<br>-<br>-#endif<br>-<br>- /*<br>- * Clock operations<br>- */<br>-<br>-#if 0<br>-struct aty_pll_ops {<br>- int (*var_to_pll)(const struct fb_info_aty *info, u32 vclk_per, u8 bpp,<br>- union aty_pll *pll);<br>-#if 0<br>- u32 (*pll_to_var)(const struct fb_info_aty *info,<br>- const union aty_pll *pll);<br>- void (*set_pll)(const struct fb_info_aty *info, const union aty_pll *pll);<br>-#endif<br>-};<br>-<br>-#endif<br>-<br>-#if 0<br>-extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */<br>-extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */<br>-extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */<br>-extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */<br>-extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */<br>-extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */<br>-#endif<br>-#if 0<br>-static struct aty_pll_ops aty_pll_ct; /* Integrated */<br>-<br>-static void aty_set_pll_ct(const struct fb_info_aty *info,<br>- const union aty_pll *pll);<br>-<br>-static void aty_calc_pll_ct(const struct fb_info_aty *info,<br>- struct pll_ct *pll);<br>-#endif<br>-#if 0<br>- /*<br>- * Hardware cursor support<br>- */<br>-extern struct aty_cursor *aty_init_cursor(struct fb_info_aty *fb);<br>-extern void atyfb_cursor(struct display *p, int mode, int x, int y);<br>-extern void aty_set_cursor_color(struct fb_info_aty *fb);<br>-extern void aty_set_cursor_shape(struct fb_info_aty *fb);<br>-extern int atyfb_set_font(struct display *d, int width, int height);<br>-#endif<br>- /*<br>- * Hardware acceleration<br>- */<br>-<br>-static inline void wait_for_fifo(u16 entries, const struct fb_info_aty *info)<br>-{<br>- while ((aty_ld_le32(FIFO_STAT, info) & 0xffff) ><br>- ((u32)(0x8000 >> entries)));<br>-}<br>-<br>-static inline void wait_for_idle(struct fb_info_aty *info)<br>-{<br>- wait_for_fifo(16, info);<br>- while ((aty_ld_le32(GUI_STAT, info) & 1)!= 0);<br>- info->blitter_may_be_busy = 0;<br>-}<br>-#if 0<br>-extern void aty_reset_engine(const struct fb_info_aty *info);<br>-extern void aty_init_engine(const struct atyfb_par *par,<br>- struct fb_info_aty *info);<br>-extern void aty_rectfill(int dstx, int dsty, u32 width, u32 height,<br>- u32 color, struct fb_info_aty *info);<br>-<br>-<br>- /*<br>- * Text console acceleration<br>- */<br>-<br>-extern const struct display_switch fbcon_aty8;<br>-extern const struct display_switch fbcon_aty16;<br>-extern const struct display_switch fbcon_aty24;<br>-extern const struct display_switch fbcon_aty32;<br>-#endif<br>diff --git a/src/drivers/ati/ragexl/fb.h b/src/drivers/ati/ragexl/fb.h<br>deleted file mode 100644<br>index 8daf7ba..0000000<br>--- a/src/drivers/ati/ragexl/fb.h<br>+++ /dev/null<br>@@ -1,344 +0,0 @@<br>-#ifndef _LINUX_FB_H<br>-#define _LINUX_FB_H<br>-<br>-#define u32 uint32_t<br>-#define u16 uint16_t<br>-#define u8 uint8_t<br>-#define s16 short<br>-<br>-/* Definitions of frame buffers */<br>-<br>-#define FB_MAJOR 29<br>-#define FB_MAX 32 /* sufficient for now */<br>-<br>-/* ioctls<br>- * 0x46 is 'F' */<br>-#define FBIOGET_VSCREENINFO 0x4600<br>-#define FBIOPUT_VSCREENINFO 0x4601<br>-#define FBIOGET_FSCREENINFO 0x4602<br>-#define FBIOGETCMAP 0x4604<br>-#define FBIOPUTCMAP 0x4605<br>-#define FBIOPAN_DISPLAY 0x4606<br>-/* 0x4607-0x460B are defined below */<br>-/* #define FBIOGET_MONITORSPEC 0x460C */<br>-/* #define FBIOPUT_MONITORSPEC 0x460D */<br>-/* #define FBIOSWITCH_MONIBIT 0x460E */<br>-#define FBIOGET_CON2FBMAP 0x460F<br>-#define FBIOPUT_CON2FBMAP 0x4610<br>-#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */<br>-#define FBIOGET_VBLANK _IOR('F', 0x12, struct fb_vblank)<br>-#define FBIO_ALLOC 0x4613<br>-#define FBIO_FREE 0x4614<br>-#define FBIOGET_GLYPH 0x4615<br>-#define FBIOGET_HWCINFO 0x4616<br>-#define FBIOPUT_MODEINFO 0x4617<br>-#define FBIOGET_DISPINFO 0x4618<br>-<br>-<br>-#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */<br>-#define FB_TYPE_PLANES 1 /* Non interleaved planes */<br>-#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */<br>-#define FB_TYPE_TEXT 3 /* Text/attributes */<br>-#define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */<br>-<br>-#define FB_AUX_TEXT_MDA 0 /* Monochrome text */<br>-#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */<br>-#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */<br>-#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */<br>-#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */<br>-<br>-#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */<br>-#define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */<br>-#define FB_AUX_VGA_PLANES_CFB8 2 /* CFB8 in planes (VGA) */<br>-<br>-#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */<br>-#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */<br>-#define FB_VISUAL_TRUECOLOR 2 /* True color */<br>-#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */<br>-#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */<br>-#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */<br>-<br>-#define FB_ACCEL_NONE 0 /* no hardware accelerator */<br>-#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */<br>-#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */<br>-#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */<br>-#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */<br>-#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */<br>-#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */<br>-#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */<br>-#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */<br>-#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */<br>-#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */<br>-#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */<br>-#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */<br>-#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */<br>-#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */<br>-#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */<br>-#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */<br>-#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */<br>-#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */<br>-#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */<br>-#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */<br>-#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */<br>-#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */<br>-#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */<br>-#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */<br>-#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */<br>-#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */<br>-#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */<br>-#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */<br>-#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */<br>-#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */<br>-#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */<br>-#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */<br>-#define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */<br>-#define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */<br>-#define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */<br>-#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */<br>-#define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */<br>-#define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */<br>-#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */<br>-#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */<br>-<br>-#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */<br>-#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */<br>-#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */<br>-#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */<br>-#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */<br>-#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */<br>-#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */<br>-#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */<br>-#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */<br>-<br>-#if 0<br>-<br>-struct fb_fix_screeninfo {<br>- char id[16]; /* identification string eg "TT Builtin" */<br>- unsigned long smem_start; /* Start of frame buffer mem */<br>- /* (physical address) */<br>- u32 smem_len; /* Length of frame buffer mem */<br>- u32 type; /* see FB_TYPE_* */<br>- u32 type_aux; /* Interleave for interleaved Planes */<br>- u32 visual; /* see FB_VISUAL_* */<br>- u16 xpanstep; /* zero if no hardware panning */<br>- u16 ypanstep; /* zero if no hardware panning */<br>- u16 ywrapstep; /* zero if no hardware ywrap */<br>- u32 line_length; /* length of a line in bytes */<br>- u8 *mmio_start; /* Start of Memory Mapped I/O */<br>- /* (physical address) */<br>- u32 mmio_len; /* Length of Memory Mapped I/O */<br>- u32 accel; /* Type of acceleration available */<br>- u16 reserved[3]; /* Reserved for future compatibility */<br>-};<br>-<br>-#endif<br>-<br>-/* Interpretation of offset for color fields: All offsets are from the right,<br>- * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you<br>- * can use the offset as right argument to <<). A pixel afterwards is a bit<br>- * stream and is written to video memory as that unmodified. This implies<br>- * big-endian byte order if bits_per_pixel is greater than 8.<br>- */<br>-struct fb_bitfield {<br>- u32 offset; /* beginning of bitfield */<br>- u32 length; /* length of bitfield */<br>- u32 msb_right; /* != 0 : Most significant bit is */<br>- /* right */<br>-};<br>-<br>-#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */<br>-<br>-#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/<br>-#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */<br>-#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */<br>-#define FB_ACTIVATE_MASK 15<br>- /* values */<br>-#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */<br>-#define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */<br>-#define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */<br>-<br>-#define FB_ACCELF_TEXT 1 /* text mode acceleration */<br>-<br>-#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */<br>-#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */<br>-#define FB_SYNC_EXT 4 /* external sync */<br>-#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */<br>-#define FB_SYNC_BROADCAST 16 /* broadcast video timings */<br>- /* vtotal = 144d/288n/576i => PAL */<br>- /* vtotal = 121d/242n/484i => NTSC */<br>-#define FB_SYNC_ON_GREEN 32 /* sync on green */<br>-<br>-#define FB_VMODE_NONINTERLACED 0 /* non interlaced */<br>-#define FB_VMODE_INTERLACED 1 /* interlaced */<br>-#define FB_VMODE_DOUBLE 2 /* double scan */<br>-#define FB_VMODE_MASK 255<br>-<br>-#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */<br>-#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */<br>-#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */<br>-<br>-struct fb_var_screeninfo {<br>- u32 xres; /* visible resolution */<br>- u32 yres;<br>- u32 xres_virtual; /* virtual resolution */<br>- u32 yres_virtual;<br>- u32 xoffset; /* offset from virtual to visible */<br>- u32 yoffset; /* resolution */<br>-<br>- u32 bits_per_pixel; /* guess what */<br>- u32 grayscale; /* != 0 Graylevels instead of colors */<br>-<br>- struct fb_bitfield red; /* bitfield in fb mem if true color, */<br>- struct fb_bitfield green; /* else only length is significant */<br>- struct fb_bitfield blue;<br>- struct fb_bitfield transp; /* transparency */<br>-<br>- u32 nonstd; /* != 0 Non standard pixel format */<br>-<br>- u32 activate; /* see FB_ACTIVATE_* */<br>-<br>- u32 height; /* height of picture in mm */<br>- u32 width; /* width of picture in mm */<br>-<br>- u32 accel_flags; /* acceleration flags (hints) */<br>-<br>- /* Timing: All values in pixclocks, except pixclock (of course) */<br>- u32 pixclock; /* pixel clock in ps (pico seconds) */<br>- u32 left_margin; /* time from sync to picture */<br>- u32 right_margin; /* time from picture to sync */<br>- u32 upper_margin; /* time from sync to picture */<br>- u32 lower_margin;<br>- u32 hsync_len; /* length of horizontal sync */<br>- u32 vsync_len; /* length of vertical sync */<br>- u32 sync; /* see FB_SYNC_* */<br>- u32 vmode; /* see FB_VMODE_* */<br>- u32 reserved[6]; /* Reserved for future compatibility */<br>-};<br>-<br>-struct fb_cmap {<br>- u32 start; /* First entry */<br>- u32 len; /* Number of entries */<br>- u16 *red; /* Red values */<br>- u16 *green;<br>- u16 *blue;<br>- u16 *transp; /* transparency, can be NULL */<br>-};<br>-<br>-struct fb_con2fbmap {<br>- u32 console;<br>- u32 framebuffer;<br>-};<br>-<br>-/* VESA Blanking Levels */<br>-#define VESA_NO_BLANKING 0<br>-#define VESA_VSYNC_SUSPEND 1<br>-#define VESA_HSYNC_SUSPEND 2<br>-#define VESA_POWERDOWN 3<br>-<br>-struct fb_monspecs {<br>- u32 hfmin; /* hfreq lower limit (Hz) */<br>- u32 hfmax; /* hfreq upper limit (Hz) */<br>- u16 vfmin; /* vfreq lower limit (Hz) */<br>- u16 vfmax; /* vfreq upper limit (Hz) */<br>- unsigned dpms : 1; /* supports DPMS */<br>-};<br>-<br>-#define FB_VBLANK_VBLANKING 0x001 /* currently in a vertical blank */<br>-#define FB_VBLANK_HBLANKING 0x002 /* currently in a horizontal blank */<br>-#define FB_VBLANK_HAVE_VBLANK 0x004 /* vertical blanks can be detected */<br>-#define FB_VBLANK_HAVE_HBLANK 0x008 /* horizontal blanks can be detected */<br>-#define FB_VBLANK_HAVE_COUNT 0x010 /* global retrace counter is available */<br>-#define FB_VBLANK_HAVE_VCOUNT 0x020 /* the vcount field is valid */<br>-#define FB_VBLANK_HAVE_HCOUNT 0x040 /* the hcount field is valid */<br>-#define FB_VBLANK_VSYNCING 0x080 /* currently in a vsync */<br>-#define FB_VBLANK_HAVE_VSYNC 0x100 /* verical syncs can be detected */<br>-<br>-struct fb_vblank {<br>- u32 flags; /* FB_VBLANK flags */<br>- u32 count; /* counter of retraces since boot */<br>- u32 vcount; /* current scanline position */<br>- u32 hcount; /* current scandot position */<br>- u32 reserved[4]; /* reserved for future compatibility */<br>-};<br>-<br>-<br>-#if 1<br>-<br>-#define FBCMD_GET_CURRENTPAR 0xDEAD0005<br>-#define FBCMD_SET_CURRENTPAR 0xDEAD8005<br>-<br>-#endif<br>-<br>-<br>-<br>-/*<br>- * Hardware Cursor<br>- */<br>-<br>-#define FBIOGET_FCURSORINFO 0x4607<br>-#define FBIOGET_VCURSORINFO 0x4608<br>-#define FBIOPUT_VCURSORINFO 0x4609<br>-#define FBIOGET_CURSORSTATE 0x460A<br>-#define FBIOPUT_CURSORSTATE 0x460B<br>-<br>-<br>-struct fb_fix_cursorinfo {<br>- u16 crsr_width; /* width and height of the cursor in */<br>- u16 crsr_height; /* pixels (zero if no cursor) */<br>- u16 crsr_xsize; /* cursor size in display pixels */<br>- u16 crsr_ysize;<br>- u16 crsr_color1; /* colormap entry for cursor color1 */<br>- u16 crsr_color2; /* colormap entry for cursor color2 */<br>-};<br>-<br>-struct fb_var_cursorinfo {<br>- u16 width;<br>- u16 height;<br>- u16 xspot;<br>- u16 yspot;<br>- u8 data[1]; /* field with [height][width] */<br>-};<br>-<br>-struct fb_cursorstate {<br>- s16 xoffset;<br>- s16 yoffset;<br>- u16 mode;<br>-};<br>-<br>-<br>-struct fb_info {<br>- char modename[40]; /* default video mode */<br>-// kdev_t node;<br>- int flags;<br>- int open; /* Has this been open already ? */<br>- struct fb_var_screeninfo var; /* Current var */<br>-#if 0<br>- struct fb_fix_screeninfo fix; /* Current fix */<br>-#endif<br>- struct fb_monspecs monspecs; /* Current Monitor specs */<br>- struct fb_cmap cmap; /* Current cmap */<br>-// struct fb_ops *fbops;<br>- char *screen_base; /* Virtual address */<br>- struct display *disp; /* initial display variable */<br>-// struct vc_data *display_fg; /* Console visible on this display */<br>- char fontname[40]; /* default font name */<br>-#if 0<br>- devfs_handle_t devfs_handle; /* Devfs handle for new name */<br>- devfs_handle_t devfs_lhandle; /* Devfs handle for compat. symlink */<br>- int (*changevar)(int); /* tell console var has changed */<br>- int (*switch_con)(int, struct fb_info*);<br>- /* tell fb to switch consoles */<br>- int (*updatevar)(int, struct fb_info*);<br>- /* tell fb to update the vars */<br>- void (*blank)(int, struct fb_info*); /* tell fb to (un)blank the screen */<br>- /* arg = 0: unblank */<br>- /* arg > 0: VESA level (arg-1) */<br>-#endif<br>- void *pseudo_palette; /* Fake palette of 16 colors and<br>- the cursor's color for non<br>- palette mode */<br>-/* From here on everything is device dependent */<br>- void *par;<br>-};<br>-<br>-#endif /* _LINUX_FB_H */<br>diff --git a/src/drivers/ati/ragexl/fbcon.h b/src/drivers/ati/ragexl/fbcon.h<br>deleted file mode 100644<br>index d6f122c..0000000<br>--- a/src/drivers/ati/ragexl/fbcon.h<br>+++ /dev/null<br>@@ -1,139 +0,0 @@<br>-/*<br>- * linux/drivers/video/fbcon.h -- Low level frame buffer based console driver<br>- *<br>- * Copyright (C) 1997 Geert Uytterhoeven<br>- *<br>- * This file is subject to the terms and conditions of the GNU General Public<br>- * License. See the file COPYING in the main directory of this archive<br>- * for more details.<br>- */<br>-<br>-#ifndef _VIDEO_FBCON_H<br>-#define _VIDEO_FBCON_H<br>-<br>-struct display {<br>- /* Filled in by the frame buffer device */<br>- struct fb_var_screeninfo var; /* variable infos. yoffset and vmode */<br>- /* are updated by fbcon.c */<br>- struct fb_cmap cmap; /* colormap */<br>- char *screen_base; /* pointer to top of virtual screen */<br>- /* (virtual address) */<br>- int visual;<br>- int type; /* see FB_TYPE_* */<br>- int type_aux; /* Interleave for interleaved Planes */<br>- u16 ypanstep; /* zero if no hardware ypan */<br>- u16 ywrapstep; /* zero if no hardware ywrap */<br>- u32 line_length; /* length of a line in bytes */<br>- u16 can_soft_blank; /* zero if no hardware blanking */<br>- u16 inverse; /* != 0 text black on white as default */<br>-<br>- /* Filled in by the low-level console driver */<br>-<br>- struct vc_data *conp; /* pointer to console data */<br>- int vrows; /* number of virtual rows */<br>- unsigned short cursor_x; /* current cursor position */<br>- unsigned short cursor_y;<br>- int fgcol; /* text colors */<br>- int bgcol;<br>- u32 next_line; /* offset to one line below */<br>- u32 next_plane; /* offset to next plane */<br>- u8 *fontdata; /* Font associated to this display */<br>- unsigned short _fontheightlog;<br>- unsigned short _fontwidthlog;<br>- unsigned short _fontheight;<br>- unsigned short _fontwidth;<br>- int userfont; /* != 0 if fontdata kmalloc()ed */<br>- u16 scrollmode; /* Scroll Method */<br>- short yscroll; /* Hardware scrolling */<br>- unsigned char fgshift, bgshift;<br>- unsigned short charmask; /* 0xff or 0x1ff */<br>-};<br>-<br>-<br>-#define fontheight(p) ((p)->_fontheight)<br>-#define fontheightlog(p) ((p)->_fontheightlog)<br>-<br>-#ifdef FBCON_FONTWIDTH8_ONLY<br>-<br>-/* fontwidth w is supported by dispsw */<br>-#define FONTWIDTH(w) (1 << ((8) - 1))<br>-/* fontwidths w1-w2 inclusive are supported by dispsw */<br>-#define FONTWIDTHRANGE(w1,w2) FONTWIDTH(8)<br>-<br>-#define fontwidth(p) (8)<br>-#define fontwidthlog(p) (0)<br>-<br>-#else<br>-<br>-/* fontwidth w is supported by dispsw */<br>-#define FONTWIDTH(w) (1 << ((w) - 1))<br>-/* fontwidths w1-w2 inclusive are supported by dispsw */<br>-#define FONTWIDTHRANGE(w1,w2) (FONTWIDTH(w2+1) - FONTWIDTH(w1))<br>-<br>-#define fontwidth(p) ((p)->_fontwidth)<br>-#define fontwidthlog(p) ((p)->_fontwidthlog)<br>-<br>-#endif<br>-<br>- /*<br>- * Attribute Decoding<br>- */<br>-<br>-/* Color */<br>-#define attr_fgcol(p,s) \<br>- (((s) >> ((p)->fgshift)) & 0x0f)<br>-#define attr_bgcol(p,s) \<br>- (((s) >> ((p)->bgshift)) & 0x0f)<br>-#define attr_bgcol_ec(p,conp) \<br>- ((conp) ? (((conp)->vc_video_erase_char >> ((p)->bgshift)) & 0x0f) : 0)<br>-<br>-/* Monochrome */<br>-#define attr_bold(p,s) \<br>- ((s) & 0x200)<br>-#define attr_reverse(p,s) \<br>- (((s) & 0x800) ^ ((p)->inverse ? 0x800 : 0))<br>-#define attr_underline(p,s) \<br>- ((s) & 0x400)<br>-#define attr_blink(p,s) \<br>- ((s) & 0x8000)<br>-<br>- /*<br>- * Scroll Method<br>- */<br>-<br>-/* Internal flags */<br>-#define __SCROLL_YPAN 0x001<br>-#define __SCROLL_YWRAP 0x002<br>-#define __SCROLL_YMOVE 0x003<br>-#define __SCROLL_YREDRAW 0x004<br>-#define __SCROLL_YMASK 0x00f<br>-#define __SCROLL_YFIXED 0x010<br>-#define __SCROLL_YNOMOVE 0x020<br>-#define __SCROLL_YPANREDRAW 0x040<br>-#define __SCROLL_YNOPARTIAL 0x080<br>-<br>-/* Only these should be used by the drivers */<br>-/* Which one should you use? If you have a fast card and slow bus,<br>- then probably just 0 to indicate fbcon should choose between<br>- YWRAP/YPAN+MOVE/YMOVE. On the other side, if you have a fast bus<br>- and even better if your card can do fonting (1->8/32bit painting),<br>- you should consider either SCROLL_YREDRAW (if your card is<br>- able to do neither YPAN/YWRAP), or SCROLL_YNOMOVE.<br>- The best is to test it with some real life scrolling (usually, not<br>- all lines on the screen are filled completely with non-space characters,<br>- and REDRAW performs much better on such lines, so don't cat a file<br>- with every line covering all screen columns, it would not be the right<br>- benchmark).<br>- */<br>-#define SCROLL_YREDRAW (__SCROLL_YFIXED|__SCROLL_YREDRAW)<br>-#define SCROLL_YNOMOVE (__SCROLL_YNOMOVE|__SCROLL_YPANREDRAW)<br>-<br>-/* SCROLL_YNOPARTIAL, used in combination with the above, is for video<br>- cards which can not handle using panning to scroll a portion of the<br>- screen without excessive flicker. Panning will only be used for<br>- whole screens.<br>- */<br>-/* Namespace consistency */<br>-#define SCROLL_YNOPARTIAL __SCROLL_YNOPARTIAL<br>-<br>-#endif /* _VIDEO_FBCON_H */<br>diff --git a/src/drivers/ati/ragexl/mach64.h b/src/drivers/ati/ragexl/mach64.h<br>deleted file mode 100644<br>index 7400b43..0000000<br>--- a/src/drivers/ati/ragexl/mach64.h<br>+++ /dev/null<br>@@ -1,1169 +0,0 @@<br>-/*<br>- * ATI Mach64 Register Definitions<br>- *<br>- * Copyright (C) 1997 Michael AK Tesch<br>- * written with much help from Jon Howell<br>- *<br>- * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License<br>- * as published by the Free Software Foundation; either version<br>- * 2 of the License, or (at your option) any later version.<br>- */<br>-<br>-/*<br>- * most of the rest of this file comes from ATI sample code<br>- */<br>-#ifndef REGMACH64_H<br>-#define REGMACH64_H<br>-<br>-/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */<br>-<br>-/* Accelerator CRTC */<br>-#define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */<br>-#define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */<br>-#define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */<br>-#define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */<br>-#define CRTC_H_SYNC_STRT 0x0004<br>-#define CRTC2_H_SYNC_STRT 0x0004<br>-#define CRTC_H_SYNC_DLY 0x0005<br>-#define CRTC2_H_SYNC_DLY 0x0005<br>-#define CRTC_H_SYNC_WID 0x0006<br>-#define CRTC2_H_SYNC_WID 0x0006<br>-#define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */<br>-#define CRTC2_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */<br>-#define CRTC_V_TOTAL 0x0008<br>-#define CRTC2_V_TOTAL 0x0008<br>-#define CRTC_V_DISP 0x000A<br>-#define CRTC2_V_DISP 0x000A<br>-#define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */<br>-#define CRTC2_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */<br>-#define CRTC_V_SYNC_STRT 0x000C<br>-#define CRTC2_V_SYNC_STRT 0x000C<br>-#define CRTC_V_SYNC_WID 0x000E<br>-#define CRTC2_V_SYNC_WID 0x000E<br>-#define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */<br>-#define CRTC2_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */<br>-#define CRTC_OFF_PITCH 0x0014 /* Dword offset 0_05 */<br>-#define CRTC_OFFSET 0x0014<br>-#define CRTC_PITCH 0x0016<br>-#define CRTC_INT_CNTL 0x0018 /* Dword offset 0_06 */<br>-#define CRTC_GEN_CNTL 0x001C /* Dword offset 0_07 */<br>-#define CRTC_PIX_WIDTH 0x001D<br>-#define CRTC_FIFO 0x001E<br>-#define CRTC_EXT_DISP 0x001F<br>-<br>-/* Memory Buffer Control */<br>-#define DSP_CONFIG 0x0020 /* Dword offset 0_08 */<br>-#define PM_DSP_CONFIG 0x0020 /* Dword offset 0_08 (Mobility Only) */<br>-#define DSP_ON_OFF 0x0024 /* Dword offset 0_09 */<br>-#define PM_DSP_ON_OFF 0x0024 /* Dword offset 0_09 (Mobility Only) */<br>-#define TIMER_CONFIG 0x0028 /* Dword offset 0_0A */<br>-#define MEM_BUF_CNTL 0x002C /* Dword offset 0_0B */<br>-#define MEM_ADDR_CONFIG 0x0034 /* Dword offset 0_0D */<br>-<br>-/* Accelerator CRTC */<br>-#define CRT_TRAP 0x0038 /* Dword offset 0_0E */<br>-<br>-#define I2C_CNTL_0 0x003C /* Dword offset 0_0F */<br>-<br>-/* Overscan */<br>-#define OVR_CLR 0x0040 /* Dword offset 0_10 */<br>-#define OVR2_CLR 0x0040 /* Dword offset 0_10 */<br>-#define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */<br>-#define OVR2_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */<br>-#define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */<br>-#define OVR2_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */<br>-<br>-/* Memory Buffer Control */<br>-#define VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 */<br>-#define PM_VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 (Mobility Only) */<br>-#define VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 */<br>-#define PM_VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 (Mobility Only) */<br>-#define DSP2_CONFIG 0x0054 /* Dword offset 0_15 */<br>-#define PM_DSP2_CONFIG 0x0054 /* Dword offset 0_15 (Mobility Only) */<br>-#define DSP2_ON_OFF 0x0058 /* Dword offset 0_16 */<br>-#define PM_DSP2_ON_OFF 0x0058 /* Dword offset 0_16 (Mobility Only) */<br>-<br>-/* Accelerator CRTC */<br>-#define CRTC2_OFF_PITCH 0x005C /* Dword offset 0_17 */<br>-<br>-/* Hardware Cursor */<br>-#define CUR_CLR0 0x0060 /* Dword offset 0_18 */<br>-#define CUR2_CLR0 0x0060 /* Dword offset 0_18 */<br>-#define CUR_CLR1 0x0064 /* Dword offset 0_19 */<br>-#define CUR2_CLR1 0x0064 /* Dword offset 0_19 */<br>-#define CUR_OFFSET 0x0068 /* Dword offset 0_1A */<br>-#define CUR2_OFFSET 0x0068 /* Dword offset 0_1A */<br>-#define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */<br>-#define CUR2_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */<br>-#define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */<br>-#define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */<br>-<br>-#define CFG_PANEL_LG 0x0074 /* Dword offset 0_1D */<br>-<br>-/* General I/O Control */<br>-#define GP_IO 0x0078 /* Dword offset 0_1E */<br>-<br>-/* Test and Debug */<br>-#define HW_DEBUG 0x007C /* Dword offset 0_1F */<br>-<br>-/* Scratch Pad and Test */<br>-#define SCRATCH_REG0 0x0080 /* Dword offset 0_20 */<br>-#define SCRATCH_REG1 0x0084 /* Dword offset 0_21 */<br>-#define SCRATCH_REG2 0x0088 /* Dword offset 0_22 */<br>-#define SCRATCH_REG3 0x008C /* Dword offset 0_23 */<br>-<br>-/* Clock Control */<br>-#define CLOCK_CNTL 0x0090 /* Dword offset 0_24 */<br>-#define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */<br>-<br>-/* Configuration */<br>-#define CFG_STAT1 0x0094 /* Dword offset 0_25 */<br>-#define CFG_STAT2 0x0098 /* Dword offset 0_26 */<br>-<br>-/* Bus Control */<br>-#define BUS_CNTL 0x00A0 /* Dword offset 0_28 */<br>-<br>-#define LCD_INDEX 0x00A4 /* Dword offset 0_29 */<br>-#define LCD_DATA 0x00A8 /* Dword offset 0_2A */<br>-<br>-/* Memory Control */<br>-#define EXT_MEM_CNTL 0x00AC /* Dword offset 0_2B */<br>-#define MEM_CNTL 0x00B0 /* Dword offset 0_2C */<br>-#define MEM_VGA_WP_SEL 0x00B4 /* Dword offset 0_2D */<br>-#define MEM_VGA_RP_SEL 0x00B8 /* Dword offset 0_2E */<br>-<br>-#define I2C_CNTL_1 0x00BC /* Dword offset 0_2F */<br>-<br>-/* DAC Control */<br>-#define DAC_REGS 0x00C0 /* Dword offset 0_30 */<br>-#define DAC_W_INDEX 0x00C0 /* Dword offset 0_30 */<br>-#define DAC_DATA 0x00C1 /* Dword offset 0_30 */<br>-#define DAC_MASK 0x00C2 /* Dword offset 0_30 */<br>-#define DAC_R_INDEX 0x00C3 /* Dword offset 0_30 */<br>-#define DAC_CNTL 0x00C4 /* Dword offset 0_31 */<br>-<br>-#define EXT_DAC_REGS 0x00C8 /* Dword offset 0_32 */<br>-<br>-/* Test and Debug */<br>-#define GEN_TEST_CNTL 0x00D0 /* Dword offset 0_34 */<br>-<br>-/* Custom Macros */<br>-#define CUSTOM_MACRO_CNTL 0x00D4 /* Dword offset 0_35 */<br>-<br>-#define LCD_GEN_CNTL_LG 0x00D4 /* Dword offset 0_35 */<br>-<br>-#define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */<br>-<br>-/* Configuration */<br>-#define CFG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */<br>-#define CFG_CHIP_ID 0x00E0 /* Dword offset 0_38 */<br>-#define CFG_STAT0 0x00E4 /* Dword offset 0_39 */<br>-<br>-/* Test and Debug */<br>-#define CRC_SIG 0x00E8 /* Dword offset 0_3A */<br>-#define CRC2_SIG 0x00E8 /* Dword offset 0_3A */<br>-<br>-<br>-/* GUI MEMORY MAPPED Registers */<br>-<br>-/* Draw Engine Destination Trajectory */<br>-#define DST_OFF_PITCH 0x0100 /* Dword offset 0_40 */<br>-#define DST_X 0x0104 /* Dword offset 0_41 */<br>-#define DST_Y 0x0108 /* Dword offset 0_42 */<br>-#define DST_Y_X 0x010C /* Dword offset 0_43 */<br>-#define DST_WIDTH 0x0110 /* Dword offset 0_44 */<br>-#define DST_HEIGHT 0x0114 /* Dword offset 0_45 */<br>-#define DST_HEIGHT_WIDTH 0x0118 /* Dword offset 0_46 */<br>-#define DST_X_WIDTH 0x011C /* Dword offset 0_47 */<br>-#define DST_BRES_LNTH 0x0120 /* Dword offset 0_48 */<br>-#define DST_BRES_ERR 0x0124 /* Dword offset 0_49 */<br>-#define DST_BRES_INC 0x0128 /* Dword offset 0_4A */<br>-#define DST_BRES_DEC 0x012C /* Dword offset 0_4B */<br>-#define DST_CNTL 0x0130 /* Dword offset 0_4C */<br>-#define DST_Y_X__ALIAS__ 0x0134 /* Dword offset 0_4D */<br>-#define TRAIL_BRES_ERR 0x0138 /* Dword offset 0_4E */<br>-#define TRAIL_BRES_INC 0x013C /* Dword offset 0_4F */<br>-#define TRAIL_BRES_DEC 0x0140 /* Dword offset 0_50 */<br>-#define LEAD_BRES_LNTH 0x0144 /* Dword offset 0_51 */<br>-#define Z_OFF_PITCH 0x0148 /* Dword offset 0_52 */<br>-#define Z_CNTL 0x014C /* Dword offset 0_53 */<br>-#define ALPHA_TST_CNTL 0x0150 /* Dword offset 0_54 */<br>-#define SECONDARY_STW_EXP 0x0158 /* Dword offset 0_56 */<br>-#define SECONDARY_S_X_INC 0x015C /* Dword offset 0_57 */<br>-#define SECONDARY_S_Y_INC 0x0160 /* Dword offset 0_58 */<br>-#define SECONDARY_S_START 0x0164 /* Dword offset 0_59 */<br>-#define SECONDARY_W_X_INC 0x0168 /* Dword offset 0_5A */<br>-#define SECONDARY_W_Y_INC 0x016C /* Dword offset 0_5B */<br>-#define SECONDARY_W_START 0x0170 /* Dword offset 0_5C */<br>-#define SECONDARY_T_X_INC 0x0174 /* Dword offset 0_5D */<br>-#define SECONDARY_T_Y_INC 0x0178 /* Dword offset 0_5E */<br>-#define SECONDARY_T_START 0x017C /* Dword offset 0_5F */<br>-<br>-/* Draw Engine Source Trajectory */<br>-#define SRC_OFF_PITCH 0x0180 /* Dword offset 0_60 */<br>-#define SRC_X 0x0184 /* Dword offset 0_61 */<br>-#define SRC_Y 0x0188 /* Dword offset 0_62 */<br>-#define SRC_Y_X 0x018C /* Dword offset 0_63 */<br>-#define SRC_WIDTH1 0x0190 /* Dword offset 0_64 */<br>-#define SRC_HEIGHT1 0x0194 /* Dword offset 0_65 */<br>-#define SRC_HEIGHT1_WIDTH1 0x0198 /* Dword offset 0_66 */<br>-#define SRC_X_START 0x019C /* Dword offset 0_67 */<br>-#define SRC_Y_START 0x01A0 /* Dword offset 0_68 */<br>-#define SRC_Y_X_START 0x01A4 /* Dword offset 0_69 */<br>-#define SRC_WIDTH2 0x01A8 /* Dword offset 0_6A */<br>-#define SRC_HEIGHT2 0x01AC /* Dword offset 0_6B */<br>-#define SRC_HEIGHT2_WIDTH2 0x01B0 /* Dword offset 0_6C */<br>-#define SRC_CNTL 0x01B4 /* Dword offset 0_6D */<br>-<br>-#define SCALE_OFF 0x01C0 /* Dword offset 0_70 */<br>-#define SECONDARY_SCALE_OFF 0x01C4 /* Dword offset 0_71 */<br>-<br>-#define TEX_0_OFF 0x01C0 /* Dword offset 0_70 */<br>-#define TEX_1_OFF 0x01C4 /* Dword offset 0_71 */<br>-#define TEX_2_OFF 0x01C8 /* Dword offset 0_72 */<br>-#define TEX_3_OFF 0x01CC /* Dword offset 0_73 */<br>-#define TEX_4_OFF 0x01D0 /* Dword offset 0_74 */<br>-#define TEX_5_OFF 0x01D4 /* Dword offset 0_75 */<br>-#define TEX_6_OFF 0x01D8 /* Dword offset 0_76 */<br>-#define TEX_7_OFF 0x01DC /* Dword offset 0_77 */<br>-<br>-#define SCALE_WIDTH 0x01DC /* Dword offset 0_77 */<br>-#define SCALE_HEIGHT 0x01E0 /* Dword offset 0_78 */<br>-<br>-#define TEX_8_OFF 0x01E0 /* Dword offset 0_78 */<br>-#define TEX_9_OFF 0x01E4 /* Dword offset 0_79 */<br>-#define TEX_10_OFF 0x01E8 /* Dword offset 0_7A */<br>-#define S_Y_INC 0x01EC /* Dword offset 0_7B */<br>-<br>-#define SCALE_PITCH 0x01EC /* Dword offset 0_7B */<br>-#define SCALE_X_INC 0x01F0 /* Dword offset 0_7C */<br>-<br>-#define RED_X_INC 0x01F0 /* Dword offset 0_7C */<br>-#define GREEN_X_INC 0x01F4 /* Dword offset 0_7D */<br>-<br>-#define SCALE_Y_INC 0x01F4 /* Dword offset 0_7D */<br>-#define SCALE_VACC 0x01F8 /* Dword offset 0_7E */<br>-#define SCALE_3D_CNTL 0x01FC /* Dword offset 0_7F */<br>-<br>-/* Host Data */<br>-#define HOST_DATA0 0x0200 /* Dword offset 0_80 */<br>-#define HOST_DATA1 0x0204 /* Dword offset 0_81 */<br>-#define HOST_DATA2 0x0208 /* Dword offset 0_82 */<br>-#define HOST_DATA3 0x020C /* Dword offset 0_83 */<br>-#define HOST_DATA4 0x0210 /* Dword offset 0_84 */<br>-#define HOST_DATA5 0x0214 /* Dword offset 0_85 */<br>-#define HOST_DATA6 0x0218 /* Dword offset 0_86 */<br>-#define HOST_DATA7 0x021C /* Dword offset 0_87 */<br>-#define HOST_DATA8 0x0220 /* Dword offset 0_88 */<br>-#define HOST_DATA9 0x0224 /* Dword offset 0_89 */<br>-#define HOST_DATAA 0x0228 /* Dword offset 0_8A */<br>-#define HOST_DATAB 0x022C /* Dword offset 0_8B */<br>-#define HOST_DATAC 0x0230 /* Dword offset 0_8C */<br>-#define HOST_DATAD 0x0234 /* Dword offset 0_8D */<br>-#define HOST_DATAE 0x0238 /* Dword offset 0_8E */<br>-#define HOST_DATAF 0x023C /* Dword offset 0_8F */<br>-#define HOST_CNTL 0x0240 /* Dword offset 0_90 */<br>-<br>-/* GUI Bus Mastering */<br>-#define BM_HOSTDATA 0x0244 /* Dword offset 0_91 */<br>-#define BM_ADDR 0x0248 /* Dword offset 0_92 */<br>-#define BM_DATA 0x0248 /* Dword offset 0_92 */<br>-#define BM_GUI_TABLE_CMD 0x024C /* Dword offset 0_93 */<br>-<br>-/* Pattern */<br>-#define PAT_REG0 0x0280 /* Dword offset 0_A0 */<br>-#define PAT_REG1 0x0284 /* Dword offset 0_A1 */<br>-#define PAT_CNTL 0x0288 /* Dword offset 0_A2 */<br>-<br>-/* Scissors */<br>-#define SC_LEFT 0x02A0 /* Dword offset 0_A8 */<br>-#define SC_RIGHT 0x02A4 /* Dword offset 0_A9 */<br>-#define SC_LEFT_RIGHT 0x02A8 /* Dword offset 0_AA */<br>-#define SC_TOP 0x02AC /* Dword offset 0_AB */<br>-#define SC_BOTTOM 0x02B0 /* Dword offset 0_AC */<br>-#define SC_TOP_BOTTOM 0x02B4 /* Dword offset 0_AD */<br>-<br>-/* Data Path */<br>-#define USR1_DST_OFF_PITCH 0x02B8 /* Dword offset 0_AE */<br>-#define USR2_DST_OFF_PITCH 0x02BC /* Dword offset 0_AF */<br>-#define DP_BKGD_CLR 0x02C0 /* Dword offset 0_B0 */<br>-#define DP_FOG_CLR 0x02C4 /* Dword offset 0_B1 */<br>-#define DP_FRGD_CLR 0x02C4 /* Dword offset 0_B1 */<br>-#define DP_WRITE_MASK 0x02C8 /* Dword offset 0_B2 */<br>-#define DP_CHAIN_MASK 0x02CC /* Dword offset 0_B3 */<br>-#define DP_PIX_WIDTH 0x02D0 /* Dword offset 0_B4 */<br>-#define DP_MIX 0x02D4 /* Dword offset 0_B5 */<br>-#define DP_SRC 0x02D8 /* Dword offset 0_B6 */<br>-#define DP_FRGD_CLR_MIX 0x02DC /* Dword offset 0_B7 */<br>-#define DP_FRGD_BKGD_CLR 0x02E0 /* Dword offset 0_B8 */<br>-<br>-/* Draw Engine Destination Trajectory */<br>-#define DST_X_Y 0x02E8 /* Dword offset 0_BA */<br>-#define DST_WIDTH_HEIGHT 0x02EC /* Dword offset 0_BB */<br>-<br>-/* Data Path */<br>-#define USR_DST_PICTH 0x02F0 /* Dword offset 0_BC */<br>-#define DP_SET_GUI_ENGINE2 0x02F8 /* Dword offset 0_BE */<br>-#define DP_SET_GUI_ENGINE 0x02FC /* Dword offset 0_BF */<br>-<br>-/* Color Compare */<br>-#define CLR_CMP_CLR 0x0300 /* Dword offset 0_C0 */<br>-#define CLR_CMP_MASK 0x0304 /* Dword offset 0_C1 */<br>-#define CLR_CMP_CNTL 0x0308 /* Dword offset 0_C2 */<br>-<br>-/* Command FIFO */<br>-#define FIFO_STAT 0x0310 /* Dword offset 0_C4 */<br>-<br>-#define CONTEXT_MASK 0x0320 /* Dword offset 0_C8 */<br>-#define CONTEXT_LOAD_CNTL 0x032C /* Dword offset 0_CB */<br>-<br>-/* Engine Control */<br>-#define GUI_TRAJ_CNTL 0x0330 /* Dword offset 0_CC */<br>-<br>-/* Engine Status/FIFO */<br>-#define GUI_STAT 0x0338 /* Dword offset 0_CE */<br>-<br>-#define TEX_PALETTE_INDEX 0x0340 /* Dword offset 0_D0 */<br>-#define STW_EXP 0x0344 /* Dword offset 0_D1 */<br>-#define LOG_MAX_INC 0x0348 /* Dword offset 0_D2 */<br>-#define S_X_INC 0x034C /* Dword offset 0_D3 */<br>-#define S_Y_INC__ALIAS__ 0x0350 /* Dword offset 0_D4 */<br>-<br>-#define SCALE_PITCH__ALIAS__ 0x0350 /* Dword offset 0_D4 */<br>-<br>-#define S_START 0x0354 /* Dword offset 0_D5 */<br>-#define W_X_INC 0x0358 /* Dword offset 0_D6 */<br>-#define W_Y_INC 0x035C /* Dword offset 0_D7 */<br>-#define W_START 0x0360 /* Dword offset 0_D8 */<br>-#define T_X_INC 0x0364 /* Dword offset 0_D9 */<br>-#define T_Y_INC 0x0368 /* Dword offset 0_DA */<br>-<br>-#define SECONDARY_SCALE_PITCH 0x0368 /* Dword offset 0_DA */<br>-<br>-#define T_START 0x036C /* Dword offset 0_DB */<br>-#define TEX_SIZE_PITCH 0x0370 /* Dword offset 0_DC */<br>-#define TEX_CNTL 0x0374 /* Dword offset 0_DD */<br>-#define SECONDARY_TEX_OFFSET 0x0378 /* Dword offset 0_DE */<br>-#define TEX_PALETTE 0x037C /* Dword offset 0_DF */<br>-<br>-#define SCALE_PITCH_BOTH 0x0380 /* Dword offset 0_E0 */<br>-#define SECONDARY_SCALE_OFF_ACC 0x0384 /* Dword offset 0_E1 */<br>-#define SCALE_OFF_ACC 0x0388 /* Dword offset 0_E2 */<br>-#define SCALE_DST_Y_X 0x038C /* Dword offset 0_E3 */<br>-<br>-/* Draw Engine Destination Trajectory */<br>-#define COMPOSITE_SHADOW_ID 0x0398 /* Dword offset 0_E6 */<br>-<br>-#define SECONDARY_SCALE_X_INC 0x039C /* Dword offset 0_E7 */<br>-<br>-#define SPECULAR_RED_X_INC 0x039C /* Dword offset 0_E7 */<br>-#define SPECULAR_RED_Y_INC 0x03A0 /* Dword offset 0_E8 */<br>-#define SPECULAR_RED_START 0x03A4 /* Dword offset 0_E9 */<br>-<br>-#define SECONDARY_SCALE_HACC 0x03A4 /* Dword offset 0_E9 */<br>-<br>-#define SPECULAR_GREEN_X_INC 0x03A8 /* Dword offset 0_EA */<br>-#define SPECULAR_GREEN_Y_INC 0x03AC /* Dword offset 0_EB */<br>-#define SPECULAR_GREEN_START 0x03B0 /* Dword offset 0_EC */<br>-#define SPECULAR_BLUE_X_INC 0x03B4 /* Dword offset 0_ED */<br>-#define SPECULAR_BLUE_Y_INC 0x03B8 /* Dword offset 0_EE */<br>-#define SPECULAR_BLUE_START 0x03BC /* Dword offset 0_EF */<br>-<br>-#define SCALE_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */<br>-<br>-#define RED_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */<br>-#define RED_Y_INC 0x03C4 /* Dword offset 0_F1 */<br>-#define RED_START 0x03C8 /* Dword offset 0_F2 */<br>-<br>-#define SCALE_HACC 0x03C8 /* Dword offset 0_F2 */<br>-#define SCALE_Y_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */<br>-<br>-#define GREEN_X_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */<br>-#define GREEN_Y_INC 0x03D0 /* Dword offset 0_F4 */<br>-<br>-#define SECONDARY_SCALE_Y_INC 0x03D0 /* Dword offset 0_F4 */<br>-#define SECONDARY_SCALE_VACC 0x03D4 /* Dword offset 0_F5 */<br>-<br>-#define GREEN_START 0x03D4 /* Dword offset 0_F5 */<br>-#define BLUE_X_INC 0x03D8 /* Dword offset 0_F6 */<br>-#define BLUE_Y_INC 0x03DC /* Dword offset 0_F7 */<br>-#define BLUE_START 0x03E0 /* Dword offset 0_F8 */<br>-#define Z_X_INC 0x03E4 /* Dword offset 0_F9 */<br>-#define Z_Y_INC 0x03E8 /* Dword offset 0_FA */<br>-#define Z_START 0x03EC /* Dword offset 0_FB */<br>-#define ALPHA_X_INC 0x03F0 /* Dword offset 0_FC */<br>-#define FOG_X_INC 0x03F0 /* Dword offset 0_FC */<br>-#define ALPHA_Y_INC 0x03F4 /* Dword offset 0_FD */<br>-#define FOG_Y_INC 0x03F4 /* Dword offset 0_FD */<br>-#define ALPHA_START 0x03F8 /* Dword offset 0_FE */<br>-#define FOG_START 0x03F8 /* Dword offset 0_FE */<br>-<br>-#define OVERLAY_Y_X_START 0x0400 /* Dword offset 1_00 */<br>-#define OVERLAY_Y_X_END 0x0404 /* Dword offset 1_01 */<br>-#define OVERLAY_VIDEO_KEY_CLR 0x0408 /* Dword offset 1_02 */<br>-#define OVERLAY_VIDEO_KEY_MSK 0x040C /* Dword offset 1_03 */<br>-#define OVERLAY_GRAPHICS_KEY_CLR 0x0410 /* Dword offset 1_04 */<br>-#define OVERLAY_GRAPHICS_KEY_MSK 0x0414 /* Dword offset 1_05 */<br>-#define OVERLAY_KEY_CNTL 0x0418 /* Dword offset 1_06 */<br>-<br>-#define OVERLAY_SCALE_INC 0x0420 /* Dword offset 1_08 */<br>-#define OVERLAY_SCALE_CNTL 0x0424 /* Dword offset 1_09 */<br>-#define SCALER_HEIGHT_WIDTH 0x0428 /* Dword offset 1_0A */<br>-#define SCALER_TEST 0x042C /* Dword offset 1_0B */<br>-#define SCALER_BUF0_OFFSET 0x0434 /* Dword offset 1_0D */<br>-#define SCALER_BUF1_OFFSET 0x0438 /* Dword offset 1_0E */<br>-#define SCALE_BUF_PITCH 0x043C /* Dword offset 1_0F */<br>-<br>-#define CAPTURE_START_END 0x0440 /* Dword offset 1_10 */<br>-#define CAPTURE_X_WIDTH 0x0444 /* Dword offset 1_11 */<br>-#define VIDEO_FORMAT 0x0448 /* Dword offset 1_12 */<br>-#define VBI_START_END 0x044C /* Dword offset 1_13 */<br>-#define CAPTURE_CONFIG 0x0450 /* Dword offset 1_14 */<br>-#define TRIG_CNTL 0x0454 /* Dword offset 1_15 */<br>-<br>-#define OVERLAY_EXCLUSIVE_HORZ 0x0458 /* Dword offset 1_16 */<br>-#define OVERLAY_EXCLUSIVE_VERT 0x045C /* Dword offset 1_17 */<br>-<br>-#define VAL_WIDTH 0x0460 /* Dword offset 1_18 */<br>-#define CAPTURE_DEBUG 0x0464 /* Dword offset 1_19 */<br>-#define VIDEO_SYNC_TEST 0x0468 /* Dword offset 1_1A */<br>-<br>-/* GenLocking */<br>-#define SNAPSHOT_VH_COUNTS 0x0470 /* Dword offset 1_1C */<br>-#define SNAPSHOT_F_COUNT 0x0474 /* Dword offset 1_1D */<br>-#define N_VIF_COUNT 0x0478 /* Dword offset 1_1E */<br>-#define SNAPSHOT_VIF_COUNT 0x047C /* Dword offset 1_1F */<br>-<br>-#define CAPTURE_BUF0_OFFSET 0x0480 /* Dword offset 1_20 */<br>-#define CAPTURE_BUF1_OFFSET 0x0484 /* Dword offset 1_21 */<br>-#define CAPTURE_BUF_PITCH 0x0488 /* Dword offset 1_22 */<br>-<br>-/* GenLocking */<br>-#define SNAPSHOT2_VH_COUNTS 0x04B0 /* Dword offset 1_2C */<br>-#define SNAPSHOT2_F_COUNT 0x04B4 /* Dword offset 1_2D */<br>-#define N_VIF2_COUNT 0x04B8 /* Dword offset 1_2E */<br>-#define SNAPSHOT2_VIF_COUNT 0x04BC /* Dword offset 1_2F */<br>-<br>-#define MPP_CONFIG 0x04C0 /* Dword offset 1_30 */<br>-#define MPP_STROBE_SEQ 0x04C4 /* Dword offset 1_31 */<br>-#define MPP_ADDR 0x04C8 /* Dword offset 1_32 */<br>-#define MPP_DATA 0x04CC /* Dword offset 1_33 */<br>-#define TVO_CNTL 0x0500 /* Dword offset 1_40 */<br>-<br>-/* Test and Debug */<br>-#define CRT_HORZ_VERT_LOAD 0x0544 /* Dword offset 1_51 */<br>-<br>-/* AGP */<br>-#define AGP_BASE 0x0548 /* Dword offset 1_52 */<br>-#define AGP_CNTL 0x054C /* Dword offset 1_53 */<br>-<br>-#define SCALER_COLOUR_CNTL 0x0550 /* Dword offset 1_54 */<br>-#define SCALER_H_COEFF0 0x0554 /* Dword offset 1_55 */<br>-#define SCALER_H_COEFF1 0x0558 /* Dword offset 1_56 */<br>-#define SCALER_H_COEFF2 0x055C /* Dword offset 1_57 */<br>-#define SCALER_H_COEFF3 0x0560 /* Dword offset 1_58 */<br>-#define SCALER_H_COEFF4 0x0564 /* Dword offset 1_59 */<br>-<br>-/* Command FIFO */<br>-#define GUI_CMDFIFO_DEBUG 0x0570 /* Dword offset 1_5C */<br>-#define GUI_CMDFIFO_DATA 0x0574 /* Dword offset 1_5D */<br>-#define GUI_CNTL 0x0578 /* Dword offset 1_5E */<br>-<br>-/* Bus Mastering */<br>-#define BM_FRAME_BUF_OFFSET 0x0580 /* Dword offset 1_60 */<br>-#define BM_SYSTEM_MEM_ADDR 0x0584 /* Dword offset 1_61 */<br>-#define BM_COMMAND 0x0588 /* Dword offset 1_62 */<br>-#define BM_STATUS 0x058C /* Dword offset 1_63 */<br>-#define BM_GUI_TABLE 0x05B8 /* Dword offset 1_6E */<br>-#define BM_SYSTEM_TABLE 0x05BC /* Dword offset 1_6F */<br>-<br>-#define SCALER_BUF0_OFFSET_U 0x05D4 /* Dword offset 1_75 */<br>-#define SCALER_BUF0_OFFSET_V 0x05D8 /* Dword offset 1_76 */<br>-#define SCALER_BUF1_OFFSET_U 0x05DC /* Dword offset 1_77 */<br>-#define SCALER_BUF1_OFFSET_V 0x05E0 /* Dword offset 1_78 */<br>-<br>-/* Setup Engine */<br>-#define VERTEX_1_S 0x0640 /* Dword offset 1_90 */<br>-#define VERTEX_1_T 0x0644 /* Dword offset 1_91 */<br>-#define VERTEX_1_W 0x0648 /* Dword offset 1_92 */<br>-#define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_93 */<br>-#define VERTEX_1_Z 0x0650 /* Dword offset 1_94 */<br>-#define VERTEX_1_ARGB 0x0654 /* Dword offset 1_95 */<br>-#define VERTEX_1_X_Y 0x0658 /* Dword offset 1_96 */<br>-#define ONE_OVER_AREA 0x065C /* Dword offset 1_97 */<br>-#define VERTEX_2_S 0x0660 /* Dword offset 1_98 */<br>-#define VERTEX_2_T 0x0664 /* Dword offset 1_99 */<br>-#define VERTEX_2_W 0x0668 /* Dword offset 1_9A */<br>-#define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_9B */<br>-#define VERTEX_2_Z 0x0670 /* Dword offset 1_9C */<br>-#define VERTEX_2_ARGB 0x0674 /* Dword offset 1_9D */<br>-#define VERTEX_2_X_Y 0x0678 /* Dword offset 1_9E */<br>-#define ONE_OVER_AREA 0x065C /* Dword offset 1_9F */<br>-#define VERTEX_3_S 0x0680 /* Dword offset 1_A0 */<br>-#define VERTEX_3_T 0x0684 /* Dword offset 1_A1 */<br>-#define VERTEX_3_W 0x0688 /* Dword offset 1_A2 */<br>-#define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_A3 */<br>-#define VERTEX_3_Z 0x0690 /* Dword offset 1_A4 */<br>-#define VERTEX_3_ARGB 0x0694 /* Dword offset 1_A5 */<br>-#define VERTEX_3_X_Y 0x0698 /* Dword offset 1_A6 */<br>-#define ONE_OVER_AREA 0x065C /* Dword offset 1_A7 */<br>-#define VERTEX_1_S 0x0640 /* Dword offset 1_AB */<br>-#define VERTEX_1_T 0x0644 /* Dword offset 1_AC */<br>-#define VERTEX_1_W 0x0648 /* Dword offset 1_AD */<br>-#define VERTEX_2_S 0x0660 /* Dword offset 1_AE */<br>-#define VERTEX_2_T 0x0664 /* Dword offset 1_AF */<br>-#define VERTEX_2_W 0x0668 /* Dword offset 1_B0 */<br>-#define VERTEX_3_SECONDARY_S 0x06C0 /* Dword offset 1_B0 */<br>-#define VERTEX_3_S 0x0680 /* Dword offset 1_B1 */<br>-#define VERTEX_3_SECONDARY_T 0x06C4 /* Dword offset 1_B1 */<br>-#define VERTEX_3_T 0x0684 /* Dword offset 1_B2 */<br>-#define VERTEX_3_SECONDARY_W 0x06C8 /* Dword offset 1_B2 */<br>-#define VERTEX_3_W 0x0688 /* Dword offset 1_B3 */<br>-#define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_B4 */<br>-#define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_B5 */<br>-#define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_B6 */<br>-#define VERTEX_1_Z 0x0650 /* Dword offset 1_B7 */<br>-#define VERTEX_2_Z 0x0670 /* Dword offset 1_B8 */<br>-#define VERTEX_3_Z 0x0690 /* Dword offset 1_B9 */<br>-#define VERTEX_1_ARGB 0x0654 /* Dword offset 1_BA */<br>-#define VERTEX_2_ARGB 0x0674 /* Dword offset 1_BB */<br>-#define VERTEX_3_ARGB 0x0694 /* Dword offset 1_BC */<br>-#define VERTEX_1_X_Y 0x0658 /* Dword offset 1_BD */<br>-#define VERTEX_2_X_Y 0x0678 /* Dword offset 1_BE */<br>-#define VERTEX_3_X_Y 0x0698 /* Dword offset 1_BF */<br>-#define ONE_OVER_AREA_UC 0x0700 /* Dword offset 1_C0 */<br>-#define SETUP_CNTL 0x0704 /* Dword offset 1_C1 */<br>-#define VERTEX_1_SECONDARY_S 0x0728 /* Dword offset 1_CA */<br>-#define VERTEX_1_SECONDARY_T 0x072C /* Dword offset 1_CB */<br>-#define VERTEX_1_SECONDARY_W 0x0730 /* Dword offset 1_CC */<br>-#define VERTEX_2_SECONDARY_S 0x0734 /* Dword offset 1_CD */<br>-#define VERTEX_2_SECONDARY_T 0x0738 /* Dword offset 1_CE */<br>-#define VERTEX_2_SECONDARY_W 0x073C /* Dword offset 1_CF */<br>-<br>-<br>-#define GTC_3D_RESET_DELAY 3 /* 3D engine reset delay in ms */<br>-<br>-/* CRTC control values (mostly CRTC_GEN_CNTL) */<br>-<br>-#define CRTC_H_SYNC_NEG 0x00200000<br>-#define CRTC_V_SYNC_NEG 0x00200000<br>-<br>-#define CRTC_DBL_SCAN_EN 0x00000001<br>-#define CRTC_INTERLACE_EN 0x00000002<br>-#define CRTC_HSYNC_DIS 0x00000004<br>-#define CRTC_VSYNC_DIS 0x00000008<br>-#define CRTC_CSYNC_EN 0x00000010<br>-#define CRTC_PIX_BY_2_EN 0x00000020 /* unused on RAGE */<br>-#define CRTC_DISPLAY_DIS 0x00000040<br>-#define CRTC_VGA_XOVERSCAN 0x00000040<br>-<br>-#define CRTC_PIX_WIDTH_MASK 0x00000700<br>-#define CRTC_PIX_WIDTH_4BPP 0x00000100<br>-#define CRTC_PIX_WIDTH_8BPP 0x00000200<br>-#define CRTC_PIX_WIDTH_15BPP 0x00000300<br>-#define CRTC_PIX_WIDTH_16BPP 0x00000400<br>-#define CRTC_PIX_WIDTH_24BPP 0x00000500<br>-#define CRTC_PIX_WIDTH_32BPP 0x00000600<br>-<br>-#define CRTC_BYTE_PIX_ORDER 0x00000800<br>-#define CRTC_PIX_ORDER_MSN_LSN 0x00000000<br>-#define CRTC_PIX_ORDER_LSN_MSN 0x00000800<br>-<br>-#define CRTC_FIFO_LWM 0x000f0000<br>-<br>-#define VGA_128KAP_PAGING 0x00100000<br>-#define VFC_SYNC_TRISTATE 0x00200000<br>-#define CRTC_LOCK_REGS 0x00400000<br>-#define CRTC_SYNC_TRISTATE 0x00800000<br>-<br>-#define CRTC_EXT_DISP_EN 0x01000000<br>-#define CRTC_ENABLE 0x02000000<br>-#define CRTC_DISP_REQ_ENB 0x04000000<br>-#define VGA_ATI_LINEAR 0x08000000<br>-#define CRTC_VSYNC_FALL_EDGE 0x10000000<br>-#define VGA_TEXT_132 0x20000000<br>-#define VGA_XCRT_CNT_EN 0x40000000<br>-#define VGA_CUR_B_TEST 0x80000000<br>-<br>-#define CRTC_CRNT_VLINE 0x07f00000<br>-#define CRTC_VBLANK 0x00000001<br>-<br>-<br>-/* DAC control values */<br>-<br>-#define DAC_EXT_SEL_RS2 0x01<br>-#define DAC_EXT_SEL_RS3 0x02<br>-#define DAC_8BIT_EN 0x00000100<br>-#define DAC_PIX_DLY_MASK 0x00000600<br>-#define DAC_PIX_DLY_0NS 0x00000000<br>-#define DAC_PIX_DLY_2NS 0x00000200<br>-#define DAC_PIX_DLY_4NS 0x00000400<br>-#define DAC_BLANK_ADJ_MASK 0x00001800<br>-#define DAC_BLANK_ADJ_0 0x00000000<br>-#define DAC_BLANK_ADJ_1 0x00000800<br>-#define DAC_BLANK_ADJ_2 0x00001000<br>-<br>-<br>-/* Mix control values */<br>-<br>-#define MIX_NOT_DST 0x0000<br>-#define MIX_0 0x0001<br>-#define MIX_1 0x0002<br>-#define MIX_DST 0x0003<br>-#define MIX_NOT_SRC 0x0004<br>-#define MIX_XOR 0x0005<br>-#define MIX_XNOR 0x0006<br>-#define MIX_SRC 0x0007<br>-#define MIX_NAND 0x0008<br>-#define MIX_NOT_SRC_OR_DST 0x0009<br>-#define MIX_SRC_OR_NOT_DST 0x000a<br>-#define MIX_OR 0x000b<br>-#define MIX_AND 0x000c<br>-#define MIX_SRC_AND_NOT_DST 0x000d<br>-#define MIX_NOT_SRC_AND_DST 0x000e<br>-#define MIX_NOR 0x000f<br>-<br>-/* Maximum engine dimensions */<br>-#define ENGINE_MIN_X 0<br>-#define ENGINE_MIN_Y 0<br>-#define ENGINE_MAX_X 4095<br>-#define ENGINE_MAX_Y 16383<br>-<br>-/* Mach64 engine bit constants - these are typically ORed together */<br>-<br>-/* BUS_CNTL register constants */<br>-#define BUS_FIFO_ERR_ACK 0x00200000<br>-#define BUS_HOST_ERR_ACK 0x00800000<br>-<br>-/* GEN_TEST_CNTL register constants */<br>-#define GEN_OVR_OUTPUT_EN 0x20<br>-#define HWCURSOR_ENABLE 0x80<br>-#define GUI_ENGINE_ENABLE 0x100<br>-#define BLOCK_WRITE_ENABLE 0x200<br>-<br>-/* DSP_CONFIG register constants */<br>-#define DSP_XCLKS_PER_QW 0x00003fff<br>-#define DSP_LOOP_LATENCY 0x000f0000<br>-#define DSP_PRECISION 0x00700000<br>-<br>-/* DSP_ON_OFF register constants */<br>-#define DSP_OFF 0x000007ff<br>-#define DSP_ON 0x07ff0000<br>-<br>-/* CLOCK_CNTL register constants */<br>-#define CLOCK_SEL 0x0f<br>-#define CLOCK_DIV 0x30<br>-#define CLOCK_DIV1 0x00<br>-#define CLOCK_DIV2 0x10<br>-#define CLOCK_DIV4 0x20<br>-#define CLOCK_STROBE 0x40<br>-#define PLL_WR_EN 0x02<br>-<br>-/* PLL register indices */<br>-#define MPLL_CNTL 0x00<br>-#define VPLL_CNTL 0x01<br>-#define PLL_REF_DIV 0x02<br>-#define PLL_GEN_CNTL 0x03<br>-#define MCLK_FB_DIV 0x04<br>-#define PLL_VCLK_CNTL 0x05<br>-#define VCLK_POST_DIV 0x06<br>-#define VCLK0_FB_DIV 0x07<br>-#define VCLK1_FB_DIV 0x08<br>-#define VCLK2_FB_DIV 0x09<br>-#define VCLK3_FB_DIV 0x0A<br>-#define PLL_EXT_CNTL 0x0B<br>-#define DLL_CNTL 0x0C<br>-#define DLL1_CNTL 0x0C<br>-#define VFC_CNTL 0x0D<br>-#define PLL_TEST_CNTL 0x0E<br>-#define PLL_TEST_COUNT 0x0F<br>-#define LVDS_CNTL0 0x10<br>-#define LVDS_CNTL1 0x11<br>-#define AGP1_CNTL 0x12<br>-#define AGP2_CNTL 0x13<br>-#define DLL2_CNTL 0x14<br>-#define SCLK_FB_DIV 0x15<br>-#define SPLL_CNTL1 0x16<br>-#define SPLL_CNTL2 0x17<br>-#define APLL_STRAPS 0x18<br>-#define EXT_VPLL_CNTL 0x19<br>-#define EXT_VPLL_REF_DIV 0x1A<br>-#define EXT_VPLL_FB_DIV 0x1B<br>-#define EXT_VPLL_MSB 0x1C<br>-#define HTOTAL_CNTL 0x1D<br>-#define BYTE_CLK_CNTL 0x1E<br>-#define TV_PLL_CNTL1 0x1F<br>-#define TV_PLL_CNTL2 0x20<br>-#define TV_PLL_CNTL 0x21<br>-#define EXT_TV_PLL 0x22<br>-#define V2PLL_CNTL 0x23<br>-#define PLL_V2CLK_CNTL 0x24<br>-#define EXT_V2PLL_REF_DIV 0x25<br>-#define EXT_V2PLL_FB_DIV 0x26<br>-#define EXT_V2PLL_MSB 0x27<br>-#define HTOTAL2_CNTL 0x28<br>-#define PLL_YCLK_CNTL 0x29<br>-#define PM_DYN_CLK_CNTL 0x2A<br>-<br>-/* Fields in PLL registers */<br>-#define PLL_PC_GAIN 0x07<br>-#define PLL_VC_GAIN 0x18<br>-#define PLL_DUTY_CYC 0xE0<br>-#define PLL_OVERRIDE 0x01<br>-#define PLL_MCLK_RST 0x02<br>-#define OSC_EN 0x04<br>-#define EXT_CLK_EN 0x08<br>-#define MCLK_SRC_SEL 0x70<br>-#define EXT_CLK_CNTL 0x80<br>-#define VCLK_SRC_SEL 0x03<br>-#define PLL_VCLK_RST 0x04<br>-#define VCLK_INVERT 0x08<br>-#define VCLK0_POST 0x03<br>-#define VCLK1_POST 0x0C<br>-#define VCLK2_POST 0x30<br>-#define VCLK3_POST 0xC0<br>-<br>-/* CFG_CNTL register constants */<br>-#define APERTURE_4M_ENABLE 1<br>-#define APERTURE_8M_ENABLE 2<br>-#define VGA_APERTURE_ENABLE 4<br>-<br>-/* CFG_STAT0 register constants (GX, CX) */<br>-#define CFG_BUS_TYPE 0x00000007<br>-#define CFG_MEM_TYPE 0x00000038<br>-#define CFG_INIT_DAC_TYPE 0x00000e00<br>-<br>-/* CFG_STAT0 register constants (CT, ET, VT) */<br>-#define CFG_MEM_TYPE_xT 0x00000007<br>-<br>-#define ISA 0<br>-#define EISA 1<br>-#define LOCAL_BUS 6<br>-#define PCI 7<br>-<br>-/* Memory types for GX, CX */<br>-#define DRAMx4 0<br>-#define VRAMx16 1<br>-#define VRAMx16ssr 2<br>-#define DRAMx16 3<br>-#define GraphicsDRAMx16 4<br>-#define EnhancedVRAMx16 5<br>-#define EnhancedVRAMx16ssr 6<br>-<br>-/* Memory types for CT, ET, VT, GT */<br>-#define DRAM 1<br>-#define EDO 2<br>-#define PSEUDO_EDO 3<br>-#define SDRAM 4<br>-#define SGRAM 5<br>-#define WRAM 6<br>-<br>-#define DAC_INTERNAL 0x00<br>-#define DAC_IBMRGB514 0x01<br>-#define DAC_ATI68875 0x02<br>-#define DAC_TVP3026_A 0x72<br>-#define DAC_BT476 0x03<br>-#define DAC_BT481 0x04<br>-#define DAC_ATT20C491 0x14<br>-#define DAC_SC15026 0x24<br>-#define DAC_MU9C1880 0x34<br>-#define DAC_IMSG174 0x44<br>-#define DAC_ATI68860_B 0x05<br>-#define DAC_ATI68860_C 0x15<br>-#define DAC_TVP3026_B 0x75<br>-#define DAC_STG1700 0x06<br>-#define DAC_ATT498 0x16<br>-#define DAC_STG1702 0x07<br>-#define DAC_SC15021 0x17<br>-#define DAC_ATT21C498 0x27<br>-#define DAC_STG1703 0x37<br>-#define DAC_CH8398 0x47<br>-#define DAC_ATT20C408 0x57<br>-<br>-#define CLK_ATI18818_0 0<br>-#define CLK_ATI18818_1 1<br>-#define CLK_STG1703 2<br>-#define CLK_CH8398 3<br>-#define CLK_INTERNAL 4<br>-#define CLK_ATT20C408 5<br>-#define CLK_IBMRGB514 6<br>-<br>-/* MEM_CNTL register constants */<br>-#define MEM_SIZE_ALIAS 0x00000007<br>-#define MEM_SIZE_512K 0x00000000<br>-#define MEM_SIZE_1M 0x00000001<br>-#define MEM_SIZE_2M 0x00000002<br>-#define MEM_SIZE_4M 0x00000003<br>-#define MEM_SIZE_6M 0x00000004<br>-#define MEM_SIZE_8M 0x00000005<br>-#define MEM_SIZE_ALIAS_GTB 0x0000000F<br>-#define MEM_SIZE_2M_GTB 0x00000003<br>-#define MEM_SIZE_4M_GTB 0x00000007<br>-#define MEM_SIZE_6M_GTB 0x00000009<br>-#define MEM_SIZE_8M_GTB 0x0000000B<br>-#define MEM_BNDRY 0x00030000<br>-#define MEM_BNDRY_0K 0x00000000<br>-#define MEM_BNDRY_256K 0x00010000<br>-#define MEM_BNDRY_512K 0x00020000<br>-#define MEM_BNDRY_1M 0x00030000<br>-#define MEM_BNDRY_EN 0x00040000<br>-<br>-/* ATI PCI constants */<br>-#define PCI_ATI_VENDOR_ID 0x1002<br>-<br>-<br>-/* CFG_CHIP_ID register constants */<br>-#define CFG_CHIP_TYPE 0x0000FFFF<br>-#define CFG_CHIP_CLASS 0x00FF0000<br>-#define CFG_CHIP_REV 0xFF000000<br>-#define CFG_CHIP_MAJOR 0x07000000<br>-#define CFG_CHIP_FND_ID 0x38000000<br>-#define CFG_CHIP_MINOR 0xC0000000<br>-<br>-<br>-/* Chip IDs read from CFG_CHIP_ID */<br>-<br>-/* mach64GX family */<br>-#define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */<br>-#define CX_CHIP_ID 0x57 /* mach64CX (ATI888CX00) */<br>-<br>-#define GX_PCI_ID 0x4758 /* mach64GX (ATI888GX00) */<br>-#define CX_PCI_ID 0x4358 /* mach64CX (ATI888CX00) */<br>-<br>-/* mach64CT family */<br>-#define CT_CHIP_ID 0x4354 /* mach64CT (ATI264CT) */<br>-#define ET_CHIP_ID 0x4554 /* mach64ET (ATI264ET) */<br>-<br>-/* mach64CT family / mach64VT class */<br>-#define VT_CHIP_ID 0x5654 /* mach64VT (ATI264VT) */<br>-#define VU_CHIP_ID 0x5655 /* mach64VTB (ATI264VTB) */<br>-#define VV_CHIP_ID 0x5656 /* mach64VT4 (ATI264VT4) */<br>-<br>-/* mach64CT family / mach64GT (3D RAGE) class */<br>-#define LB_CHIP_ID 0x4c42 /* RAGE LT PRO, AGP */<br>-#define LD_CHIP_ID 0x4c44 /* RAGE LT PRO */<br>-#define LG_CHIP_ID 0x4c47 /* RAGE LT */<br>-#define LI_CHIP_ID 0x4c49 /* RAGE LT PRO */<br>-#define LP_CHIP_ID 0x4c50 /* RAGE LT PRO */<br>-#define LT_CHIP_ID 0x4c54 /* RAGE LT */<br>-<br>-#define GR_CHIP_ID 0x4752 /* RAGE XL, BGA, PCI33 */<br>-#define GS_CHIP_ID 0x4753 /* RAGE XL, PQFP, PCI33 */<br>-#define GM_CHIP_ID 0x474d /* RAGE XL, BGA, AGP 1x,2x */<br>-#define GN_CHIP_ID 0x474e /* RAGE XL, PQFP,AGP 1x,2x */<br>-#define GO_CHIP_ID 0x474f /* RAGE XL, BGA, PCI66 */<br>-#define GL_CHIP_ID 0x474c /* RAGE XL, PQFP, PCI66 */<br>-<br>-#define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \<br>- (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \<br>- (id)==GO_CHIP_ID || (id)==GL_CHIP_ID)<br>-<br>-#define GT_CHIP_ID 0x4754 /* RAGE (GT) */<br>-#define GU_CHIP_ID 0x4755 /* RAGE II/II+ (GTB) */<br>-#define GV_CHIP_ID 0x4756 /* RAGE IIC, PCI */<br>-#define GW_CHIP_ID 0x4757 /* RAGE IIC, AGP */<br>-#define GZ_CHIP_ID 0x475a /* RAGE IIC, AGP */<br>-#define GB_CHIP_ID 0x4742 /* RAGE PRO, BGA, AGP 1x and 2x */<br>-#define GD_CHIP_ID 0x4744 /* RAGE PRO, BGA, AGP 1x only */<br>-#define GI_CHIP_ID 0x4749 /* RAGE PRO, BGA, PCI33 only */<br>-#define GP_CHIP_ID 0x4750 /* RAGE PRO, PQFP, PCI33, full 3D */<br>-#define GQ_CHIP_ID 0x4751 /* RAGE PRO, PQFP, PCI33, limited 3D */<br>-#define LM_CHIP_ID 0x4c4d /* RAGE Mobility PCI */<br>-#define LN_CHIP_ID 0x4c4e /* RAGE Mobility AGP */<br>-<br>-<br>-/* Mach64 major ASIC revisions */<br>-#define MACH64_ASIC_NEC_VT_A3 0x08<br>-#define MACH64_ASIC_NEC_VT_A4 0x48<br>-#define MACH64_ASIC_SGS_VT_A4 0x40<br>-#define MACH64_ASIC_SGS_VT_B1S1 0x01<br>-#define MACH64_ASIC_SGS_GT_B1S1 0x01<br>-#define MACH64_ASIC_SGS_GT_B1S2 0x41<br>-#define MACH64_ASIC_UMC_GT_B2U1 0x1a<br>-#define MACH64_ASIC_UMC_GT_B2U2 0x5a<br>-#define MACH64_ASIC_UMC_VT_B2U3 0x9a<br>-#define MACH64_ASIC_UMC_GT_B2U3 0x9a<br>-#define MACH64_ASIC_UMC_R3B_D_P_A1 0x1b<br>-#define MACH64_ASIC_UMC_R3B_D_P_A2 0x5b<br>-#define MACH64_ASIC_UMC_R3B_D_P_A3 0x1c<br>-#define MACH64_ASIC_UMC_R3B_D_P_A4 0x5c<br>-<br>-/* Mach64 foundries */<br>-#define MACH64_FND_SGS 0<br>-#define MACH64_FND_NEC 1<br>-#define MACH64_FND_UMC 3<br>-<br>-/* Mach64 chip types */<br>-#define MACH64_UNKNOWN 0<br>-#define MACH64_GX 1<br>-#define MACH64_CX 2<br>-#define MACH64_CT 3<br>-#define MACH64_ET 4<br>-#define MACH64_VT 5<br>-#define MACH64_GT 6<br>-<br>-/* DST_CNTL register constants */<br>-#define DST_X_RIGHT_TO_LEFT 0<br>-#define DST_X_LEFT_TO_RIGHT 1<br>-#define DST_Y_BOTTOM_TO_TOP 0<br>-#define DST_Y_TOP_TO_BOTTOM 2<br>-#define DST_X_MAJOR 0<br>-#define DST_Y_MAJOR 4<br>-#define DST_X_TILE 8<br>-#define DST_Y_TILE 0x10<br>-#define DST_LAST_PEL 0x20<br>-#define DST_POLYGON_ENABLE 0x40<br>-#define DST_24_ROTATION_ENABLE 0x80<br>-<br>-/* SRC_CNTL register constants */<br>-#define SRC_PATTERN_ENABLE 1<br>-#define SRC_ROTATION_ENABLE 2<br>-#define SRC_LINEAR_ENABLE 4<br>-#define SRC_BYTE_ALIGN 8<br>-#define SRC_LINE_X_RIGHT_TO_LEFT 0<br>-#define SRC_LINE_X_LEFT_TO_RIGHT 0x10<br>-<br>-/* HOST_CNTL register constants */<br>-#define HOST_BYTE_ALIGN 1<br>-<br>-/* GUI_TRAJ_CNTL register constants */<br>-#define PAT_MONO_8x8_ENABLE 0x01000000<br>-#define PAT_CLR_4x2_ENABLE 0x02000000<br>-#define PAT_CLR_8x1_ENABLE 0x04000000<br>-<br>-/* DP_CHAIN_MASK register constants */<br>-#define DP_CHAIN_4BPP 0x8888<br>-#define DP_CHAIN_7BPP 0xD2D2<br>-#define DP_CHAIN_8BPP 0x8080<br>-#define DP_CHAIN_8BPP_RGB 0x9292<br>-#define DP_CHAIN_15BPP 0x4210<br>-#define DP_CHAIN_16BPP 0x8410<br>-#define DP_CHAIN_24BPP 0x8080<br>-#define DP_CHAIN_32BPP 0x8080<br>-<br>-/* DP_PIX_WIDTH register constants */<br>-#define DST_1BPP 0<br>-#define DST_4BPP 1<br>-#define DST_8BPP 2<br>-#define DST_15BPP 3<br>-#define DST_16BPP 4<br>-#define DST_32BPP 6<br>-#define SRC_1BPP 0<br>-#define SRC_4BPP 0x100<br>-#define SRC_8BPP 0x200<br>-#define SRC_15BPP 0x300<br>-#define SRC_16BPP 0x400<br>-#define SRC_32BPP 0x600<br>-#define HOST_1BPP 0<br>-#define HOST_4BPP 0x10000<br>-#define HOST_8BPP 0x20000<br>-#define HOST_15BPP 0x30000<br>-#define HOST_16BPP 0x40000<br>-#define HOST_32BPP 0x60000<br>-#define BYTE_ORDER_MSB_TO_LSB 0<br>-#define BYTE_ORDER_LSB_TO_MSB 0x1000000<br>-<br>-/* DP_MIX register constants */<br>-#define BKGD_MIX_NOT_D 0<br>-#define BKGD_MIX_ZERO 1<br>-#define BKGD_MIX_ONE 2<br>-#define BKGD_MIX_D 3<br>-#define BKGD_MIX_NOT_S 4<br>-#define BKGD_MIX_D_XOR_S 5<br>-#define BKGD_MIX_NOT_D_XOR_S 6<br>-#define BKGD_MIX_S 7<br>-#define BKGD_MIX_NOT_D_OR_NOT_S 8<br>-#define BKGD_MIX_D_OR_NOT_S 9<br>-#define BKGD_MIX_NOT_D_OR_S 10<br>-#define BKGD_MIX_D_OR_S 11<br>-#define BKGD_MIX_D_AND_S 12<br>-#define BKGD_MIX_NOT_D_AND_S 13<br>-#define BKGD_MIX_D_AND_NOT_S 14<br>-#define BKGD_MIX_NOT_D_AND_NOT_S 15<br>-#define BKGD_MIX_D_PLUS_S_DIV2 0x17<br>-#define FRGD_MIX_NOT_D 0<br>-#define FRGD_MIX_ZERO 0x10000<br>-#define FRGD_MIX_ONE 0x20000<br>-#define FRGD_MIX_D 0x30000<br>-#define FRGD_MIX_NOT_S 0x40000<br>-#define FRGD_MIX_D_XOR_S 0x50000<br>-#define FRGD_MIX_NOT_D_XOR_S 0x60000<br>-#define FRGD_MIX_S 0x70000<br>-#define FRGD_MIX_NOT_D_OR_NOT_S 0x80000<br>-#define FRGD_MIX_D_OR_NOT_S 0x90000<br>-#define FRGD_MIX_NOT_D_OR_S 0xa0000<br>-#define FRGD_MIX_D_OR_S 0xb0000<br>-#define FRGD_MIX_D_AND_S 0xc0000<br>-#define FRGD_MIX_NOT_D_AND_S 0xd0000<br>-#define FRGD_MIX_D_AND_NOT_S 0xe0000<br>-#define FRGD_MIX_NOT_D_AND_NOT_S 0xf0000<br>-#define FRGD_MIX_D_PLUS_S_DIV2 0x170000<br>-<br>-/* DP_SRC register constants */<br>-#define BKGD_SRC_BKGD_CLR 0<br>-#define BKGD_SRC_FRGD_CLR 1<br>-#define BKGD_SRC_HOST 2<br>-#define BKGD_SRC_BLIT 3<br>-#define BKGD_SRC_PATTERN 4<br>-#define FRGD_SRC_BKGD_CLR 0<br>-#define FRGD_SRC_FRGD_CLR 0x100<br>-#define FRGD_SRC_HOST 0x200<br>-#define FRGD_SRC_BLIT 0x300<br>-#define FRGD_SRC_PATTERN 0x400<br>-#define MONO_SRC_ONE 0<br>-#define MONO_SRC_PATTERN 0x10000<br>-#define MONO_SRC_HOST 0x20000<br>-#define MONO_SRC_BLIT 0x30000<br>-<br>-/* CLR_CMP_CNTL register constants */<br>-#define COMPARE_FALSE 0<br>-#define COMPARE_TRUE 1<br>-#define COMPARE_NOT_EQUAL 4<br>-#define COMPARE_EQUAL 5<br>-#define COMPARE_DESTINATION 0<br>-#define COMPARE_SOURCE 0x1000000<br>-<br>-/* FIFO_STAT register constants */<br>-#define FIFO_ERR 0x80000000<br>-<br>-/* CONTEXT_LOAD_CNTL constants */<br>-#define CONTEXT_NO_LOAD 0<br>-#define CONTEXT_LOAD 0x10000<br>-#define CONTEXT_LOAD_AND_DO_FILL 0x20000<br>-#define CONTEXT_LOAD_AND_DO_LINE 0x30000<br>-#define CONTEXT_EXECUTE 0<br>-#define CONTEXT_CMD_DISABLE 0x80000000<br>-<br>-/* GUI_STAT register constants */<br>-#define ENGINE_IDLE 0<br>-#define ENGINE_BUSY 1<br>-#define SCISSOR_LEFT_FLAG 0x10<br>-#define SCISSOR_RIGHT_FLAG 0x20<br>-#define SCISSOR_TOP_FLAG 0x40<br>-#define SCISSOR_BOTTOM_FLAG 0x80<br>-<br>-/* ATI VGA Extended Registers */<br>-#define sioATIEXT 0x1ce<br>-#define bioATIEXT 0x3ce<br>-<br>-#define ATI2E 0xae<br>-#define ATI32 0xb2<br>-#define ATI36 0xb6<br>-<br>-/* VGA Graphics Controller Registers */<br>-#define VGAGRA 0x3ce<br>-#define GRA06 0x06<br>-<br>-/* VGA Sequencer Registers */<br>-#define VGASEQ 0x3c4<br>-#define SEQ02 0x02<br>-#define SEQ04 0x04<br>-<br>-#define MACH64_MAX_X ENGINE_MAX_X<br>-#define MACH64_MAX_Y ENGINE_MAX_Y<br>-<br>-#define INC_X 0x0020<br>-#define INC_Y 0x0080<br>-<br>-#define RGB16_555 0x0000<br>-#define RGB16_565 0x0040<br>-#define RGB16_655 0x0080<br>-#define RGB16_664 0x00c0<br>-<br>-#define POLY_TEXT_TYPE 0x0001<br>-#define IMAGE_TEXT_TYPE 0x0002<br>-#define TEXT_TYPE_8_BIT 0x0004<br>-#define TEXT_TYPE_16_BIT 0x0008<br>-#define POLY_TEXT_TYPE_8 (POLY_TEXT_TYPE | TEXT_TYPE_8_BIT)<br>-#define IMAGE_TEXT_TYPE_8 (IMAGE_TEXT_TYPE | TEXT_TYPE_8_BIT)<br>-#define POLY_TEXT_TYPE_16 (POLY_TEXT_TYPE | TEXT_TYPE_16_BIT)<br>-#define IMAGE_TEXT_TYPE_16 (IMAGE_TEXT_TYPE | TEXT_TYPE_16_BIT)<br>-<br>-#define MACH64_NUM_CLOCKS 16<br>-#define MACH64_NUM_FREQS 50<br>-<br>-/* Power Management register constants (LT & LT Pro) */<br>-#define PWR_MGT_ON 0x00000001<br>-#define PWR_MGT_MODE_MASK 0x00000006<br>-#define AUTO_PWR_UP 0x00000008<br>-#define USE_F32KHZ 0x00000400<br>-#define TRISTATE_MEM_EN 0x00000800<br>-#define SELF_REFRESH 0x00000080<br>-#define PWR_BLON 0x02000000<br>-#define STANDBY_NOW 0x10000000<br>-#define SUSPEND_NOW 0x20000000<br>-#define PWR_MGT_STATUS_MASK 0xC0000000<br>-#define PWR_MGT_STATUS_SUSPEND 0x80000000<br>-<br>-/* PM Mode constants */<br>-#define PWR_MGT_MODE_PIN 0x00000000<br>-#define PWR_MGT_MODE_REG 0x00000002<br>-#define PWR_MGT_MODE_TIMER 0x00000004<br>-#define PWR_MGT_MODE_PCI 0x00000006<br>-<br>-/* LCD registers (LT Pro) */<br>-<br>-/* LCD Index register */<br>-#define LCD_INDEX_MASK 0x0000003F<br>-#define LCD_DISPLAY_DIS 0x00000100<br>-#define LCD_SRC_SEL 0x00000200<br>-#define CRTC2_DISPLAY_DIS 0x00000400<br>-<br>-/* LCD register indices */<br>-#define CFG_PANEL 0x00<br>-#define LCD_GEN_CTRL 0x01<br>-#define DSTN_CONTROL 0x02<br>-#define HFB_PITCH_ADDR 0x03<br>-#define HORZ_STRETCHING 0x04<br>-#define VERT_STRETCHING 0x05<br>-#define EXT_VERT_STRETCH 0x06<br>-#define LT_GIO 0x07<br>-#define POWER_MANAGEMENT 0x08<br>-#define ZVGPIO 0x09<br>-#define ICON_CLR0 0x0A<br>-#define ICON_CLR1 0x0B<br>-#define ICON_OFFSET 0x0C<br>-#define ICON_HORZ_VERT_POSN 0x0D<br>-#define ICON_HORZ_VERT_OFF 0x0E<br>-#define ICON2_CLR0 0x0F<br>-#define ICON2_CLR1 0x10<br>-#define ICON2_OFFSET 0x11<br>-#define ICON2_HORZ_VERT_POSN 0x12<br>-#define ICON2_HORZ_VERT_OFF 0x13<br>-#define LCD_MISC_CNTL 0x14<br>-#define APC_CNTL 0x1C<br>-#define POWER_MANAGEMENT_2 0x1D<br>-#define ALPHA_BLENDING 0x25<br>-#define PORTRAIT_GEN_CNTL 0x26<br>-#define APC_CTRL_IO 0x27<br>-#define TEST_IO 0x28<br>-#define TEST_OUTPUTS 0x29<br>-#define DP1_MEM_ACCESS 0x2A<br>-#define DP0_MEM_ACCESS 0x2B<br>-#define DP0_DEBUG_A 0x2C<br>-#define DP0_DEBUG_B 0x2D<br>-#define DP1_DEBUG_A 0x2E<br>-#define DP1_DEBUG_B 0x2F<br>-#define DPCTRL_DEBUG_A 0x30<br>-#define DPCTRL_DEBUG_B 0x31<br>-#define MEMBLK_DEBUG 0x32<br>-#define APC_LUT_AB 0x33<br>-#define APC_LUT_CD 0x34<br>-#define APC_LUT_EF 0x35<br>-#define APC_LUT_GH 0x36<br>-#define APC_LUT_IJ 0x37<br>-#define APC_LUT_KL 0x38<br>-#define APC_LUT_MN 0x39<br>-#define APC_LUT_OP 0x3A<br>-<br>-<br>-/* Values in LCD_MISC_CNTL */<br>-#define BIAS_MOD_LEVEL_MASK 0x0000ff00<br>-#define BIAS_MOD_LEVEL_SHIFT 8<br>-#define BLMOD_EN 0x00010000<br>-#define BIASMOD_EN 0x00020000<br>-<br>-#endif /* REGMACH64_H */<br>diff --git a/src/drivers/ati/ragexl/mach64_ct.c b/src/drivers/ati/ragexl/mach64_ct.c<br>deleted file mode 100644<br>index 9b45f2a..0000000<br>--- a/src/drivers/ati/ragexl/mach64_ct.c<br>+++ /dev/null<br>@@ -1,370 +0,0 @@<br>-#define DEBUG_PLL 0<br>-#define PLL_CRTC_DECODE 0<br>-<br>-/* FIXME: remove the FAIL definition */<br>-#if 0<br>-#define FAIL(x) do { printk(BIOS_DEBUG, x); return -EINVAL; } while (0)<br>-#else<br>-#define FAIL(x)<br>-#endif<br>-<br>-static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per,<br>- struct pll_ct *pll);<br>-static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp,<br>- struct pll_ct *pll);<br>-static int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per,<br>- u8 bpp, union aty_pll *pll);<br>-#if PLL_CRTC_DECODE==1<br>-static u32 aty_pll_ct_to_var(const struct fb_info_aty *info,<br>- const union aty_pll *pll);<br>-#endif<br>-<br>-/* ------------------------------------------------------------------------- */<br>-<br>- /*<br>- * PLL programming (Mach64 CT family)<br>- */<br>-static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp,<br>- struct pll_ct *pll)<br>-{<br>- u32 dsp_xclks_per_row, dsp_loop_latency, dsp_precision, dsp_off, dsp_on;<br>- u32 xclks_per_row, fifo_off, fifo_on, y, fifo_size;<br>- u32 memcntl, n, t_pfc, t_rp, t_ras, t_rcd, t_crd, t_rcc, t_lat;<br>-<br>-#if DEBUG_PLL==1<br>- printk(BIOS_DEBUG, "aty_dsp_gt : mclk_fb_mult=%d\n", pll->mclk_fb_mult);<br>-#endif<br>-<br>- /* (64*xclk/vclk/bpp)<<11 = xclocks_per_row<<11 */<br>- xclks_per_row = ((u32)pll->mclk_fb_mult * (u32)pll->mclk_fb_div *<br>- (u32)pll->vclk_post_div_real * 64) << 11;<br>- xclks_per_row /=<br>- (2 * (u32)pll->vclk_fb_div * (u32)pll->xclk_post_div_real * bpp);<br>-<br>- if (xclks_per_row < (1<<11))<br>- FAIL("Dotclock too high");<br>- if (M64_HAS(FIFO_24)) {<br>- fifo_size = 24;<br>- dsp_loop_latency = 0;<br>- } else {<br>- fifo_size = 32;<br>- dsp_loop_latency = 2;<br>- }<br>- dsp_precision = 0;<br>- y = (xclks_per_row*fifo_size)>>11;<br>- while (y) {<br>- y >>= 1;<br>- dsp_precision++;<br>- }<br>- dsp_precision -= 5;<br>-<br>- /* fifo_off<<6 */<br>- fifo_off = ((xclks_per_row*(fifo_size-1))>>5); // + (3<<6);<br>-<br>- if (info->total_vram > 1*1024*1024) {<br>- switch (info->ram_type) {<br>- case WRAM:<br>- /* >1 MB WRAM */<br>- dsp_loop_latency += 9;<br>- n = 4;<br>- break;<br>- case SDRAM:<br>- case SGRAM:<br>- /* >1 MB SDRAM */<br>- dsp_loop_latency += 8;<br>- n = 2;<br>- break;<br>- default:<br>- /* >1 MB DRAM */<br>- dsp_loop_latency += 6;<br>- n = 3;<br>- break;<br>- }<br>- } else {<br>- if (info->ram_type >= SDRAM) {<br>- /* <2 MB SDRAM */<br>- dsp_loop_latency += 9;<br>- n = 2;<br>- } else {<br>- /* <2 MB DRAM */<br>- dsp_loop_latency += 8;<br>- n = 3;<br>- }<br>- }<br>-<br>- memcntl = aty_ld_le32(MEM_CNTL, info);<br>- t_rcd = ((memcntl >> 10) & 0x03) + 1;<br>- t_crd = ((memcntl >> 12) & 0x01);<br>- t_rp = ((memcntl >> 8) & 0x03) + 1;<br>- t_ras = ((memcntl >> 16) & 0x07) + 1;<br>- t_lat = (memcntl >> 4) & 0x03;<br>-<br>- t_pfc = t_rp + t_rcd + t_crd;<br>-<br>- t_rcc = max(t_rp + t_ras, t_pfc + n);<br>-<br>- /* fifo_on<<6 */<br>- fifo_on = (2 * t_rcc + t_pfc + n - 1) << 6;<br>-<br>- dsp_xclks_per_row = xclks_per_row>>dsp_precision;<br>- dsp_on = fifo_on>>dsp_precision;<br>- dsp_off = fifo_off>>dsp_precision;<br>-<br>- pll->dsp_config = (dsp_xclks_per_row & 0x3fff) |<br>- ((dsp_loop_latency & 0xf)<<16) |<br>- ((dsp_precision & 7)<<20);<br>- pll->dsp_on_off = (dsp_off & 0x7ff) | ((dsp_on & 0x7ff)<<16);<br>- return 0;<br>-}<br>-<br>-<br>-static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per,<br>- struct pll_ct *pll)<br>-{<br>-#if DEBUG_PLL==1<br>- int pllmclk, pllsclk;<br>-#endif<br>- u32 q;<br>-<br>- pll->pll_ref_div = info->pll_per*2*255/info->ref_clk_per;<br>-<br>- /* FIXME: use the VTB/GTB /3 post divider if it's better suited */<br>-<br>- /* actually 8*q */<br>- q = info->ref_clk_per*pll->pll_ref_div*4/info->mclk_per;<br>-<br>- if (q < 16*8 || q > 255*8)<br>- FAIL("mclk out of range\n");<br>- else if (q < 32*8)<br>- pll->mclk_post_div_real = 8;<br>- else if (q < 64*8)<br>- pll->mclk_post_div_real = 4;<br>- else if (q < 128*8)<br>- pll->mclk_post_div_real = 2;<br>- else<br>- pll->mclk_post_div_real = 1;<br>- pll->sclk_fb_div = q*pll->mclk_post_div_real/8;<br>-<br>-#if DEBUG_PLL==1<br>- pllsclk = (1000000 * 2 * pll->sclk_fb_div) /<br>- (info->ref_clk_per * pll->pll_ref_div);<br>-<br>- printk(BIOS_DEBUG, "aty_valid_pll_ct: pllsclk=%d MHz, mclk=%d MHz\n",<br>- pllsclk, pllsclk / pll->mclk_post_div_real);<br>-#endif<br>-<br>- pll->mclk_fb_mult = M64_HAS(MFB_TIMES_4) ? 4 : 2;<br>-<br>- /* actually 8*q */<br>- q = info->ref_clk_per * pll->pll_ref_div * 8 /<br>- (pll->mclk_fb_mult * info->xclk_per);<br>-<br>- if (q < 16*8 || q > 255*8)<br>- FAIL("mclk out of range\n");<br>- else if (q < 32*8)<br>- pll->xclk_post_div_real = 8;<br>- else if (q < 64*8)<br>- pll->xclk_post_div_real = 4;<br>- else if (q < 128*8)<br>- pll->xclk_post_div_real = 2;<br>- else<br>- pll->xclk_post_div_real = 1;<br>- pll->mclk_fb_div = q*pll->xclk_post_div_real/8;<br>-<br>-#if DEBUG_PLL==1<br>- pllmclk = (1000000 * pll->mclk_fb_mult * pll->mclk_fb_div) /<br>- (info->ref_clk_per * pll->pll_ref_div);<br>- printk(BIOS_DEBUG, "aty_valid_pll_ct: pllmclk=%d MHz, xclk=%d MHz\n",<br>- pllmclk, pllmclk / pll->xclk_post_div_real);<br>-#endif<br>-<br>- /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */<br>- q = info->ref_clk_per*pll->pll_ref_div*4/vclk_per; /* actually 8*q */<br>- if (q < 16*8 || q > 255*8)<br>- FAIL("vclk out of range\n");<br>- else if (q < 32*8)<br>- pll->vclk_post_div_real = 8;<br>- else if (q < 64*8)<br>- pll->vclk_post_div_real = 4;<br>- else if (q < 128*8)<br>- pll->vclk_post_div_real = 2;<br>- else<br>- pll->vclk_post_div_real = 1;<br>- pll->vclk_fb_div = q*pll->vclk_post_div_real/8;<br>- return 0;<br>-}<br>-<br>-static void aty_calc_pll_ct(const struct fb_info_aty *info, struct pll_ct *pll)<br>-{<br>- u8 xpostdiv = 0;<br>- u8 mpostdiv = 0;<br>- u8 vpostdiv = 0;<br>-<br>- if (M64_HAS(SDRAM_MAGIC_PLL) && (info->ram_type >= SDRAM))<br>- pll->pll_gen_cntl = 0x64; /* mclk = sclk */<br>- else<br>- pll->pll_gen_cntl = 0xe4; /* mclk = sclk */<br>-<br>- switch (pll->mclk_post_div_real) {<br>- case 1:<br>- mpostdiv = 0;<br>- break;<br>- case 2:<br>- mpostdiv = 1;<br>- break;<br>- case 4:<br>- mpostdiv = 2;<br>- break;<br>- case 8:<br>- mpostdiv = 3;<br>- break;<br>- }<br>-<br>- pll->spll_cntl2 = mpostdiv << 4; /* sclk == pllsclk / mpostdiv */<br>-<br>- switch (pll->xclk_post_div_real) {<br>- case 1:<br>- xpostdiv = 0;<br>- break;<br>- case 2:<br>- xpostdiv = 1;<br>- break;<br>- case 3:<br>- xpostdiv = 4;<br>- break;<br>- case 4:<br>- xpostdiv = 2;<br>- break;<br>- case 8:<br>- xpostdiv = 3;<br>- break;<br>- }<br>-<br>- if (M64_HAS(MAGIC_POSTDIV))<br>- pll->pll_ext_cntl = 0;<br>- else<br>- pll->pll_ext_cntl = xpostdiv; /* xclk == pllmclk / xpostdiv */<br>-<br>- if (pll->mclk_fb_mult == 4)<br>- pll->pll_ext_cntl |= 0x08;<br>-<br>- switch (pll->vclk_post_div_real) {<br>- case 2:<br>- vpostdiv = 1;<br>- break;<br>- case 3:<br>- pll->pll_ext_cntl |= 0x10;<br>- case 1:<br>- vpostdiv = 0;<br>- break;<br>- case 6:<br>- pll->pll_ext_cntl |= 0x10;<br>- case 4:<br>- vpostdiv = 2;<br>- break;<br>- case 12:<br>- pll->pll_ext_cntl |= 0x10;<br>- case 8:<br>- vpostdiv = 3;<br>- break;<br>- }<br>-<br>- pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */<br>- pll->vclk_post_div = vpostdiv;<br>-}<br>-<br>-int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per,<br>- u8 bpp, union aty_pll *pll)<br>-{<br>- int err;<br>- if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))<br>- return err;<br>- if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))<br>- return err;<br>- aty_calc_pll_ct(info, &pll->ct);<br>- return 0;<br>-}<br>-#if CONFIG_CONSOLE_BTEXT<br>-#if PLL_CRTC_DECODE==1<br>-u32 aty_pll_ct_to_var(const struct fb_info_aty *info,<br>- const union aty_pll *pll)<br>-{<br>- u32 ref_clk_per = info->ref_clk_per;<br>- u8 pll_ref_div = pll->ct.pll_ref_div;<br>- u8 vclk_fb_div = pll->ct.vclk_fb_div;<br>- u8 vclk_post_div = pll->ct.vclk_post_div_real;<br>-<br>- return ref_clk_per*pll_ref_div*vclk_post_div/vclk_fb_div/2;<br>-}<br>-#endif<br>-void aty_set_pll_ct(const struct fb_info_aty *info, const union aty_pll *pll)<br>-{<br>-#if DEBUG_PLL==1<br>- printk(BIOS_DEBUG, "aty_set_pll_ct: about to program:\n"<br>- "refdiv=%d, extcntl=0x%02x, mfbdiv=%d\n"<br>- "spllcntl2=0x%02x, sfbdiv=%d, gencntl=0x%02x\n"<br>- "vclkcntl=0x%02x, vpostdiv=0x%02x, vfbdiv=%d\n"<br>- "clocksel=%d\n",<br>- pll->ct.pll_ref_div, pll->ct.pll_ext_cntl,<br>- pll->ct.mclk_fb_div, pll->ct.spll_cntl2,<br>- pll->ct.sclk_fb_div, pll->ct.pll_gen_cntl,<br>- pll->ct.pll_vclk_cntl, pll->ct.vclk_post_div,<br>- pll->ct.vclk_fb_div, aty_ld_le32(CLOCK_CNTL, info) & 0x03);<br>-#endif<br>-<br>- aty_st_pll(PLL_REF_DIV, pll->ct.pll_ref_div, info);<br>-<br>- aty_st_pll(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, info);<br>- aty_st_pll(MCLK_FB_DIV, pll->ct.mclk_fb_div, info); // for XCLK<br>-<br>- aty_st_pll(SPLL_CNTL2, pll->ct.spll_cntl2, info);<br>- aty_st_pll(SCLK_FB_DIV, pll->ct.sclk_fb_div, info); // for MCLK<br>-<br>- aty_st_pll(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, info);<br>-<br>- aty_st_pll(EXT_VPLL_CNTL, 0, info);<br>- aty_st_pll(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, info);<br>- aty_st_pll(VCLK_POST_DIV, pll->ct.vclk_post_div, info);<br>- aty_st_pll(VCLK0_FB_DIV, pll->ct.vclk_fb_div, info);<br>-<br>- if (M64_HAS(GTB_DSP)) {<br>- u8 dll_cntl;<br>-<br>- if (M64_HAS(XL_DLL))<br>- dll_cntl = 0x80;<br>- else if (info->ram_type >= SDRAM)<br>- dll_cntl = 0xa6;<br>- else<br>- dll_cntl = 0xa0;<br>- aty_st_pll(DLL_CNTL, dll_cntl, info);<br>- aty_st_pll(VFC_CNTL, 0x1b, info);<br>- aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, info);<br>- aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, info);<br>-<br>- mdelay(10);<br>- aty_st_pll(DLL_CNTL, dll_cntl, info);<br>- mdelay(10);<br>- aty_st_pll(DLL_CNTL, dll_cntl | 0x40, info);<br>- mdelay(10);<br>- aty_st_pll(DLL_CNTL, dll_cntl & ~0x40, info);<br>- }<br>-}<br>-#if 0<br>-static int dummy(void)<br>-{<br>- return 0;<br>-}<br>-static struct aty_dac_ops aty_dac_ct = {<br>- set_dac: (void *)dummy,<br>-};<br>-<br>-static struct aty_pll_ops aty_pll_ct = {<br>- var_to_pll: aty_var_to_pll_ct,<br>-#if 0<br>- pll_to_var: aty_pll_ct_to_var,<br>- set_pll: aty_set_pll_ct,<br>-#endif<br>-};<br>-#endif<br>-<br>-#endif /* CONFIG_CONSOLE_BTEXT */<br>diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c<br>deleted file mode 100644<br>index c5d4404..0000000<br>--- a/src/drivers/ati/ragexl/xlinit.c<br>+++ /dev/null<br>@@ -1,1518 +0,0 @@<br>-/*<br>- * ATI Rage XL Initialization. Support for Xpert98 and Victoria<br>- * PCI cards.<br>- *<br>- * Copyright (C) 2002 MontaVista Software Inc.<br>- * Author: MontaVista Software, Inc.<br>- * stevel@mvista.com or source@mvista.com<br>- * Copyright (C) 2004 Tyan Computer.<br>- * Auther: Yinghai Lu yhlu@tyan.com<br>- * move to coreboot<br>- * This code is distributed without warranty under the GPL v2 (see COPYING) *<br>- */<br>-#include <delay.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include <arch/io.h><br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-<br>-// FIXME BTEXT console within coreboot has been obsoleted<br>-// and will go away. The BTEXT code in this file should be<br>-// fixed to export a framebuffer console through the coreboot<br>-// table (and possibly make it available for bootsplash use)<br>-// Hence do only remove this if you fix the code.<br>-#define CONFIG_CONSOLE_BTEXT 0<br>-<br>-#if CONFIG_CONSOLE_BTEXT<br>-<br>-#define PLL_CRTC_DECODE 0<br>-#define SUPPORT_8_BPP_ABOVE 0<br>-<br>-#include "fb.h"<br>-#include "fbcon.h"<br>-<br>-struct aty_cmap_regs {<br>- u8 windex;<br>- u8 lut;<br>- u8 mask;<br>- u8 rindex;<br>- u8 cntl;<br>-};<br>-<br>-#include <console/btext.h><br>-<br>-#endif /*CONFIG_CONSOLE_BTEXT*/<br>-<br>-#include "mach64.h"<br>-<br>-#include "atyfb.h"<br>-<br>-#include "mach64_ct.c"<br>-<br>-#define MPLL_GAIN 0xad<br>-#define VPLL_GAIN 0xd5<br>-<br>-#define HAS_VICTORIA 0<br>-<br>-enum {<br>-#if HAS_VICTORIA==1<br>- VICTORIA = 0,<br>- XPERT98,<br>-#else<br>- XPERT98=0,<br>-#endif<br>- NUM_XL_CARDS<br>-};<br>-<br>-//static struct aty_pll_ops aty_pll_ct;<br>-<br>-#define DEFAULT_CARD XPERT98<br>-static int xl_card = DEFAULT_CARD;<br>-<br>-static const struct xl_card_cfg_t {<br>- int ref_crystal; // 10^4 Hz<br>- int mem_type;<br>- int mem_size;<br>- u32 mem_cntl;<br>- u32 ext_mem_cntl;<br>- u32 mem_addr_config;<br>- u32 bus_cntl;<br>- u32 dac_cntl;<br>- u32 hw_debug;<br>- u32 custom_macro_cntl;<br>- u8 dll2_cntl;<br>- u8 pll_yclk_cntl;<br>-} card_cfg[NUM_XL_CARDS] = {<br>-#if HAS_VICTORIA==1<br>- // VICTORIA<br>- { 2700, SDRAM, 0x800000,<br>- 0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040,<br>- 0x82010102, 0x48803800, 0x005E0179,<br>- 0x50, 0x25<br>- },<br>-#endif<br>- // XPERT98<br>- { 1432, WRAM, 0x800000,<br>- 0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001,<br>- 0x8000000A, 0x48833800, 0x007F0779,<br>- 0x10, 0x19<br>- }<br>-};<br>-<br>-typedef struct {<br>- u8 lcd_reg;<br>- u32 val;<br>-} lcd_tbl_t;<br>-<br>-static const lcd_tbl_t lcd_tbl[] = {<br>- { 0x01, 0x000520C0 },<br>- { 0x08, 0x02000408 },<br>- { 0x03, 0x00000F00 },<br>- { 0x00, 0x00000000 },<br>- { 0x02, 0x00000000 },<br>- { 0x04, 0x00000000 },<br>- { 0x05, 0x00000000 },<br>- { 0x06, 0x00000000 },<br>- { 0x33, 0x00000000 },<br>- { 0x34, 0x00000000 },<br>- { 0x35, 0x00000000 },<br>- { 0x36, 0x00000000 },<br>- { 0x37, 0x00000000 }<br>-};<br>-<br>-static inline u32 aty_ld_lcd(u8 lcd_reg, struct fb_info_aty *info)<br>-{<br>- aty_st_8(LCD_INDEX, lcd_reg, info);<br>- return aty_ld_le32(LCD_DATA, info);<br>-}<br>-<br>-static inline void aty_st_lcd(u8 lcd_reg, u32 val,<br>- struct fb_info_aty *info)<br>-{<br>- aty_st_8(LCD_INDEX, lcd_reg, info);<br>- aty_st_le32(LCD_DATA, val, info);<br>-}<br>-<br>-static void reset_gui(struct fb_info_aty *info)<br>-{<br>- aty_st_8(GEN_TEST_CNTL+1, 0x01, info);<br>- aty_st_8(GEN_TEST_CNTL+1, 0x00, info);<br>- aty_st_8(GEN_TEST_CNTL+1, 0x02, info);<br>- mdelay(5);<br>-}<br>-<br>-<br>-static void reset_sdram(struct fb_info_aty *info)<br>-{<br>- u8 temp;<br>-<br>- temp = aty_ld_8(EXT_MEM_CNTL, info);<br>- temp |= 0x02;<br>- aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_RESET = 1b<br>- temp |= 0x08;<br>- aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 10b<br>- temp |= 0x0c;<br>- aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 11b<br>- mdelay(5);<br>- temp &= 0xf3;<br>- aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 00b<br>- temp &= 0xfd;<br>- aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_REST = 0b<br>- mdelay(5);<br>-}<br>-<br>-static void init_dll(struct fb_info_aty *info)<br>-{<br>- // enable DLL<br>- aty_st_pll(PLL_GEN_CNTL,<br>- aty_ld_pll(PLL_GEN_CNTL, info) & 0x7f,<br>- info);<br>-<br>- // reset DLL<br>- aty_st_pll(DLL_CNTL, 0x82, info);<br>- aty_st_pll(DLL_CNTL, 0xE2, info);<br>- mdelay(5);<br>- aty_st_pll(DLL_CNTL, 0x82, info);<br>- mdelay(6);<br>-}<br>-<br>-static void reset_clocks(struct fb_info_aty *info, struct pll_ct *pll,<br>- int hsync_enb)<br>-{<br>- reset_gui(info);<br>- aty_st_pll(MCLK_FB_DIV, pll->mclk_fb_div, info);<br>- aty_st_pll(SCLK_FB_DIV, pll->sclk_fb_div, info);<br>-<br>- mdelay(15);<br>- init_dll(info);<br>- aty_st_8(GEN_TEST_CNTL+1, 0x00, info);<br>- mdelay(5);<br>- aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);<br>- mdelay(6);<br>- reset_sdram(info);<br>- aty_st_8(CRTC_GEN_CNTL+3,<br>- hsync_enb ? 0x00 : 0x04, info);<br>-<br>- aty_st_pll(SPLL_CNTL2, pll->spll_cntl2, info);<br>- aty_st_pll(PLL_GEN_CNTL, pll->pll_gen_cntl, info);<br>- aty_st_pll(PLL_VCLK_CNTL, pll->pll_vclk_cntl, info);<br>-}<br>-<br>-static int atyfb_xl_init(struct fb_info_aty *info)<br>-{<br>- int i, err;<br>- u32 temp;<br>- union aty_pll pll;<br>- const struct xl_card_cfg_t * card = &card_cfg[xl_card];<br>-<br>- aty_st_8(CFG_STAT0, 0x85, info);<br>- mdelay(10);<br>-<br>- /*<br>- * The following needs to be set before the call<br>- * to var_to_pll() below. They'll be re-set again<br>- * to the same values in aty_init().<br>- */<br>- info->ref_clk_per = 100000000UL/card->ref_crystal;<br>- info->ram_type = card->mem_type;<br>- info->total_vram = card->mem_size;<br>-#if HAS_VICTORIA == 1<br>- if (xl_card == VICTORIA) {<br>- // the MCLK, XCLK are 120MHz on victoria card<br>- info->mclk_per = 1000000/120;<br>- info->xclk_per = 1000000/120;<br>- info->features &= ~M64F_MFB_TIMES_4;<br>- }<br>-#endif<br>-<br>- /*<br>- * Calculate mclk and xclk dividers, etc. The passed<br>- * pixclock and bpp values don't matter yet, the vclk<br>- * isn't programmed until later.<br>- */<br>- if ((err = aty_var_to_pll_ct(info, 39726, 8, &pll))) return err;<br>-// if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll))) return err;<br>-<br>-<br>- aty_st_pll(LVDS_CNTL0, 0x00, info);<br>- aty_st_pll(DLL2_CNTL, card->dll2_cntl, info);<br>- aty_st_pll(V2PLL_CNTL, 0x10, info);<br>- aty_st_pll(MPLL_CNTL, MPLL_GAIN, info);<br>- aty_st_pll(VPLL_CNTL, VPLL_GAIN, info);<br>- aty_st_pll(PLL_VCLK_CNTL, 0x00, info);<br>- aty_st_pll(VFC_CNTL, 0x1B, info);<br>- aty_st_pll(PLL_REF_DIV, pll.ct.pll_ref_div, info);<br>- aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, info);<br>- aty_st_pll(SPLL_CNTL2, 0x03, info);<br>- aty_st_pll(PLL_GEN_CNTL, 0x44, info);<br>-<br>- reset_clocks(info, &pll.ct, 0);<br>- mdelay(10);<br>-<br>- aty_st_pll(VCLK_POST_DIV, 0x03, info);<br>- aty_st_pll(VCLK0_FB_DIV, 0xDA, info);<br>- aty_st_pll(VCLK_POST_DIV, 0x0F, info);<br>- aty_st_pll(VCLK1_FB_DIV, 0xF5, info);<br>- aty_st_pll(VCLK_POST_DIV, 0x3F, info);<br>- aty_st_pll(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, info);<br>- aty_st_pll(VCLK2_FB_DIV, 0x00, info);<br>- aty_st_pll(VCLK_POST_DIV, 0xFF, info);<br>- aty_st_pll(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, info);<br>- aty_st_pll(VCLK3_FB_DIV, 0x00, info);<br>-<br>- aty_st_8(BUS_CNTL, 0x01, info);<br>- aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, info);<br>-<br>- aty_st_le32(CRTC_GEN_CNTL, 0x04000200, info);<br>- aty_st_le16(CFG_STAT0, 0x0020, info);<br>- aty_st_le32(MEM_CNTL, 0x10151A33, info);<br>- aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, info);<br>- aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, info);<br>- aty_st_le32(DAC_CNTL, card->dac_cntl, info);<br>- aty_st_le16(GEN_TEST_CNTL, 0x0100, info);<br>- aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, info);<br>- aty_st_le32(MEM_BUF_CNTL, 0x00382848, info);<br>-<br>- aty_st_le32(HW_DEBUG, card->hw_debug, info);<br>- aty_st_le16(MEM_ADDR_CONFIG, 0x0000, info);<br>- aty_st_le16(GP_IO+2, 0x0000, info);<br>- aty_st_le16(GEN_TEST_CNTL, 0x0000, info);<br>- aty_st_le16(EXT_DAC_REGS+2, 0x0000, info);<br>- aty_st_le32(CRTC_INT_CNTL, 0x00000000, info);<br>- aty_st_le32(TIMER_CONFIG, 0x00000000, info);<br>- aty_st_le32(0xEC, 0x00000000, info);<br>- aty_st_le32(0xFC, 0x00000000, info);<br>-<br>- for (i=0; i<ARRAY_SIZE(lcd_tbl); i++) {<br>- aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);<br>- }<br>-<br>- aty_st_le16(CFG_STAT0, 0x00A4, info);<br>- mdelay(10);<br>-<br>- aty_st_8(BUS_CNTL+1, 0xA0, info);<br>- mdelay(10);<br>-<br>- reset_clocks(info, &pll.ct, 1);<br>- mdelay(10);<br>-<br>- // something about power management<br>- aty_st_8(LCD_INDEX, 0x08, info);<br>- aty_st_8(LCD_DATA, 0x0A, info);<br>- aty_st_8(LCD_INDEX, 0x08, info);<br>- aty_st_8(LCD_DATA+3, 0x02, info);<br>- aty_st_8(LCD_INDEX, 0x08, info);<br>- aty_st_8(LCD_DATA, 0x0B, info);<br>- mdelay(2);<br>-<br>- // enable display requests, enable CRTC<br>- aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);<br>- // disable display<br>- aty_st_8(CRTC_GEN_CNTL, 0x40, info);<br>- // disable display requests, disable CRTC<br>- aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);<br>- mdelay(10);<br>-<br>- aty_st_pll(PLL_YCLK_CNTL, 0x25, info);<br>-<br>- aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, info);<br>- aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, info);<br>- aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, info);<br>- aty_st_8(CUSTOM_MACRO_CNTL+1,<br>- (card->custom_macro_cntl>>8) & 0xff, info);<br>-<br>- aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, info);<br>- aty_st_le32(MEM_CNTL, card->mem_cntl, info);<br>- aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, info);<br>-<br>- aty_st_8(CFG_STAT0, 0xA0 | card->mem_type, info);<br>-<br>- aty_st_pll(PLL_YCLK_CNTL, 0x01, info);<br>- mdelay(15);<br>- aty_st_pll(PLL_YCLK_CNTL, card->pll_yclk_cntl, info);<br>- mdelay(1);<br>-<br>- reset_clocks(info, &pll.ct, 0);<br>- mdelay(50);<br>- reset_clocks(info, &pll.ct, 0);<br>- mdelay(50);<br>-<br>- // enable extended register block<br>- aty_st_8(BUS_CNTL+3, 0x7B, info);<br>- mdelay(1);<br>- // disable extended register block<br>- aty_st_8(BUS_CNTL+3, 0x73, info);<br>-<br>- aty_st_8(CFG_STAT0, 0x80 | card->mem_type, info);<br>-<br>- // disable display requests, disable CRTC<br>- aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);<br>- // disable mapping registers in VGA aperture<br>- aty_st_8(CFG_CNTL, aty_ld_8(CFG_CNTL, info) & ~0x04, info);<br>- mdelay(50);<br>- // enable display requests, enable CRTC<br>- aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);<br>-<br>- // make GPIO's 14,15,16 all inputs<br>- aty_st_8(LCD_INDEX, 0x07, info);<br>- aty_st_8(LCD_DATA+3, 0x00, info);<br>-<br>- // enable the display<br>- aty_st_8(CRTC_GEN_CNTL, 0x00, info);<br>- mdelay(17);<br>- // reset the memory controller<br>- aty_st_8(GEN_TEST_CNTL+1, 0x02, info);<br>- mdelay(15);<br>- aty_st_8(GEN_TEST_CNTL+1, 0x00, info);<br>- mdelay(30);<br>-<br>- // enable extended register block<br>- aty_st_8(BUS_CNTL+3,<br>- (u8)(aty_ld_8(BUS_CNTL+3, info) | 0x08),<br>- info);<br>- // set FIFO size to 512 (PIO)<br>- aty_st_le32(GUI_CNTL,<br>- aty_ld_le32(GUI_CNTL, info) & ~0x3,<br>- info);<br>-<br>- // enable CRT and disable lcd<br>- aty_st_8(LCD_INDEX, 0x01, info);<br>- temp = aty_ld_le32(LCD_DATA, info);<br>- temp = (temp | 0x01) & ~0x02;<br>- aty_st_le32(LCD_DATA, temp, info);<br>-<br>- return 0;<br>-}<br>-<br>-static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)";<br>-static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)";<br>-<br>-<br>-#if CONFIG_CONSOLE_BTEXT<br>-static void aty_set_crtc(const struct fb_info_aty *info,<br>- const struct crtc *crtc);<br>-static int aty_var_to_crtc(const struct fb_info_aty *info,<br>- const struct fb_var_screeninfo *var,<br>- struct crtc *crtc);<br>-#if PLL_CRTC_DECODE==1<br>-static int aty_crtc_to_var(const struct crtc *crtc,<br>- struct fb_var_screeninfo *var);<br>-#endif<br>-<br>-static void atyfb_set_par(const struct atyfb_par *par,<br>- struct fb_info_aty *info);<br>-static int atyfb_decode_var(const struct fb_var_screeninfo *var,<br>- struct atyfb_par *par,<br>- const struct fb_info_aty *info);<br>-#if PLL_CRTC_DECODE==1<br>-static int atyfb_encode_var(struct fb_var_screeninfo *var,<br>- const struct atyfb_par *par,<br>- const struct fb_info_aty *info);<br>-#endif<br>-<br>-static void do_install_cmap(int con, struct fb_info_aty *info);<br>-<br>-#if 0<br>-static u32 default_vram = 0;<br>-#endif<br>-<br>-unsigned char color_table[] = { 0, 4, 2, 6, 1, 5, 3, 7,<br>- 8,12,10,14, 9,13,11,15 };<br>-#if 0<br>-/* the default colour table, for VGA+ colour systems */<br>-int default_red[] = {0x00,0xaa,0x00,0xaa,0x00,0xaa,0x00,0xaa,<br>- 0x55,0xff,0x55,0xff,0x55,0xff,0x55,0xff};<br>-int default_grn[] = {0x00,0x00,0xaa,0x55,0x00,0x00,0xaa,0xaa,<br>- 0x55,0x55,0xff,0xff,0x55,0x55,0xff,0xff};<br>-int default_blu[] = {0x00,0x00,0x00,0x00,0xaa,0xaa,0xaa,0xaa,<br>- 0x55,0x55,0x55,0x55,0xff,0xff,0xff,0xff};<br>-#endif<br>-<br>-struct fb_var_screeninfo default_var = {<br>- /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */<br>- 640, 480, 640, 480, 0, 0, 8, 0,<br>- {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},<br>- 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,<br>- 0, FB_VMODE_NONINTERLACED<br>-};<br>-<br>-#endif /*CONFIG_CONSOLE_BTEXT*/<br>-<br>-static struct {<br>- u16 pci_id, chip_type;<br>- u8 rev_mask, rev_val;<br>- const char *name;<br>- int pll, mclk, xclk;<br>- u32 features;<br>-} aty_chips[] = {<br>- /* 3D RAGE XL PCI-66/BGA */<br>- { 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },<br>- /* 3D RAGE XL PCI-33/BGA */<br>- { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },<br>-};<br>-#if CONFIG_CONSOLE_BTEXT<br>-static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk)<br>-{<br>- int i, size;<br>-#if 0<br>- const int ragepro_tbl[] = {<br>- 44, 50, 55, 66, 75, 80, 100<br>- };<br>-#endif<br>- const int ragexl_tbl[] = {<br>- 50, 66, 75, 83, 90, 95, 100, 105,<br>- 110, 115, 120, 125, 133, 143, 166<br>- };<br>- const int *refresh_tbl;<br>-#if 0<br>- if (IS_XL(id)) {<br>-#endif<br>- refresh_tbl = ragexl_tbl;<br>- size = sizeof(ragexl_tbl)/sizeof(int);<br>-#if 0<br>- } else {<br>- refresh_tbl = ragepro_tbl;<br>- size = sizeof(ragepro_tbl)/sizeof(int);<br>- }<br>-#endif<br>-<br>- for (i=0; i < size; i++) {<br>- if (xclk < refresh_tbl[i])<br>- break;<br>- }<br>-<br>- info->mem_refresh_rate = i;<br>-}<br>-#endif /*CONFIG_CONSOLE_BTEXT */<br>-static void ati_ragexl_init(struct device *dev)<br>-{<br>- u32 chip_id;<br>- int j;<br>- u16 type;<br>- u8 rev;<br>- const char *chipname = NULL;<br>-#if CONFIG_CONSOLE_BTEXT<br>- u32 i;<br>- const char *xtal;<br>-#endif<br>- int pll, mclk, xclk;<br>-<br>-#if CONFIG_CONSOLE_BTEXT<br>-<br>-#if 0<br>- int gtb_memsize, k;<br>-#endif<br>-<br>- struct fb_var_screeninfo var;<br>-#if 0<br>- struct display *disp;<br>-#endif<br>-<br>-#if 0<br>- u8 pll_ref_div;<br>-#endif<br>-<br>-#endif /*CONFIG_CONSOLE_BTEXT==1 */<br>-<br>- struct fb_info_aty *info;<br>- struct fb_info_aty info_t;<br>- struct resource *res;<br>- info = &info_t;<br>-<br>-#define USE_AUX_REG 1<br>-<br>-<br>- res = dev->resource_list;<br>- if (res->flags & IORESOURCE_IO) {<br>- res = res->next;<br>- }<br>-<br>-#if CONFIG_CONSOLE_BTEXT<br>- info->frame_buffer = res->base;<br>-#endif /* CONFIG_CONSOLE_BTEXT */<br>-<br>-#if USE_AUX_REG==0<br>- info->ati_regbase = res2mmio(res, 0x7ff000+0xc00, 0);<br>-#else<br>- /* Fix this to look for the correct index. */<br>- //if (dev->resource_list && dev->resource_list->next)<br>- res = dev->resource_list->next->next;<br>- if (res->flags & IORESOURCE_MEM) {<br>- info->ati_regbase = res2mmio(res, 0x400, 0); //using auxiliary register<br>- }<br>-<br>-#endif<br>-<br>-#if CONFIG_CONSOLE_BTEXT<br>- info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0);<br>-#endif<br>-<br>-#if 0<br>- printk(BIOS_DEBUG, "ati_regbase = 0x%p, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);<br>-#endif<br>-<br>- chip_id = aty_ld_le32(CFG_CHIP_ID, info);<br>- type = chip_id & CFG_CHIP_TYPE;<br>- rev = (chip_id & CFG_CHIP_REV)>>24;<br>- for (j = 0; j < ARRAY_SIZE(aty_chips); j++)<br>- if (type == aty_chips[j].chip_type &&<br>- (rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) {<br>- chipname = aty_chips[j].name;<br>- pll = aty_chips[j].pll;<br>- mclk = aty_chips[j].mclk;<br>- xclk = aty_chips[j].xclk;<br>- info->features = aty_chips[j].features;<br>- goto found;<br>- }<br>- printk(BIOS_SPEW, "ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);<br>- return ;<br>-<br>-found:<br>- printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev);<br>-#if 0<br>- if (M64_HAS(INTEGRATED)) {<br>- /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */<br>- if (mclk == 67 && info->ram_type < SDRAM)<br>- mclk = 63;<br>- }<br>-#endif<br>-#if CONFIG_CONSOLE_BTEXT<br>- aty_calc_mem_refresh(info, type, xclk);<br>-#endif /* CONFIG_CONSOLE_BTEXT */<br>-<br>- info->pll_per = 1000000/pll;<br>- info->mclk_per = 1000000/mclk;<br>- info->xclk_per = 1000000/xclk;<br>-<br>-// info->dac_ops = &aty_dac_ct;<br>-// info->pll_ops = &aty_pll_ct;<br>- info->bus_type = PCI;<br>-<br>-<br>- atyfb_xl_init(info);<br>-<br>-#if CONFIG_CONSOLE_BTEXT<br>-<br>- info->ram_type = (aty_ld_le32(CFG_STAT0, info) & 0x07);<br>-<br>- info->ref_clk_per = 1000000000000ULL/14318180;<br>- xtal = "14.31818";<br>-#if 0<br>- if (M64_HAS(GTB_DSP) && (pll_ref_div = aty_ld_pll(PLL_REF_DIV, info))) {<br>- int diff1, diff2;<br>- diff1 = 510*14/pll_ref_div-pll;<br>- diff2 = 510*29/pll_ref_div-pll;<br>- if (diff1 < 0)<br>- diff1 = -diff1;<br>- if (diff2 < 0)<br>- diff2 = -diff2;<br>- if (diff2 < diff1) {<br>- info->ref_clk_per = 1000000000000ULL/29498928;<br>- xtal = "29.498928";<br>- }<br>- }<br>-#endif<br>-<br>- i = aty_ld_le32(MEM_CNTL, info);<br>-#if 0<br>- gtb_memsize = M64_HAS(GTB_DSP);<br>- if (gtb_memsize) // We have<br>-#endif<br>- switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */<br>- case MEM_SIZE_512K:<br>- info->total_vram = 0x80000;<br>- break;<br>- case MEM_SIZE_1M:<br>- info->total_vram = 0x100000;<br>- break;<br>- case MEM_SIZE_2M_GTB:<br>- info->total_vram = 0x200000;<br>- break;<br>- case MEM_SIZE_4M_GTB:<br>- info->total_vram = 0x400000;<br>- break;<br>- case MEM_SIZE_6M_GTB:<br>- info->total_vram = 0x600000;<br>- break;<br>- case MEM_SIZE_8M_GTB:<br>- info->total_vram = 0x800000;<br>- break;<br>- default:<br>- info->total_vram = 0x80000;<br>- }<br>-#if 0<br>- else<br>- switch (i & MEM_SIZE_ALIAS) {<br>- case MEM_SIZE_512K:<br>- info->total_vram = 0x80000;<br>- break;<br>- case MEM_SIZE_1M:<br>- info->total_vram = 0x100000;<br>- break;<br>- case MEM_SIZE_2M:<br>- info->total_vram = 0x200000;<br>- break;<br>- case MEM_SIZE_4M:<br>- info->total_vram = 0x400000;<br>- break;<br>- case MEM_SIZE_6M:<br>- info->total_vram = 0x600000;<br>- break;<br>- case MEM_SIZE_8M:<br>- info->total_vram = 0x800000;<br>- break;<br>- default:<br>- info->total_vram = 0x80000;<br>- }<br>-#endif<br>-<br>- if (M64_HAS(MAGIC_VRAM_SIZE)) {<br>- if (aty_ld_le32(CFG_STAT1, info) & 0x40000000)<br>- info->total_vram += 0x400000;<br>- }<br>-#if 0<br>- if (default_vram) {<br>- info->total_vram = default_vram*1024;<br>- i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);<br>- if (info->total_vram <= 0x80000)<br>- i |= MEM_SIZE_512K;<br>- else if (info->total_vram <= 0x100000)<br>- i |= MEM_SIZE_1M;<br>- else if (info->total_vram <= 0x200000)<br>- i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;<br>- else if (info->total_vram <= 0x400000)<br>- i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;<br>- else if (info->total_vram <= 0x600000)<br>- i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;<br>- else<br>- i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;<br>- aty_st_le32(MEM_CNTL, i, info);<br>- }<br>-#endif<br>-<br>- /* Clear the video memory */<br>-// fb_memset((void *)info->frame_buffer, 0, info->total_vram);<br>-#if 0<br>- disp = &info->disp;<br>-<br>-// strcpy(info->fb_info.modename, atyfb_name);<br>- info->fb_info.node = -1;<br>-// info->fb_info.fbops = &atyfb_ops;<br>- info->fb_info.disp = disp;<br>-// strcpy(info->fb_info.fontname, fontname);<br>- info->fb_info.changevar = NULL;<br>-// info->fb_info.switch_con = &atyfbcon_switch;<br>-// info->fb_info.updatevar = &atyfbcon_updatevar;<br>-// info->fb_info.blank = &atyfbcon_blank;<br>- info->fb_info.flags = FBINFO_FLAG_DEFAULT;<br>-#endif<br>- var = default_var;<br>-<br>-#if 0<br>- if (noaccel) // We has noaccel in default<br>- var.accel_flags &= ~FB_ACCELF_TEXT;<br>- else<br>- var.accel_flags |= FB_ACCELF_TEXT;<br>-#endif<br>-<br>- if (var.yres == var.yres_virtual) {<br>- u32 vram = info->total_vram ;<br>- var.yres_virtual = ((vram * 8) / var.bits_per_pixel) / var.xres_virtual;<br>- if (var.yres_virtual < var.yres)<br>- var.yres_virtual = var.yres;<br>- }<br>-<br>- if (atyfb_decode_var(&var, &info->default_par, info)) {<br>-#if 0<br>- printk(BIOS_DEBUG, "atyfb: can't set default video mode\n");<br>-#endif<br>- return ;<br>- }<br>-#if 0<br>- for (j = 0; j < 16; j++) {<br>- k = color_table[j];<br>- info->palette[j].red = default_red[k];<br>- info->palette[j].green = default_grn[k];<br>- info->palette[j].blue = default_blu[k];<br>- }<br>-#endif<br>-<br>-#if 0<br>- if (curblink && M64_HAS(INTEGRATED)) {<br>- info->cursor = aty_init_cursor(info);<br>- if (info->cursor) {<br>- info->dispsw.cursor = atyfb_cursor;<br>- info->dispsw.set_font = atyfb_set_font;<br>- }<br>- }<br>-#endif<br>-<br>-#if PLL_CRTC_DECODE==1<br>- atyfb_set_var(&var, -1, &info->fb_info);<br>-#else<br>- atyfb_set_par(&info->default_par, info);<br>-// do_install_cmap(-1, &info->fb_info);<br>- do_install_cmap(-1, info);<br>-#endif<br>-<br>-#if PLL_CRTC_DECODE==1<br>-<br>- printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,<br>- (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,<br>- ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,<br>- info->current_par.crtc.bpp,<br>- info->current_par.crtc.vxres*info->default_par.crtc.bpp/8<br>- );<br>- btext_setup_display(<br>- (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,<br>- ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,<br>- info->current_par.crtc.bpp,<br>- info->current_par.crtc.vxres*info->current_par.crtc.bpp/8,info->frame_buffer);<br>-#else<br>- printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,<br>- (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,<br>- ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,<br>- info->default_par.crtc.bpp,<br>- info->default_par.crtc.vxres*info->default_par.crtc.bpp/8<br>- );<br>- btext_setup_display(<br>- (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,<br>- ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,<br>- info->default_par.crtc.bpp,<br>- info->default_par.crtc.vxres*info->default_par.crtc.bpp/8,info->frame_buffer);<br>-#endif<br>-<br>- btext_clearscreen();<br>-<br>- map_boot_text();<br>-<br>-#if 0<br>-<br>- btext_drawstring("test framebuffer\n");<br>-<br>- mdelay(10000);<br>-// test end<br>-#endif<br>-<br>-#endif /* CONFIG_CONSOLE_BTEXT */<br>-<br>-}<br>-<br>-#if CONFIG_CONSOLE_BTEXT<br>-<br>-static int atyfb_decode_var(const struct fb_var_screeninfo *var,<br>- struct atyfb_par *par,<br>- const struct fb_info_aty *info)<br>-{<br>- int err;<br>-<br>- if ((err = aty_var_to_crtc(info, var, &par->crtc)) ||<br>- (err = aty_var_to_pll_ct(info, var->pixclock, par->crtc.bpp,<br>- &par->pll)))<br>- return err;<br>-<br>-#if 0<br>- if (var->accel_flags & FB_ACCELF_TEXT)<br>- par->accel_flags = FB_ACCELF_TEXT;<br>- else<br>-#endif<br>- par->accel_flags = 0;<br>-<br>-#if 0 /* fbmon is not done. uncomment for 2.5.x -brad */<br>- if (!fbmon_valid_timings(var->pixclock, htotal, vtotal, info))<br>- return -EINVAL;<br>-#endif<br>-<br>- return 0;<br>-}<br>-#if PLL_CRTC_DECODE==1<br>-static int atyfb_encode_var(struct fb_var_screeninfo *var,<br>- const struct atyfb_par *par,<br>- const struct fb_info_aty *info)<br>-{<br>- int err;<br>-<br>- memset(var, 0, sizeof(struct fb_var_screeninfo));<br>-<br>- if ((err = aty_crtc_to_var(&par->crtc, var)))<br>- return err;<br>- var->pixclock = aty_pll_ct_to_var(info, &par->pll);<br>-<br>- var->height = -1;<br>- var->width = -1;<br>- var->accel_flags = par->accel_flags;<br>-<br>- return 0;<br>-}<br>-#endif<br>-static void aty_set_crtc(const struct fb_info_aty *info,<br>- const struct crtc *crtc)<br>-{<br>- aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, info);<br>- aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, info);<br>- aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, info);<br>- aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, info);<br>- aty_st_le32(CRTC_VLINE_CRNT_VLINE, 0, info);<br>- aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, info);<br>- aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, info);<br>-}<br>-<br>-static int aty_var_to_crtc(const struct fb_info_aty *info,<br>- const struct fb_var_screeninfo *var,<br>- struct crtc *crtc)<br>-{<br>- u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;<br>- u32 left, right, upper, lower, hslen, vslen, sync, vmode;<br>- u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;<br>- u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;<br>- u32 pix_width, dp_pix_width, dp_chain_mask;<br>-<br>- /* input */<br>- xres = var->xres;<br>- yres = var->yres;<br>- vxres = var->xres_virtual;<br>- vyres = var->yres_virtual;<br>- xoffset = var->xoffset;<br>- yoffset = var->yoffset;<br>- bpp = var->bits_per_pixel;<br>- left = var->left_margin;<br>- right = var->right_margin;<br>- upper = var->upper_margin;<br>- lower = var->lower_margin;<br>- hslen = var->hsync_len;<br>- vslen = var->vsync_len;<br>- sync = var->sync;<br>- vmode = var->vmode;<br>-<br>- /* convert (and round up) and validate */<br>- xres = (xres+7) & ~7;<br>- xoffset = (xoffset+7) & ~7;<br>- vxres = (vxres+7) & ~7;<br>- if (vxres < xres+xoffset)<br>- vxres = xres+xoffset;<br>- h_disp = xres/8-1;<br>- if (h_disp > 0xff)<br>- FAIL("h_disp too large");<br>- h_sync_strt = h_disp+(right/8);<br>- if (h_sync_strt > 0x1ff)<br>- FAIL("h_sync_start too large");<br>- h_sync_dly = right & 7;<br>- h_sync_wid = (hslen+7)/8;<br>- if (h_sync_wid > 0x1f)<br>- FAIL("h_sync_wid too large");<br>- h_total = h_sync_strt+h_sync_wid+(h_sync_dly+left+7)/8;<br>- if (h_total > 0x1ff)<br>- FAIL("h_total too large");<br>- h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;<br>-<br>- if (vyres < yres+yoffset)<br>- vyres = yres+yoffset;<br>- v_disp = yres-1;<br>- if (v_disp > 0x7ff)<br>- FAIL("v_disp too large");<br>- v_sync_strt = v_disp+lower;<br>- if (v_sync_strt > 0x7ff)<br>- FAIL("v_sync_strt too large");<br>- v_sync_wid = vslen;<br>- if (v_sync_wid > 0x1f)<br>- FAIL("v_sync_wid too large");<br>- v_total = v_sync_strt+v_sync_wid+upper;<br>- if (v_total > 0x7ff)<br>- FAIL("v_total too large");<br>- v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;<br>-<br>- c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;<br>-<br>- if (bpp <= 8) {<br>- bpp = 8;<br>- pix_width = CRTC_PIX_WIDTH_8BPP;<br>- dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;<br>- dp_chain_mask = 0x8080;<br>- }<br>-#if SUPPORT_8_BPP_ABOVE==1<br>- else if (bpp <= 16) {<br>- bpp = 16;<br>- pix_width = CRTC_PIX_WIDTH_15BPP;<br>- dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |<br>- BYTE_ORDER_LSB_TO_MSB;<br>- dp_chain_mask = 0x4210;<br>- } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {<br>- bpp = 24;<br>- pix_width = CRTC_PIX_WIDTH_24BPP;<br>- dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;<br>- dp_chain_mask = 0x8080;<br>- } else if (bpp <= 32) {<br>- bpp = 32;<br>- pix_width = CRTC_PIX_WIDTH_32BPP;<br>- dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |<br>- BYTE_ORDER_LSB_TO_MSB;<br>- dp_chain_mask = 0x8080;<br>- }<br>-#endif<br>-else<br>- FAIL("invalid bpp");<br>-<br>- if (vxres*vyres*bpp/8 > info->total_vram)<br>- FAIL("not enough video RAM");<br>- if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)<br>- FAIL("invalid vmode");<br>-<br>- /* output */<br>- crtc->vxres = vxres;<br>- crtc->vyres = vyres;<br>- crtc->xoffset = xoffset;<br>- crtc->yoffset = yoffset;<br>- crtc->bpp = bpp;<br>- crtc->h_tot_disp = h_total | (h_disp<<16);<br>- crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |<br>- ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) |<br>- (h_sync_pol<<21);<br>- crtc->v_tot_disp = v_total | (v_disp<<16);<br>- crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);<br>- crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);<br>- crtc->gen_cntl = pix_width | c_sync | CRTC_EXT_DISP_EN | CRTC_ENABLE;<br>- if (M64_HAS(MAGIC_FIFO)) {<br>- /* Not VTB/GTB */<br>- /* FIXME: magic FIFO values */<br>- crtc->gen_cntl |= aty_ld_le32(CRTC_GEN_CNTL, info) & 0x000e0000;<br>- }<br>- crtc->dp_pix_width = dp_pix_width;<br>- crtc->dp_chain_mask = dp_chain_mask;<br>-<br>- return 0;<br>-}<br>-#if PLL_CRTC_DECODE==1<br>-static int aty_crtc_to_var(const struct crtc *crtc,<br>- struct fb_var_screeninfo *var)<br>-{<br>- u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;<br>- u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;<br>- u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;<br>- u32 pix_width;<br>-<br>- /* input */<br>- h_total = crtc->h_tot_disp & 0x1ff;<br>- h_disp = (crtc->h_tot_disp>>16) & 0xff;<br>- h_sync_strt = (crtc->h_sync_strt_wid & 0xff) |<br>- ((crtc->h_sync_strt_wid>>4) & 0x100);<br>- h_sync_dly = (crtc->h_sync_strt_wid>>8) & 0x7;<br>- h_sync_wid = (crtc->h_sync_strt_wid>>16) & 0x1f;<br>- h_sync_pol = (crtc->h_sync_strt_wid>>21) & 0x1;<br>- v_total = crtc->v_tot_disp & 0x7ff;<br>- v_disp = (crtc->v_tot_disp>>16) & 0x7ff;<br>- v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;<br>- v_sync_wid = (crtc->v_sync_strt_wid>>16) & 0x1f;<br>- v_sync_pol = (crtc->v_sync_strt_wid>>21) & 0x1;<br>- c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;<br>- pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;<br>-<br>- /* convert */<br>- xres = (h_disp+1)*8;<br>- yres = v_disp+1;<br>- left = (h_total-h_sync_strt-h_sync_wid)*8-h_sync_dly;<br>- right = (h_sync_strt-h_disp)*8+h_sync_dly;<br>- hslen = h_sync_wid*8;<br>- upper = v_total-v_sync_strt-v_sync_wid;<br>- lower = v_sync_strt-v_disp;<br>- vslen = v_sync_wid;<br>- sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |<br>- (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |<br>- (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);<br>-<br>- switch (pix_width) {<br>-#if 0<br>- case CRTC_PIX_WIDTH_4BPP:<br>- bpp = 4;<br>- var->red.offset = 0;<br>- var->red.length = 8;<br>- var->green.offset = 0;<br>- var->green.length = 8;<br>- var->blue.offset = 0;<br>- var->blue.length = 8;<br>- var->transp.offset = 0;<br>- var->transp.length = 0;<br>- break;<br>-#endif<br>- case CRTC_PIX_WIDTH_8BPP:<br>- bpp = 8;<br>- var->red.offset = 0;<br>- var->red.length = 8;<br>- var->green.offset = 0;<br>- var->green.length = 8;<br>- var->blue.offset = 0;<br>- var->blue.length = 8;<br>- var->transp.offset = 0;<br>- var->transp.length = 0;<br>- break;<br>-#if SUPPORT_8_BPP_ABOVE==1<br>- case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */<br>- bpp = 16;<br>- var->red.offset = 10;<br>- var->red.length = 5;<br>- var->green.offset = 5;<br>- var->green.length = 5;<br>- var->blue.offset = 0;<br>- var->blue.length = 5;<br>- var->transp.offset = 0;<br>- var->transp.length = 0;<br>- break;<br>- case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */<br>- bpp = 16;<br>- var->red.offset = 11;<br>- var->red.length = 5;<br>- var->green.offset = 5;<br>- var->green.length = 6;<br>- var->blue.offset = 0;<br>- var->blue.length = 5;<br>- var->transp.offset = 0;<br>- var->transp.length = 0;<br>- break;<br>- case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */<br>- bpp = 24;<br>- var->red.offset = 16;<br>- var->red.length = 8;<br>- var->green.offset = 8;<br>- var->green.length = 8;<br>- var->blue.offset = 0;<br>- var->blue.length = 8;<br>- var->transp.offset = 0;<br>- var->transp.length = 0;<br>- break;<br>- case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */<br>- bpp = 32;<br>- var->red.offset = 16;<br>- var->red.length = 8;<br>- var->green.offset = 8;<br>- var->green.length = 8;<br>- var->blue.offset = 0;<br>- var->blue.length = 8;<br>- var->transp.offset = 24;<br>- var->transp.length = 8;<br>- break;<br>-#endif<br>- default:<br>- FAIL("Invalid pixel width");<br>- }<br>-<br>- /* output */<br>- var->xres = xres;<br>- var->yres = yres;<br>- var->xres_virtual = crtc->vxres;<br>- var->yres_virtual = crtc->vyres;<br>- var->bits_per_pixel = bpp;<br>- var->xoffset = crtc->xoffset;<br>- var->yoffset = crtc->yoffset;<br>- var->left_margin = left;<br>- var->right_margin = right;<br>- var->upper_margin = upper;<br>- var->lower_margin = lower;<br>- var->hsync_len = hslen;<br>- var->vsync_len = vslen;<br>- var->sync = sync;<br>- var->vmode = FB_VMODE_NONINTERLACED;<br>-<br>- return 0;<br>-}<br>-#endif<br>-<br>-#if 0<br>-static int encode_fix(struct fb_fix_screeninfo *fix,<br>- const struct atyfb_par *par,<br>- const struct fb_info_aty *info)<br>-{<br>- memset(fix, 0, sizeof(struct fb_fix_screeninfo));<br>-<br>- // strcpy(fix->id, atyfb_name);<br>- memcpy(fix->id, "atyfb", 5);<br>- fix->smem_start = info->frame_buffer;<br>- fix->smem_len = (u32)info->total_vram;<br>-<br>- /*<br>- * Reg Block 0 (CT-compatible block) is at ati_regbase_phys<br>- * Reg Block 1 (multimedia extensions) is at ati_regbase_phys-0x400<br>- */<br>- if (M64_HAS(GX)) {<br>- fix->mmio_start = info->ati_regbase;<br>- fix->mmio_len = 0x400;<br>- fix->accel = FB_ACCEL_ATI_MACH64GX;<br>- } else if (M64_HAS(CT)) {<br>- fix->mmio_start = info->ati_regbase;<br>- fix->mmio_len = 0x400;<br>- fix->accel = FB_ACCEL_ATI_MACH64CT;<br>- } else if (M64_HAS(VT)) {<br>- fix->mmio_start = info->ati_regbase-0x400;<br>- fix->mmio_len = 0x800;<br>- fix->accel = FB_ACCEL_ATI_MACH64VT;<br>- } else /* if (M64_HAS(GT)) */ {<br>- fix->mmio_start = info->ati_regbase-0x400;<br>- fix->mmio_len = 0x800;<br>- fix->accel = FB_ACCEL_ATI_MACH64GT;<br>- }<br>- fix->type = FB_TYPE_PACKED_PIXELS;<br>- fix->type_aux = 0;<br>- fix->line_length = par->crtc.vxres*par->crtc.bpp/8;<br>- fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR<br>- : FB_VISUAL_DIRECTCOLOR;<br>- fix->ywrapstep = 0;<br>- fix->xpanstep = 8;<br>- fix->ypanstep = 1;<br>-<br>- return 0;<br>-}<br>-#endif<br>- /*<br>- * Set the User Defined Part of the Display<br>- */<br>-#if PLL_CRTC_DECODE==1<br>-static int atyfb_set_var(struct fb_var_screeninfo *var, int con,<br>- struct fb_info *fb)<br>-{<br>- struct fb_info_aty *info = (struct fb_info_aty *)fb;<br>- struct atyfb_par par;<br>-#if 0<br>- struct display *display;<br>- int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel, accel;<br>-#endif<br>- int err;<br>- int activate = var->activate;<br>-<br>-#if 0<br>- if (con >= 0)<br>- display = &fb_display[con];<br>- else<br>-#endif<br>-#if 0<br>- display = fb->disp; /* used during initialization */<br>-#endif<br>-<br>- if ((err = atyfb_decode_var(var, &par, info)))<br>- return err;<br>-<br>- atyfb_encode_var(var, &par, (struct fb_info_aty *)info);<br>-<br>-#if 0<br>- printk(BIOS_INFO, "atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK);<br>-#endif<br>-<br>- if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {<br>-#if 0<br>- oldxres = display->var.xres;<br>- oldyres = display->var.yres;<br>- oldvxres = display->var.xres_virtual;<br>- oldvyres = display->var.yres_virtual;<br>- oldbpp = display->var.bits_per_pixel;<br>- oldaccel = display->var.accel_flags;<br>- display->var = *var;<br>- accel = var->accel_flags & FB_ACCELF_TEXT;<br>- if (oldxres != var->xres || oldyres != var->yres ||<br>- oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||<br>- oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) {<br>- struct fb_fix_screeninfo fix;<br>-<br>- encode_fix(&fix, &par, info);<br>- display->screen_base = (char *)info->frame_buffer;<br>- display->visual = fix.visual;<br>- display->type = fix.type;<br>- display->type_aux = fix.type_aux;<br>- display->ypanstep = fix.ypanstep;<br>- display->ywrapstep = fix.ywrapstep;<br>- display->line_length = fix.line_length;<br>- display->can_soft_blank = 1;<br>- display->inverse = 0;<br>-#if 0<br>- if (accel)<br>- display->scrollmode = (info->bus_type == PCI) ? SCROLL_YNOMOVE : 0;<br>- else<br>-#endif<br>- display->scrollmode = SCROLL_YREDRAW;<br>-#if 0<br>- if (info->fb_info.changevar)<br>- (*info->fb_info.changevar)(con);<br>-#endif<br>- }<br>-#endif<br>-// if (!info->fb_info.display_fg ||<br>-// info->fb_info.display_fg->vc_num == con) {<br>- atyfb_set_par(&par, info);<br>-#if 0<br>- atyfb_set_dispsw(display, info, par.crtc.bpp, accel);<br>-#endif<br>-// }<br>-#if 0<br>- if (oldbpp != var->bits_per_pixel) {<br>- if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))<br>- return err;<br>-#endif<br>- do_install_cmap(con, info);<br>-#if 0<br>- }<br>-#endif<br>- }<br>-<br>- return 0;<br>-}<br>-<br>-#endif<br>-/* ------------------------------------------------------------------------- */<br>-<br>-static void atyfb_set_par(const struct atyfb_par *par,<br>- struct fb_info_aty *info)<br>-{<br>- u32 i;<br>- int accelmode;<br>- u8 tmp;<br>-<br>- accelmode = par->accel_flags; /* hack */<br>-<br>-#if PLL_CRTC_DECODE==1<br>- info->current_par = *par;<br>-#endif<br>-<br>- if (info->blitter_may_be_busy)<br>- wait_for_idle(info);<br>- tmp = aty_ld_8(CRTC_GEN_CNTL + 3, info);<br>- aty_set_crtc(info, &par->crtc);<br>- aty_st_8(CLOCK_CNTL + info->clk_wr_offset, 0, info);<br>- /* better call aty_StrobeClock ?? */<br>- aty_st_8(CLOCK_CNTL + info->clk_wr_offset, CLOCK_STROBE, info);<br>-<br>- //info->dac_ops->set_dac(info, &par->pll, par->crtc.bpp, accelmode);<br>- //info->pll_ops->set_pll(info, &par->pll);<br>- aty_set_pll_ct(info, &par->pll);<br>-<br>-<br>- if (!M64_HAS(INTEGRATED)) {<br>- /* Don't forget MEM_CNTL */<br>- i = aty_ld_le32(MEM_CNTL, info) & 0xf0ffffff;<br>- switch (par->crtc.bpp) {<br>- case 8:<br>- i |= 0x02000000;<br>- break;<br>-#if SUPPORT_8_BPP_ABOVE==1<br>- case 16:<br>- i |= 0x03000000;<br>- break;<br>- case 32:<br>- i |= 0x06000000;<br>- break;<br>-#endif<br>- }<br>- aty_st_le32(MEM_CNTL, i, info);<br>- } else {<br>- i = aty_ld_le32(MEM_CNTL, info) & 0xf00fffff;<br>- if (!M64_HAS(MAGIC_POSTDIV))<br>- i |= info->mem_refresh_rate << 20;<br>- switch (par->crtc.bpp) {<br>- case 8:<br>-#if SUPPORT_8_BPP_ABOVE==1<br>- case 24:<br>-#endif<br>- i |= 0x00000000;<br>- break;<br>-#if SUPPORT_8_BPP_ABOVE==1<br>- case 16:<br>- i |= 0x04000000;<br>- break;<br>- case 32:<br>- i |= 0x08000000;<br>- break;<br>-#endif<br>- }<br>- if (M64_HAS(CT_BUS)) {<br>- aty_st_le32(DAC_CNTL, 0x87010184, info);<br>- aty_st_le32(BUS_CNTL, 0x680000f9, info);<br>- } else if (M64_HAS(VT_BUS)) {<br>- aty_st_le32(DAC_CNTL, 0x87010184, info);<br>- aty_st_le32(BUS_CNTL, 0x680000f9, info);<br>- } else if (M64_HAS(MOBIL_BUS)) {<br>- aty_st_le32(DAC_CNTL, 0x80010102, info);<br>- aty_st_le32(BUS_CNTL, 0x7b33a040, info);<br>- } else {<br>- /* GT */<br>- aty_st_le32(DAC_CNTL, 0x86010102, info);<br>- aty_st_le32(BUS_CNTL, 0x7b23a040, info);<br>- aty_st_le32(EXT_MEM_CNTL,<br>- aty_ld_le32(EXT_MEM_CNTL, info) | 0x5000001, info);<br>- }<br>-<br>- aty_st_le32(MEM_CNTL, i, info);<br>- }<br>- aty_st_8(DAC_MASK, 0xff, info);<br>-<br>- /* Initialize the graphics engine */<br>-#if 0<br>- if (par->accel_flags & FB_ACCELF_TEXT)<br>- aty_init_engine(par, info);<br>-#endif<br>-<br>-<br>-}<br>-#if 0<br>-static u16 red2[] = {<br>- 0x0000, 0xaaaa<br>-};<br>-static u16 green2[] = {<br>- 0x0000, 0xaaaa<br>-};<br>-static u16 blue2[] = {<br>- 0x0000, 0xaaaa<br>-};<br>-<br>-static u16 red4[] = {<br>- 0x0000, 0xaaaa, 0x5555, 0xffff<br>-};<br>-static u16 green4[] = {<br>- 0x0000, 0xaaaa, 0x5555, 0xffff<br>-};<br>-static u16 blue4[] = {<br>- 0x0000, 0xaaaa, 0x5555, 0xffff<br>-};<br>-<br>-static u16 red8[] = {<br>- 0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa<br>-};<br>-static u16 green8[] = {<br>- 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa<br>-};<br>-static u16 blue8[] = {<br>- 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa<br>-};<br>-#endif<br>-static u16 red16[] = {<br>- 0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,<br>- 0x5555, 0x5555, 0x5555, 0x5555, 0xffff, 0xffff, 0xffff, 0xffff<br>-};<br>-static u16 green16[] = {<br>- 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa,<br>- 0x5555, 0x5555, 0xffff, 0xffff, 0x5555, 0x5555, 0xffff, 0xffff<br>-};<br>-static u16 blue16[] = {<br>- 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa,<br>- 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff<br>-};<br>-#if 0<br>-static struct fb_cmap default_2_colors = {<br>- 0, 2, red2, green2, blue2, NULL<br>-};<br>-static struct fb_cmap default_8_colors = {<br>- 0, 8, red8, green8, blue8, NULL<br>-};<br>-static struct fb_cmap default_4_colors = {<br>- 0, 4, red4, green4, blue4, NULL<br>-};<br>-#endif<br>-static struct fb_cmap default_16_colors = {<br>- 0, 16, red16, green16, blue16, NULL<br>-};<br>-<br>-<br>-<br>-static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,<br>- u_int transp, struct fb_info_aty *info)<br>-{<br>- int i, scale;<br>-<br>- if (regno > 255)<br>- return 1;<br>- red >>= 8;<br>- green >>= 8;<br>- blue >>= 8;<br>-#if 0<br>-//We don't need to store it<br>- info->palette[regno].red = red;<br>- info->palette[regno].green = green;<br>- info->palette[regno].blue = blue;<br>-#endif<br>- i = aty_ld_8(DAC_CNTL, info) & 0xfc;<br>- if (M64_HAS(EXTRA_BRIGHT))<br>- i |= 0x2; /*DAC_CNTL|0x2 turns off the extra brightness for gt*/<br>- aty_st_8(DAC_CNTL, i, info);<br>- aty_st_8(DAC_MASK, 0xff, info);<br>-#if PLL_CRTC_DECODE==1<br>- scale = (M64_HAS(INTEGRATED) && info->current_par.crtc.bpp == 16) ? 3 : 0;<br>-#else<br>- scale = (M64_HAS(INTEGRATED) && info->default_par.crtc.bpp == 16) ? 3 : 0;<br>-#endif<br>- write8(&info->aty_cmap_regs->windex, regno << scale)<br>- write8(&info->aty_cmap_regs->lut, red);<br>- write8(&info->aty_cmap_regs->lut, green);<br>- write8(&info->aty_cmap_regs->lut, blue);<br>- return 0;<br>-}<br>-<br>-int fb_set_cmap(struct fb_cmap *cmap, int kspc,<br>- int (*setcolreg)(u_int, u_int, u_int, u_int, u_int,<br>- struct fb_info_aty *),<br>- struct fb_info_aty *info)<br>-{<br>- int i, start;<br>- u16 *red, *green, *blue, *transp;<br>- u_int hred, hgreen, hblue, htransp;<br>-<br>- red = cmap->red;<br>- green = cmap->green;<br>- blue = cmap->blue;<br>- transp = cmap->transp;<br>- start = cmap->start;<br>-<br>- if (start < 0)<br>- return -EINVAL;<br>- for (i = 0; i < cmap->len; i++) {<br>- hred = *red;<br>- hgreen = *green;<br>- hblue = *blue;<br>- htransp = transp ? *transp : 0;<br>- red++;<br>- green++;<br>- blue++;<br>- if (transp)<br>- transp++;<br>- if (setcolreg(start++, hred, hgreen, hblue, htransp, info))<br>- return 0;<br>- }<br>- return 0;<br>-}<br>-<br>-struct fb_cmap *fb_default_cmap(int len)<br>-{<br>-#if 0<br>- if (len <= 2)<br>- return &default_2_colors;<br>- if (len <= 4)<br>- return &default_4_colors;<br>- if (len <= 8)<br>- return &default_8_colors;<br>-#endif<br>- return &default_16_colors;<br>-}<br>-<br>-static void do_install_cmap(int con, struct fb_info_aty *info)<br>-{<br>-#if PLL_CRTC_DECODE==1<br>- int size = info->current_par.crtc.bpp == 16 ? 32 : 256;<br>-#else<br>- int size = 256;<br>-#endif<br>- fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info);<br>-}<br>-<br>-#endif /*CONFIG_CONSOLE_BTEXT */<br>-<br>-static struct device_operations ati_ragexl_graph_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = ati_ragexl_init,<br>- .scan_bus = 0,<br>-};<br>-<br>-static const struct pci_driver ati_ragexl_graph_driver __pci_driver = {<br>- .ops = &ati_ragexl_graph_ops,<br>- .vendor = PCI_VENDOR_ID_ATI,<br>- .device = PCI_DEVICE_ID_ATI_215XL,<br>-};<br></pre><p>To view, visit <a href="https://review.coreboot.org/22132">change 22132</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22132"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8a5308b6c7773d791d47832e620558394f1d727e </div>
<div style="display:none"> Gerrit-Change-Number: 22132 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>