<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22115">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/stoneyridge: Remove _PRW ASL<br><br>Remove _PRW GPE settings from GPP and USB ASL. The mainboard sets<br>the GPEs.<br><br>In addition, Stoney Ridge GPPs don't generate a GPE/SCIs.<br><br>Change-Id: Ib6a07a997bc3508109a67867014210091efc0c99<br>Signed-off-by: Marc Jones <marcj303@gmail.com><br>---<br>M src/soc/amd/stoneyridge/acpi/northbridge.asl<br>M src/soc/amd/stoneyridge/acpi/usb.asl<br>2 files changed, 0 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/22115/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl<br>index 9cc8ff0..4df6567 100644<br>--- a/src/soc/amd/stoneyridge/acpi/northbridge.asl<br>+++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl<br>@@ -49,7 +49,6 @@<br> /* Gpp 0 */<br> Device(PBR4) {<br>     Name(_ADR, 0x00020001)<br>-       Name(_PRW, Package() {0x18, 4})<br>       Method(_PRT,0) {<br>              If(PMOD){ Return(APS4) }        /* APIC mode */<br>               Return (PS4)                    /* PIC Mode */<br>@@ -59,7 +58,6 @@<br> /* Gpp 1 */<br> Device(PBR5) {<br>      Name(_ADR, 0x00020002)<br>-       Name(_PRW, Package() {0x18, 4})<br>       Method(_PRT,0) {<br>              If(PMOD){ Return(APS5) }        /* APIC mode */<br>               Return (PS5)                    /* PIC Mode */<br>@@ -69,7 +67,6 @@<br> /* Gpp 2 */<br> Device(PBR6) {<br>      Name(_ADR, 0x00020003)<br>-       Name(_PRW, Package() {0x18, 4})<br>       Method(_PRT,0) {<br>              If(PMOD){ Return(APS6) }        /* APIC mode */<br>               Return (PS6)                    /* PIC Mode */<br>@@ -79,7 +76,6 @@<br> /* Gpp 3 */<br> Device(PBR7) {<br>      Name(_ADR, 0x00020004)<br>-       Name(_PRW, Package() {0x18, 4})<br>       Method(_PRT,0) {<br>              If(PMOD){ Return(APS7) }        /* APIC mode */<br>               Return (PS7)                    /* PIC Mode */<br>@@ -89,7 +85,6 @@<br> /* Gpp 4 */<br> Device(PBR8) {<br>      Name(_ADR, 0x00020005)<br>-       Name(_PRW, Package() {0x18, 4})<br>       Method(_PRT,0) {<br>              If(PMOD){ Return(APS8) }        /* APIC mode */<br>               Return (PS8)                    /* PIC Mode */<br>diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl<br>index b93555a..3fd76b2 100644<br>--- a/src/soc/amd/stoneyridge/acpi/usb.asl<br>+++ b/src/soc/amd/stoneyridge/acpi/usb.asl<br>@@ -17,12 +17,10 @@<br> /* 0:12.0 - EHCI */<br> Device(EHC0) {<br>   Name(_ADR, 0x00120000)<br>-       Name(_PRW, Package() {0x0b, 3})<br> } /* end EHC0 */<br> <br> <br> /* 0:10.0 - XHCI 0*/<br> Device(XHC0) {<br>      Name(_ADR, 0x00100000)<br>-       Name(_PRW, Package() {0x0b, 4})<br> } /* end XHC0 */<br></pre><p>To view, visit <a href="https://review.coreboot.org/22115">change 22115</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22115"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib6a07a997bc3508109a67867014210091efc0c99 </div>
<div style="display:none"> Gerrit-Change-Number: 22115 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>