<p>Philipp Deppenwiese <strong>uploaded patch set #2</strong> to this change.</p><p><a href="https://review.coreboot.org/22103">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">security/tpm: Move tpm TSS and TSPI layer to security section<br><br>* Move code from src/lib and src/include into src/security/tpm<br>* Split TPM TSS 1.2 and 2.0<br>* Fix header includes<br>* Add a new directory structure with kconfig and makefile includes<br><br>Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b<br>Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org><br>---<br>M src/Kconfig<br>M src/cpu/intel/haswell/romstage.c<br>M src/drivers/i2c/tpm/cr50.c<br>M src/drivers/i2c/tpm/tis.c<br>M src/drivers/i2c/tpm/tis_atmel.c<br>M src/drivers/i2c/tpm/tpm.c<br>M src/drivers/intel/fsp1_1/romstage.c<br>M src/drivers/intel/fsp2_0/memory_init.c<br>M src/drivers/pc80/tpm/Kconfig<br>M src/drivers/pc80/tpm/romstage.c<br>M src/drivers/pc80/tpm/tpm.c<br>M src/drivers/spi/tpm/tis.c<br>M src/drivers/spi/tpm/tpm.c<br>M src/lib/Makefile.inc<br>M src/mainboard/asus/kgpe-d16/romstage.c<br>M src/mainboard/google/gru/chromeos.c<br>M src/mainboard/google/link/romstage.c<br>M src/mainboard/google/oak/tpm_tis.c<br>M src/mainboard/google/parrot/romstage.c<br>M src/mainboard/google/stout/romstage.c<br>M src/mainboard/intel/emeraldlake2/romstage.c<br>M src/mainboard/lenovo/x201/romstage.c<br>M src/mainboard/pcengines/apu2/romstage.c<br>M src/mainboard/samsung/lumpy/romstage.c<br>M src/mainboard/samsung/stumpy/romstage.c<br>M src/northbridge/intel/sandybridge/romstage.c<br>M src/security/Kconfig<br>M src/security/Makefile.inc<br>A src/security/tpm/Kconfig<br>A src/security/tpm/Makefile.inc<br>R src/security/tpm/antirollback.h<br>R src/security/tpm/tcg-1.2/tlcl.c<br>R src/security/tpm/tcg-1.2/tlcl_internal.h<br>R src/security/tpm/tcg-1.2/tlcl_structures.h<br>R src/security/tpm/tcg-2.0/tpm2_marshaling.c<br>R src/security/tpm/tcg-2.0/tpm2_marshaling.h<br>R src/security/tpm/tcg-2.0/tpm2_tlcl.c<br>R src/security/tpm/tcg-2.0/tpm2_tlcl_structures.h<br>R src/security/tpm/tlcl.h<br>R src/security/tpm/tpm.h<br>R src/security/tpm/tpm_error_messages.h<br>R src/security/tpm/tss_constants.h<br>M src/security/vboot/secdata_mock.c<br>M src/security/vboot/secdata_tpm.c<br>M src/security/vboot/vboot_logic.c<br>M src/soc/intel/baytrail/romstage/romstage.c<br>M src/soc/intel/braswell/romstage/romstage.c<br>M src/soc/intel/broadwell/romstage/romstage.c<br>M src/soc/intel/common/tpm_tis.c<br>M src/vendorcode/google/chromeos/cr50_enable_update.c<br>M src/vendorcode/google/chromeos/tpm2.c<br>51 files changed, 126 insertions(+), 107 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/22103/2</pre><p>To view, visit <a href="https://review.coreboot.org/22103">change 22103</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22103"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newpatchset </div>
<div style="display:none"> Gerrit-Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b </div>
<div style="display:none"> Gerrit-Change-Number: 22103 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>