<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22095">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">stoneyridge: Add SCI/GPE configuration<br><br>Add functions for configuring the GPE ACPI SCI events.<br><br>BUG=b:63268311<br>BRANCH=none<br>TEST=With the Kahlee GPE setup patch, test lidswitch powers<br>the device on and off at the login screen.<br><br>Change-Id: I5c282268edbd7b92a3f2ca7c72896406c8f8512f<br>Signed-off-by: Marc Jones <marcj303@gmail.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/smi.h<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/sb_util.c<br>M src/soc/amd/stoneyridge/smi_util.c<br>4 files changed, 102 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/22095/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h<br>index 797f4e8..78f750f 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/smi.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/smi.h<br>@@ -20,7 +20,17 @@<br> <br> #include <arch/io.h><br> <br>+#define SMI_GEVENTS 23<br>+#define SCI_GEVENTS 57<br>+<br>+#define SMI_EVENT_STATUS 0x0<br>+#define SMI_EVENT_ENABLE 0x04<br>+#define SMI_SCI_TRIG 0x08<br>+#define SMI_SCI_LEVEL 0x0c<br> #define SMI_SCI_STATUS 0x10<br>+#define SMI_SCI_EN 0x14<br>+#define SMI_SCI_MAP0 0x40<br>+# define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X))<br> <br> /* SMI source and status */<br> #define SMITYPE_AGPIO65 0<br>@@ -189,9 +199,21 @@<br> SMI_MODE_IRQ13 = 3,<br> };<br> <br>-enum smi_lvl {<br>- SMI_LVL_LOW = 0,<br>- SMI_LVL_HIGH = 1,<br>+enum smi_sci_type {<br>+ NONE = 0,<br>+ SCI = 1,<br>+ SMI = 2,<br>+ BOTH = 3,<br>+};<br>+<br>+enum smi_sci_lvl {<br>+ SMI_SCI_LVL_LOW = 0,<br>+ SMI_SCI_LVL_HIGH = 1,<br>+};<br>+<br>+enum smi_sci_dir {<br>+ SMI_SCI_EDG = 0,<br>+ SMI_SCI_LVL = 1,<br> };<br> <br> struct smi_sources_t {<br>@@ -199,10 +221,19 @@<br> void (*handler)(void);<br> };<br> <br>+struct sci_source_t {<br>+ uint8_t gevent; /* GEVENTS 0-57 */<br>+ uint8_t gpe; /* 32 GPEs */<br>+ uint8_t direction; /* Active High or Low, smi_sci_lvl */<br>+ uint8_t level; /* Edge or Level, smi_sci_dir */<br>+};<br>+<br> uint16_t pm_acpi_smi_cmd_port(void);<br> void configure_smi(uint8_t smi_num, uint8_t mode);<br> void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);<br>+void configure_gevent_sci(const struct sci_source_t * sci);<br> void disable_gevent_smi(uint8_t gevent);<br>+void gpe_configure_sci(const struct sci_source_t * scis, size_t num_gpes);<br> <br> #ifndef __SMM__<br> void enable_smi_generation(void);<br>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>index d506af9..f371af3 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>@@ -198,8 +198,10 @@<br> void pm_write8(u8 reg, u8 value);<br> void pm_write16(u8 reg, u16 value);<br> void pm_write32(u8 reg, u32 value);<br>+u8 smi_read8(u8 reg);<br> u16 smi_read16(u8 reg);<br> u32 smi_read32(u8 reg);<br>+void smi_write8(u8 reg, u8 value);<br> void smi_write16(u8 reg, u16 value);<br> void smi_write32(u8 reg, u32 value);<br> uint16_t pm_acpi_pm_cnt_blk(void);<br>diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c<br>index bdb199a..ebf791d 100644<br>--- a/src/soc/amd/stoneyridge/sb_util.c<br>+++ b/src/soc/amd/stoneyridge/sb_util.c<br>@@ -65,6 +65,16 @@<br> write16((void *)(APU_SMI_BASE + offset), value);<br> }<br> <br>+uint8_t smi_read8(uint8_t offset)<br>+{<br>+ return read8((void *)(APU_SMI_BASE + offset));<br>+}<br>+<br>+void smi_write8(uint8_t offset, uint8_t value)<br>+{<br>+ write8((void *)(APU_SMI_BASE + offset), value);<br>+}<br>+<br> uint16_t pm_acpi_pm_cnt_blk(void)<br> {<br> return pm_read16(PM1_CNT_BLK);<br>diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c<br>index 96e9d61..fc7f3a7 100644<br>--- a/src/soc/amd/stoneyridge/smi_util.c<br>+++ b/src/soc/amd/stoneyridge/smi_util.c<br>@@ -35,13 +35,13 @@<br> * @param gevent The GEVENT pin number. Valid values are 0 thru 23<br> * @param mode The type of event this pin should generate. Note that only<br> * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events.<br>- * @param level SMI_LVL_LOW or SMI_LVL_HIGH<br>+ * @param level SMI__SCI_LVL_LOW or SMI_SCI_LVL_HIGH<br> */<br> void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level)<br> {<br> uint32_t reg32;<br> /* GEVENT pins range from [0:23] */<br>- if (gevent > 23) {<br>+ if (gevent > SMI_GEVENTS) {<br> printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent);<br> return;<br> }<br>@@ -56,6 +56,60 @@<br> smi_write32(SMI_REG_SMITRIG0, reg32);<br> }<br> <br>+/**<br>+ * Configure generation of SCI for given GEVENT pin<br>+ *<br>+ * @param gevent The GEVENT pin number.<br>+ * @param gpe - GPE 0-31 to connect<br>+ * @param direction - Active high or active low<br>+ * @param level - Edge or level trigger<br>+ */<br>+void configure_gevent_sci(const struct sci_source_t * sci)<br>+{<br>+ uint32_t reg32;<br>+<br>+ /* GEVENT pins range */<br>+ if (sci->gevent > SCI_GEVENTS) {<br>+ printk(BIOS_WARNING, "BUG: Invalid SCI GEVENT: %u\n",<br>+ sci->gevent);<br>+ return;<br>+ }<br>+<br>+ /* GPEs range from [0:31] */<br>+ if (sci->gpe > 31) {<br>+ printk(BIOS_WARNING, "BUG: Invalid SCI GPE: %u\n", sci->gpe);<br>+ return;<br>+ }<br>+<br>+ printk(BIOS_DEBUG, "GEvent %d maps to GPE %d (active %s, %s trigger)\n",<br>+ sci->gevent, sci->gpe,<br>+ (!!sci->direction) ? "high" : "low",<br>+ (!!sci->level) ? "level" : "edge");<br>+<br>+ /* Map Gevent to SCI GPE# */<br>+ smi_write8(SMI_SCI_MAP(sci->gevent), sci->gpe);<br>+<br>+ /* Set the trigger direction (high/low) */<br>+ reg32 = smi_read32(SMI_SCI_TRIG);<br>+ reg32 &= ~(1 << sci->gpe);<br>+ reg32 |= !!sci->direction << sci->gpe;<br>+ smi_write32(SMI_SCI_TRIG, reg32);<br>+<br>+ /* Set the trigger level (edge/level) */<br>+ reg32 = smi_read32(SMI_SCI_LEVEL);<br>+ reg32 &= ~(1 << sci->gpe);<br>+ reg32 |= !!sci->level << sci->gpe;<br>+ smi_write32(SMI_SCI_LEVEL, reg32);<br>+}<br>+<br>+void gpe_configure_sci(const struct sci_source_t * scis, size_t num_gpes)<br>+{<br>+ size_t i;<br>+<br>+ for (i = 0; i < num_gpes; i++)<br>+ configure_gevent_sci(scis + i);<br>+}<br>+<br> /** Disable events from given GEVENT pin */<br> void disable_gevent_smi(uint8_t gevent)<br> {<br></pre><p>To view, visit <a href="https://review.coreboot.org/22095">change 22095</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22095"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5c282268edbd7b92a3f2ca7c72896406c8f8512f </div>
<div style="display:none"> Gerrit-Change-Number: 22095 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>