<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22084">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Use PCH_DEV_* instead of PCH_DEVFN_*<br><br>This change allows the same functions to be used across ramstage and<br>smm without having to add checks for what stage is using it.<br><br>BUG=b:67874513<br><br>Change-Id: I3b10c9e8975e8622d8cb0f66d90d39a914ba7e1c<br>Signed-off-by: Furquan Shaikh <furquan@chromium.org><br>---<br>M src/soc/intel/skylake/elog.c<br>1 file changed, 24 insertions(+), 25 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/22084/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c<br>index b2f325b..c015a78 100644<br>--- a/src/soc/intel/skylake/elog.c<br>+++ b/src/soc/intel/skylake/elog.c<br>@@ -170,7 +170,7 @@<br> }<br> <br> struct pme_status_info {<br>-      int devfn;<br>+   device_t dev;<br>         uint8_t reg_offset;<br>   uint32_t elog_event;<br> };<br>@@ -184,7 +184,7 @@<br>         * If wake source is XHCI, check for detailed wake source events on<br>    * USB2/3 ports.<br>       */<br>-  if ((info->devfn == PCH_DEVFN_XHCI) && pch_xhci_update_wake_event(dev))<br>+   if ((info->dev == PCH_DEV_XHCI) && pch_xhci_update_wake_event(dev))<br>                return;<br> <br>    elog_add_event_wake(info->elog_event, 0);<br>@@ -197,18 +197,17 @@<br>   uint16_t val;<br>         bool dev_found = false;<br> <br>-   static const struct pme_status_info pme_status_info[] = {<br>-            { PCH_DEVFN_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA },<br>-           { PCH_DEVFN_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE },<br>-           { PCH_DEVFN_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA },<br>-         { PCH_DEVFN_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE },<br>-           { PCH_DEVFN_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI },<br>-         { PCH_DEVFN_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI },<br>+       struct pme_status_info pme_status_info[] = {<br>+         { PCH_DEV_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA },<br>+             { PCH_DEV_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE },<br>+             { PCH_DEV_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA },<br>+           { PCH_DEV_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE },<br>+             { PCH_DEV_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI },<br>+           { PCH_DEV_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI },<br>  };<br> <br>         for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) {<br>-               dev = dev_find_slot(0, pme_status_info[i].devfn);<br>-<br>+         dev = pme_status_info[i].dev;<br>                 if (!dev)<br>                     continue;<br> <br>@@ -232,23 +231,23 @@<br>   device_t dev;<br>         uint32_t val;<br> <br>-     static const struct pme_status_info pme_status_info[] = {<br>-            { PCH_DEVFN_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 },<br>-               { PCH_DEVFN_PCIE2, 0x60, ELOG_WAKE_SOURCE_PME_PCIE2 },<br>-               { PCH_DEVFN_PCIE3, 0x60, ELOG_WAKE_SOURCE_PME_PCIE3 },<br>-               { PCH_DEVFN_PCIE4, 0x60, ELOG_WAKE_SOURCE_PME_PCIE4 },<br>-               { PCH_DEVFN_PCIE5, 0x60, ELOG_WAKE_SOURCE_PME_PCIE5 },<br>-               { PCH_DEVFN_PCIE6, 0x60, ELOG_WAKE_SOURCE_PME_PCIE6 },<br>-               { PCH_DEVFN_PCIE7, 0x60, ELOG_WAKE_SOURCE_PME_PCIE7 },<br>-               { PCH_DEVFN_PCIE8, 0x60, ELOG_WAKE_SOURCE_PME_PCIE8 },<br>-               { PCH_DEVFN_PCIE9, 0x60, ELOG_WAKE_SOURCE_PME_PCIE9 },<br>-               { PCH_DEVFN_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 },<br>-             { PCH_DEVFN_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 },<br>-             { PCH_DEVFN_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 },<br>+     struct pme_status_info pme_status_info[] = {<br>+         { PCH_DEV_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 },<br>+         { PCH_DEV_PCIE2, 0x60, ELOG_WAKE_SOURCE_PME_PCIE2 },<br>+         { PCH_DEV_PCIE3, 0x60, ELOG_WAKE_SOURCE_PME_PCIE3 },<br>+         { PCH_DEV_PCIE4, 0x60, ELOG_WAKE_SOURCE_PME_PCIE4 },<br>+         { PCH_DEV_PCIE5, 0x60, ELOG_WAKE_SOURCE_PME_PCIE5 },<br>+         { PCH_DEV_PCIE6, 0x60, ELOG_WAKE_SOURCE_PME_PCIE6 },<br>+         { PCH_DEV_PCIE7, 0x60, ELOG_WAKE_SOURCE_PME_PCIE7 },<br>+         { PCH_DEV_PCIE8, 0x60, ELOG_WAKE_SOURCE_PME_PCIE8 },<br>+         { PCH_DEV_PCIE9, 0x60, ELOG_WAKE_SOURCE_PME_PCIE9 },<br>+         { PCH_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 },<br>+               { PCH_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 },<br>+               { PCH_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 },<br>        };<br> <br>         for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) {<br>-               dev = dev_find_slot(0, pme_status_info[i].devfn);<br>+            dev = pme_status_info[i].dev;<br> <br>              if (!dev)<br>                     continue;<br></pre><p>To view, visit <a href="https://review.coreboot.org/22084">change 22084</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22084"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3b10c9e8975e8622d8cb0f66d90d39a914ba7e1c </div>
<div style="display:none"> Gerrit-Change-Number: 22084 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>