<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22085">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Move power_state functions to pmutil.c<br><br>This change moves soc_fill_power_state and soc_prev_sleep_state to<br>pmutil.c. It allows the functions to be used across romstage and smm.<br><br>BUG=b:67874513<br><br>Change-Id: I375ac029520c2cdd52926f3ab3c2d5559936dd8c<br>Signed-off-by: Furquan Shaikh <furquan@chromium.org><br>---<br>M src/soc/intel/skylake/pmutil.c<br>M src/soc/intel/skylake/romstage/power_state.c<br>2 files changed, 59 insertions(+), 60 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/22085/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c<br>index 19370e1..40afce2 100644<br>--- a/src/soc/intel/skylake/pmutil.c<br>+++ b/src/soc/intel/skylake/pmutil.c<br>@@ -247,3 +247,62 @@<br> {<br> return rtc_failure();<br> }<br>+<br>+/* Return 0, 3, or 5 to indicate the previous sleep state. */<br>+int soc_prev_sleep_state(const struct chipset_power_state *ps,<br>+ int prev_sleep_state)<br>+{<br>+ /*<br>+ * Check for any power failure to determine if this a wake from<br>+ * S5 because the PCH does not set the WAK_STS bit when waking<br>+ * from a true G3 state.<br>+ */<br>+ if (!(ps->pm1_sts & WAK_STS) &&<br>+ (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)))<br>+ prev_sleep_state = ACPI_S5;<br>+<br>+ /*<br>+ * If waking from S3 determine if deep S3 is enabled. If not,<br>+ * need to check both deep sleep well and normal suspend well.<br>+ * Otherwise just check deep sleep well.<br>+ */<br>+ if (prev_sleep_state == ACPI_S3) {<br>+ /* PWR_FLR represents deep sleep power well loss. */<br>+ uint32_t mask = PWR_FLR;<br>+<br>+ /* If deep s3 isn't enabled check the suspend well too. */<br>+ if (!deep_s3_enabled())<br>+ mask |= SUS_PWR_FLR;<br>+<br>+ if (ps->gen_pmcon_b & mask)<br>+ prev_sleep_state = ACPI_S5;<br>+ }<br>+ return prev_sleep_state;<br>+}<br>+<br>+void soc_fill_power_state(struct chipset_power_state *ps)<br>+{<br>+ uint16_t tcobase;<br>+ uint8_t *pmc;<br>+<br>+ tcobase = smbus_tco_regs();<br>+<br>+ ps->tco1_sts = inw(tcobase + TCO1_STS);<br>+ ps->tco2_sts = inw(tcobase + TCO2_STS);<br>+<br>+ printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",<br>+ ps->tco1_sts, ps->tco2_sts);<br>+<br>+ ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);<br>+ ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);<br>+<br>+ pmc = pmc_mmio_regs();<br>+ ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);<br>+ ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);<br>+<br>+ printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",<br>+ ps->gen_pmcon_a, ps->gen_pmcon_b);<br>+<br>+ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",<br>+ ps->gblrst_cause[0], ps->gblrst_cause[1]);<br>+}<br>diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c<br>index 3eae936..f11041f 100644<br>--- a/src/soc/intel/skylake/romstage/power_state.c<br>+++ b/src/soc/intel/skylake/romstage/power_state.c<br>@@ -34,66 +34,6 @@<br> #include <vboot/vboot_common.h><br> #include <intelblocks/pmclib.h><br> <br>-/* Return 0, 3, or 5 to indicate the previous sleep state. */<br>-int soc_prev_sleep_state(const struct chipset_power_state *ps,<br>- int prev_sleep_state)<br>-{<br>-<br>- /*<br>- * Check for any power failure to determine if this a wake from<br>- * S5 because the PCH does not set the WAK_STS bit when waking<br>- * from a true G3 state.<br>- */<br>- if (!(ps->pm1_sts & WAK_STS) &&<br>- (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)))<br>- prev_sleep_state = ACPI_S5;<br>-<br>- /*<br>- * If waking from S3 determine if deep S3 is enabled. If not,<br>- * need to check both deep sleep well and normal suspend well.<br>- * Otherwise just check deep sleep well.<br>- */<br>- if (prev_sleep_state == ACPI_S3) {<br>- /* PWR_FLR represents deep sleep power well loss. */<br>- uint32_t mask = PWR_FLR;<br>-<br>- /* If deep s3 isn't enabled check the suspend well too. */<br>- if (!deep_s3_enabled())<br>- mask |= SUS_PWR_FLR;<br>-<br>- if (ps->gen_pmcon_b & mask)<br>- prev_sleep_state = ACPI_S5;<br>- }<br>- return prev_sleep_state;<br>-}<br>-<br>-void soc_fill_power_state(struct chipset_power_state *ps)<br>-{<br>- uint16_t tcobase;<br>- uint8_t *pmc;<br>-<br>- tcobase = smbus_tco_regs();<br>-<br>- ps->tco1_sts = inw(tcobase + TCO1_STS);<br>- ps->tco2_sts = inw(tcobase + TCO2_STS);<br>-<br>- printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",<br>- ps->tco1_sts, ps->tco2_sts);<br>-<br>- ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);<br>- ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);<br>-<br>- pmc = pmc_mmio_regs();<br>- ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);<br>- ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);<br>-<br>- printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",<br>- ps->gen_pmcon_a, ps->gen_pmcon_b);<br>-<br>- printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",<br>- ps->gblrst_cause[0], ps->gblrst_cause[1]);<br>-}<br>-<br> int acpi_get_sleep_type(void)<br> {<br> struct chipset_power_state *ps;<br></pre><p>To view, visit <a href="https://review.coreboot.org/22085">change 22085</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22085"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I375ac029520c2cdd52926f3ab3c2d5559936dd8c </div>
<div style="display:none"> Gerrit-Change-Number: 22085 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>