<p>Werner Zeh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22035">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_bdx1: Initialize GPIOs<br><br>Add GPIO initialization for mc_bdx1 mainboard.<br>To avoid that the GPIOs will be set up twice call the init_gpios()<br>function in the late romstage phase.<br><br>Change-Id: I003277cfb871f861900b7fcdc5ec851d4c1c1e6a<br>Signed-off-by: Werner Zeh <werner.zeh@siemens.com><br>---<br>A src/mainboard/siemens/mc_bdx1/gpio.h<br>M src/mainboard/siemens/mc_bdx1/romstage.c<br>2 files changed, 96 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/22035/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/siemens/mc_bdx1/gpio.h b/src/mainboard/siemens/mc_bdx1/gpio.h<br>new file mode 100644<br>index 0000000..5b5555d<br>--- /dev/null<br>+++ b/src/mainboard/siemens/mc_bdx1/gpio.h<br>@@ -0,0 +1,92 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Siemens AG<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the<br>+ * GNU General Public License for more details.<br>+ */<br>+#ifndef MC_BDX1_GPIO_H_<br>+#define MC_BDX1_GPIO_H_<br>+<br>+#include <soc/gpio.h><br>+<br>+static const struct gpio_config mc_bdx1_gpio_config[] = {<br>+              PCH_GPIO_OUT_LOW(0),<br>+         PCH_GPIO_OUT_LOW(1),<br>+         PCH_GPIO_INPUT(2),<br>+           PCH_GPIO_INPUT(3),<br>+           PCH_GPIO_INPUT(4),<br>+           PCH_GPIO_INPUT(5),<br>+           PCH_GPIO_OUT_LOW(6),<br>+         PCH_GPIO_INPUT_INVERT(7),<br>+            PCH_GPIO_OUT_LOW(8),<br>+         PCH_GPIO_NATIVE(9),<br>+          PCH_GPIO_NATIVE(10),<br>+         PCH_GPIO_NATIVE(11),<br>+         PCH_GPIO_INPUT(12),<br>+          PCH_GPIO_NATIVE(14),<br>+         PCH_GPIO_INPUT_INVERT(15),<br>+           PCH_GPIO_OUT_LOW(16),<br>+                PCH_GPIO_NATIVE(17),<br>+         PCH_GPIO_OUT_HIGH(18),<br>+               PCH_GPIO_NATIVE(19),<br>+         PCH_GPIO_NATIVE(20),<br>+         PCH_GPIO_NATIVE(21),<br>+         PCH_GPIO_NATIVE(22),<br>+         PCH_GPIO_NATIVE(23),<br>+         PCH_GPIO_INPUT(24),<br>+          PCH_GPIO_OUT_HIGH(25),<br>+               PCH_GPIO_NATIVE(26),<br>+         PCH_GPIO_INPUT(27),<br>+          PCH_GPIO_OUT_HIGH(28),<br>+               PCH_GPIO_OUT_HIGH(29),<br>+               PCH_GPIO_NATIVE(30),<br>+         PCH_GPIO_INPUT(31),<br>+          PCH_GPIO_NATIVE(32),<br>+         PCH_GPIO_NATIVE(33),<br>+         PCH_GPIO_OUT_HIGH(35),<br>+               PCH_GPIO_NATIVE(36),<br>+         PCH_GPIO_NATIVE(37),<br>+         PCH_GPIO_NATIVE(38),<br>+         PCH_GPIO_NATIVE(39),<br>+         PCH_GPIO_INPUT(40),<br>+          PCH_GPIO_INPUT(41),<br>+          PCH_GPIO_INPUT(42),<br>+          PCH_GPIO_NATIVE(43),<br>+         PCH_GPIO_NATIVE(44),<br>+         PCH_GPIO_NATIVE(45),<br>+         PCH_GPIO_NATIVE(46),<br>+         PCH_GPIO_NATIVE(48),<br>+         PCH_GPIO_INPUT(49),<br>+          PCH_GPIO_NATIVE(50),<br>+         PCH_GPIO_NATIVE(51),<br>+         PCH_GPIO_NATIVE(52),<br>+         PCH_GPIO_NATIVE(53),<br>+         PCH_GPIO_NATIVE(54),<br>+         PCH_GPIO_NATIVE(55),<br>+         PCH_GPIO_NATIVE(57),<br>+         PCH_GPIO_NATIVE(58),<br>+         PCH_GPIO_NATIVE(59),<br>+         PCH_GPIO_NATIVE(60),<br>+         PCH_GPIO_NATIVE(61),<br>+         PCH_GPIO_NATIVE(62),<br>+         PCH_GPIO_NATIVE(65),<br>+         PCH_GPIO_OUT_LOW(67),<br>+                PCH_GPIO_NATIVE(68),<br>+         PCH_GPIO_NATIVE(69),<br>+         PCH_GPIO_NATIVE(70),<br>+         PCH_GPIO_NATIVE(71),<br>+         PCH_GPIO_INPUT(72),<br>+          PCH_GPIO_NATIVE(74),<br>+         PCH_GPIO_NATIVE(75),<br>+         PCH_GPIO_END<br>+};<br>+<br>+#endif /* MC_BDX1_GPIO_H_ */<br>diff --git a/src/mainboard/siemens/mc_bdx1/romstage.c b/src/mainboard/siemens/mc_bdx1/romstage.c<br>index cf52c01..f0123b9 100644<br>--- a/src/mainboard/siemens/mc_bdx1/romstage.c<br>+++ b/src/mainboard/siemens/mc_bdx1/romstage.c<br>@@ -3,6 +3,7 @@<br>  *<br>  * Copyright (C) 2013 Google Inc.<br>  * Copyright (C) 2015 Intel Corp.<br>+ * Copyright (C) 2017 Siemens AG<br>  *<br>  * This program is free software; you can redistribute it and/or modify<br>  * it under the terms of the GNU General Public License as published by<br>@@ -17,6 +18,8 @@<br> #include <stddef.h><br> #include <soc/romstage.h><br> #include <drivers/intel/fsp1_0/fsp_util.h><br>+#include <soc/gpio.h><br>+#include "gpio.h"<br> <br> /**<br>  * /brief mainboard call for setup that needs to be done before fsp init<br>@@ -33,7 +36,7 @@<br>  */<br> void late_mainboard_romstage_entry(void)<br> {<br>-<br>+        init_gpios(mc_bdx1_gpio_config);<br> }<br> <br> /**<br></pre><p>To view, visit <a href="https://review.coreboot.org/22035">change 22035</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22035"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I003277cfb871f861900b7fcdc5ec851d4c1c1e6a </div>
<div style="display:none"> Gerrit-Change-Number: 22035 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Werner Zeh <werner.zeh@siemens.com> </div>