<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22052">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/fsp: Update cannonlake FSP header<br><br>Update cannonlake FSP header file to revision 7.x.15.46. The update<br>detail of FSP can be found<br>https://github.com/otcshare/CCG-CNLCFL-SiCReleaseNote/tree/master/WW41<br><br>Change-Id: I065edbeffdaf555ea7d54ec3fdce56d026789c52<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>2 files changed, 23 insertions(+), 1,627 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/22052/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>index fe9933f..dded50d 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>@@ -2248,9 +2248,15 @@<br> **/<br> UINT8 RMTLoopCount;<br> <br>-/** Offset 0x0511<br>+/** Offset 0x0511 - BER Support<br>+ Enable/Disable the Rank Margin Tool interpolation/extrapolation.<br>+ 0:Disable, 1:Enable<br> **/<br>- UINT8 ReservedFspmUpd[15];<br>+ UINT8 EnBER;<br>+<br>+/** Offset 0x0512<br>+**/<br>+ UINT8 ReservedFspmUpd[14];<br> } FSP_M_CONFIG;<br> <br> /** Fsp M Test Configuration<br>@@ -2619,709 +2625,6 @@<br> UINT8 ReservedFspmTestUpd[11];<br> } FSP_M_TEST_CONFIG;<br> <br>-/** Fsp M Restricted Configuration<br>-**/<br>-typedef struct {<br>-<br>-/** Offset 0x05B0<br>-**/<br>- UINT32 Signature;<br>-<br>-/** Offset 0x05B4 - Sa Sv Remap Base Override<br>- SvRemapBaseOverride<br>-**/<br>- UINT16 SaSvRemapBaseOverride;<br>-<br>-/** Offset 0x05B6 - Sa System Agent ClockGating Enable<br>- SystemAgentClockGatingEnable<br>-**/<br>- UINT8 SaSystemAgentClockGatingEnable;<br>-<br>-/** Offset 0x05B7 - Sa Pcie Pll Shutdown Enable<br>- PciePllShutdownEnable<br>-**/<br>- UINT8 SaPciePllShutdownEnable;<br>-<br>-/** Offset 0x05B8 - Sa SV_DMI_GEN1_halt<br>- SV_DMI_GEN1_halt<br>-**/<br>- UINT8 SaSV_DMI_GEN1_halt;<br>-<br>-/** Offset 0x05B9 - Sa SV_nFTS_DMI_auto<br>- SV_nFTS_DMI_auto<br>-**/<br>- UINT8 SaSV_nFTS_DMI_auto;<br>-<br>-/** Offset 0x05BA - Sa Sv DMI_nFTS<br>- SvDMI_nFTS<br>-**/<br>- UINT8 SaSvDMI_nFTS;<br>-<br>-/** Offset 0x05BB - Sa nFTS_auto<br>- nFTS_auto<br>-**/<br>- UINT8 SanFTS_auto;<br>-<br>-/** Offset 0x05BC - Sa SvPEG_nFTS<br>- SvPEG_nFTS<br>-**/<br>- UINT8 SaSvPEG_nFTS[4];<br>-<br>-/** Offset 0x05C0 - Sa SvPEG_gen3_ccFTS<br>- SvPEG_gen3_ccFTS<br>-**/<br>- UINT8 SaSvPEG_gen3_ccFTS[4];<br>-<br>-/** Offset 0x05C4 - Sa SvPEG_gen3_nccFTS<br>- SvPEG_gen3_nccFTS<br>-**/<br>- UINT8 SaSvPEG_gen3_nccFTS[4];<br>-<br>-/** Offset 0x05C8 - Sa nFTS_gen3_auto<br>- nFTS_gen3_auto<br>-**/<br>- UINT8 SanFTS_gen3_auto;<br>-<br>-/** Offset 0x05C9 - Sa SVIAER<br>- SVIAER<br>-**/<br>- UINT8 SaSVIAER;<br>-<br>-/** Offset 0x05CA - Sa Sv Scrambler Dmi<br>- SvScramblerDmi<br>-**/<br>- UINT8 SaSvScramblerDmi;<br>-<br>-/** Offset 0x05CB<br>-**/<br>- UINT8 UnusedUpdSpace9[1];<br>-<br>-/** Offset 0x05CC - Sa Sv Scrambler Peg<br>- SvScramblerPeg<br>-**/<br>- UINT8 SaSvScramblerPeg[4];<br>-<br>-/** Offset 0x05D0 - Sa Sv Dmi Serr<br>- SvDmiSerr<br>-**/<br>- UINT8 SaSvDmiSerr;<br>-<br>-/** Offset 0x05D1<br>-**/<br>- UINT8 UnusedUpdSpace10[3];<br>-<br>-/** Offset 0x05D4 - Sa Sv Scrambler Peg Gen3<br>- SvScramblerPegGen3<br>-**/<br>- UINT8 SaSvScramblerPegGen3[4];<br>-<br>-/** Offset 0x05D8 - Sa Sv Peg Serr<br>- SvPegSerr<br>-**/<br>- UINT8 SaSvPegSerr[4];<br>-<br>-/** Offset 0x05DC - Sa Test Tx ClkGating<br>- TestTxClkGating<br>-**/<br>- UINT8 SaTestTxClkGating;<br>-<br>-/** Offset 0x05DD - Sa Test Rx ClkGating<br>- TestRxClkGating<br>-**/<br>- UINT8 SaTestRxClkGating;<br>-<br>-/** Offset 0x05DE - Sa Test Low Pwr Mode<br>- TestLowPwrMode<br>-**/<br>- UINT8 SaTestLowPwrMode;<br>-<br>-/** Offset 0x05DF - Sa Sr Mode<br>- SrMode<br>-**/<br>- UINT8 SaSrMode;<br>-<br>-/** Offset 0x05E0 - Sa Sr Seq<br>- SrSeq<br>-**/<br>- UINT8 SaSrSeq;<br>-<br>-/** Offset 0x05E1 - Sa Burst Spacing<br>- BurstSpacing<br>-**/<br>- UINT8 SaBurstSpacing;<br>-<br>-/** Offset 0x05E2 - SvPolicyEnable<br>- Enable: SV policy is enabled, Disable(Default): SV policy is disabled<br>- $EN_DIS<br>-**/<br>- UINT8 SaRestrictedSvPolicyEnable;<br>-<br>-/** Offset 0x05E3 - Cpu Sv Boot Mode<br>- 0: Auto (Default), 1: Commercial boot mode, 2: SV boot mode, 3: SV boot JTAG mode<br>- with SB loop, 4: SV boot JTAG mode without SB loop<br>- 0: Auto , 1: Commercial boot mode, 2: SV boot mode, 3: SV boot JTAG mode with SB<br>- loop, 4: SV boot JTAG mode without SB loop<br>-**/<br>- UINT8 SaCpuSvBootMode;<br>-<br>-/** Offset 0x05E4 - CpuSvBootMode<br>- Enable: FlexCon is enabled, Disble(Default): FlexCon is disabled<br>- $EN_DIS<br>-**/<br>- UINT8 XmlCliEnable;<br>-<br>-/** Offset 0x05E5 - LoadValidationFv<br>- Enable: Enable loading of ValidationFV, Disable(Default)<br>- $EN_DIS<br>-**/<br>- UINT8 LoadValidationFv;<br>-<br>-/** Offset 0x05E6 - SvReserveMemoryBelowPrmrr<br>- Enable: Enable reserve SV memory below PMRR, Disable(Default)<br>- $EN_DIS<br>-**/<br>- UINT8 SvReserveMemoryBelowPrmrr;<br>-<br>-/** Offset 0x05E7 - Sa Test Sample Part Status Override<br>- 0-Passthrough, 1-Production part, 2-Preproduction part<br>-**/<br>- UINT8 SaTestSamplePartStatusOverride;<br>-<br>-/** Offset 0x05E8 - Sa Test Grunit ClockGating<br>- Enable Sa Test Grunit ClockGating<br>- $EN_DIS<br>-**/<br>- UINT8 SaTestGrunitClockGating;<br>-<br>-/** Offset 0x05E9 - Sa Test Dmi Cap Reg Lock<br>- DMI Capability Register Lock<br>-**/<br>- UINT8 SaTestDmiCapRegLock;<br>-<br>-/** Offset 0x05EA - Sa Test Dmi Max Payload Size<br>- DMI Max Payload Size<br>-**/<br>- UINT8 SaTestDmiMaxPayloadSize;<br>-<br>-/** Offset 0x05EB - Sa Pcie VcLim Lock<br>- Lock bit<br>-**/<br>- UINT8 SaPcieVcLimLock;<br>-<br>-/** Offset 0x05EC - Sa Pcie VCm Cmp Lim<br>- VCm Completions override<br>-**/<br>- UINT8 SaPcieVCmCmpLim;<br>-<br>-/** Offset 0x05ED - Sa Pcie VCm PLim<br>- posted VCm Requests override<br>-**/<br>- UINT8 SaPcieVCmPLim;<br>-<br>-/** Offset 0x05EE - Sa Pcie VCm NpLim<br>- non-posted VCm Requests override<br>-**/<br>- UINT8 SaPcieVCmNpLim;<br>-<br>-/** Offset 0x05EF - Sa Laguna Credit WA<br>- Laguna Credit WA<br>-**/<br>- UINT8 SaLagunaCreditWA;<br>-<br>-/** Offset 0x05F0 - Sa Sv Dmi Compliance Deemphasis<br>- SvDmiComplianceDeemphasis<br>-**/<br>- UINT8 SaSvDmiComplianceDeemphasis;<br>-<br>-/** Offset 0x05F1 - Prefetch NonPrefetch Ratio<br>- 0: All prefetch, 1: Seven of Eight Prefetch, 2: Three of Four Prefetch, 3: Half<br>- Prefetch Half Non-Prefetch(Default), 4: Three of Four Non-Prefetch, 5: Seven of<br>- Eight Prefetch, 6: All Non-prefetch<br>- 0: All prefetch, 1: Seven of Eight Prefetch, 2: Three of Four Prefetch, 3: Half<br>- Prefetch Half Non-Prefetch, 4: Three of Four Non-Prefetch, 5: Seven of Eight Prefetch,<br>- 6: All Non-prefetch<br>-**/<br>- UINT8 PrefetchNonPrefetchRatio;<br>-<br>-/** Offset 0x05F2 - SaPreMemRestrictedRsvd<br>- Reserved for SA Pre-Mem Restricted<br>- $EN_DIS<br>-**/<br>- UINT8 SaPreMemRestrictedRsvd[30];<br>-<br>-/** Offset 0x0610 - MSEG Size<br>- MSEG Size. Valid values 0 : 512K , 1 : 1M , 2 : 1.5M , 3 : 2M , 4 : 2.4M , 5 : 3M<br>- 0 : 512K , 1 : 1M , 2 : 1.5M , 3 : 2M , 4 : 2.4M , 5 : 3M<br>-**/<br>- UINT64 MsegSize;<br>-<br>-/** Offset 0x0618 - Force TXT Enable<br>- Force TXT Enable; 0: disable, 1: enable<br>- $EN_DIS<br>-**/<br>- UINT8 ForceTxtEnable;<br>-<br>-/** Offset 0x0619 - SaPreMemRestrictedRsvd<br>- Reserved for SA Pre-Mem Restricted<br>- $EN_DIS<br>-**/<br>- UINT8 CpuPreMemRestrictedRsvd[23];<br>-<br>-/** Offset 0x0630 - Dmi Test Tran Co Over En<br>- Enable/Disable Lane Transmitter Coefficient.<br>-**/<br>- UINT8 PchTestDmiTranCoOverEn[4];<br>-<br>-/** Offset 0x0634 - Dmi Test Tran Co Over Post Cur<br>- Lane Transmitter Post-Cursor Coefficient Override.<br>-**/<br>- UINT8 PchTestDmiTranCoOverPostCur[4];<br>-<br>-/** Offset 0x0638 - Dmi Test Tran Co Over Pre Cur<br>- Lane Transmitter Pre-Cursor Coefficient Override.<br>-**/<br>- UINT8 PchTestDmiTranCoOverPreCur[4];<br>-<br>-/** Offset 0x063C - Dmi Test Up Port Tran Preset<br>- Upstream Port Lane Transmitter Preset.<br>-**/<br>- UINT8 PchTestDmiUpPortTranPreset[4];<br>-<br>-/** Offset 0x0640 - Dmi Test UpPort Tran Preset En<br>- 0: POR setting, 1: force enable, 2: force disable.<br>-**/<br>- UINT8 PchTestDmiUpPortTranPresetEn;<br>-<br>-/** Offset 0x0641 - Dmi Test Rtlepceb<br>- DMI Remote Transmit Link Equalization Preset/Coefficient Evaluation Bypass (RTLEPCEB).<br>-**/<br>- UINT8 PchTestDmiRtlepceb;<br>-<br>-/** Offset 0x0642 - DMI ME UMA Root Space Check<br>- DMI IOSF Root Space attribute check for RS3 for cycles targeting MEUMA.<br>- 0: POR, 1: enable, 2: disable<br>-**/<br>- UINT8 PchTestDmiMeUmaRootSpaceCheck;<br>-<br>-/** Offset 0x0643 - ModPhy Selection Policy<br>- ModPhy Selection for ChipsetInitTable <br>-**/<br>- UINT8 ModPhySelection;<br>-<br>-/** Offset 0x0644 - HECI Communication<br>- Test, 0: POR, 1: enable, 2: disable, Disables HECI communication causing ME to enter<br>- error state.<br>- $EN_DIS<br>-**/<br>- UINT8 HeciCommunication;<br>-<br>-/** Offset 0x0645 - HECI3 Interface Communication<br>- Test, 0: POR, 1: enable, 2: disable, Adds or Removes HECI3 Device from PCI space.<br>- $EN_DIS<br>-**/<br>- UINT8 HeciCommunication3;<br>-<br>-/** Offset 0x0646 - Notification test for Host Reset<br>- Test, 0: POR, 1: enable, 2: disable, Enable test for notification when Host Reset<br>- $EN_DIS<br>-**/<br>- UINT8 HostResetNotification;<br>-<br>-/** Offset 0x0647 - Send Manufacturing Reset And Halt On S3 Resume<br>- Test, 0: POR, 1: enable, 2: disable, Enable sending Manufacturing Reset and Halt<br>- on S3 Resume<br>- $EN_DIS<br>-**/<br>- UINT8 ManufRstAndHaltOnS3Resume;<br>-<br>-/** Offset 0x0648 - Force Unlock AES<br>- 0(Default)=Disable, 1=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 ForceUnlockAes;<br>-<br>-/** Offset 0x0649 - PreMemRestrictedRsvd2<br>- Reserved for Pre-Mem RestrictedReserved<br>- $EN_DIS<br>-**/<br>- UINT8 PreMemRestrictedRsvd2[23];<br>-<br>-/** Offset 0x0660 - Asynchronous ODT<br>- This option configures the Memory Controler Asynchronous ODT control<br>- 0:Enabled, 1:Disabled<br>-**/<br>- UINT8 AsyncOdtDis;<br>-<br>-/** Offset 0x0661 - Power Down Mode<br>- This option controls command bus tristating during idle periods<br>- 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto<br>-**/<br>- UINT8 PowerDownMode;<br>-<br>-/** Offset 0x0662 - Time Measure<br>- Time Measure: 0(Default)=Disable, 1=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 MrcTimeMeasure;<br>-<br>-/** Offset 0x0663 - DLL Weak Lock Support<br>- Enables/Disable DLL Weak Lock Support<br>- $EN_DIS<br>-**/<br>- UINT8 WeaklockEn;<br>-<br>-/** Offset 0x0664 - Fore 1 DPC config<br>- Enables/Disable Fore 1 DPC config<br>- $EN_DIS<br>-**/<br>- UINT8 Force1Dpc;<br>-<br>-/** Offset 0x0665 - Fore Single Rank config<br>- Enables/Disable Fore Single Rank config<br>- $EN_DIS<br>-**/<br>- UINT8 ForceSingleRank;<br>-<br>-/** Offset 0x0666 - SelfRefresh IdleTimer<br>- SelfRefresh IdleTimer, Default is 512<br>-**/<br>- UINT16 SrefCfgIdleTmr;<br>-<br>-/** Offset 0x0668 - Strong Weak Leaker<br>- Strong Weak Leaker value. 7=def<br>-**/<br>- UINT8 StrongWkLeaker;<br>-<br>-/** Offset 0x0669<br>-**/<br>- UINT8 MrcRestrictedRsvd0x0669[1];<br>-<br>-/** Offset 0x066A - Opportunistic Read<br>- Enables/Disable Opportunistic Read (Def= Enable)<br>- $EN_DIS<br>-**/<br>- UINT8 OpportunisticRead;<br>-<br>-/** Offset 0x066B - Stacked Mode<br>- Memory Stacked Mode Support (Def = Disable)<br>- $EN_DIS<br>-**/<br>- UINT8 MemStackMode;<br>-<br>-/** Offset 0x066C - Stacked Mode Ch Bit<br>- Channel hash bit used during Stacked Mode(Def= BIT28)<br>- 0:BIT28, 1:BIT29, 2:BIT30, 3:BIT31, 4:BIT32, 5:BIT33, 6:BIT34<br>-**/<br>- UINT8 StackModeChBit;<br>-<br>-/** Offset 0x066D - Low Memory Channel<br>- Selecting which Physical Channel is mapped to low memory.<br>- 0:Channel A, 1:Channel B<br>-**/<br>- UINT8 LowMemChannel;<br>-<br>-/** Offset 0x066E - Cycle Bypass Support<br>- Enables/Disable Cycle Bypass Support(Def=Disable)<br>- $EN_DIS<br>-**/<br>- UINT8 Disable2CycleBypass;<br>-<br>-/** Offset 0x066F - MC Register Offset<br>- Apply user offsets to select MC registers(Def=Disable)<br>- $EN_DIS<br>-**/<br>- UINT8 MCREGOFFSET;<br>-<br>-/** Offset 0x0670 - CA Vref Ctl Offset<br>- Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.CAVref<br>- 0:-12,1:-11, 2:-10, 3:-9, 4:-8, 5:-7, 6:-6, 7:-5, 8:-4, 9:-3, 10:-2, 11:-1, 12:0,<br>- 13:+1, 14:+2, 15:+3, 16:+4, 17:+5, 18:+6, 19:+7, 20:+8, 21:+9, 22:+10, 23:+11,<br>- 24:+12, 0xFF:RANDOM<br>-**/<br>- UINT8 CAVrefCtlOffset;<br>-<br>-/** Offset 0x0671 - Ch0 DQ Vref Ctrl Offset<br>- Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch0VrefCtl<br>- 0:-12,1:-11, 2:-10, 3:-9, 4:-8, 5:-7, 6:-6, 7:-5, 8:-4, 9:-3, 10:-2, 11:-1, 12:0,<br>- 13:+1, 14:+2, 15:+3, 16:+4, 17:+5, 18:+6, 19:+7, 20:+8, 21:+9, 22:+10, 23:+11,<br>- 24:+12, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch0VrefCtlOffset;<br>-<br>-/** Offset 0x0672 - Ch1 DQ Vref Ctrl Offset<br>- Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch1VrefCtl<br>- 0:-12,1:-11, 2:-10, 3:-9, 4:-8, 5:-7, 6:-6, 7:-5, 8:-4, 9:-3, 10:-2, 11:-1, 12:0,<br>- 13:+1, 14:+2, 15:+3, 16:+4, 17:+5, 18:+6, 19:+7, 20:+8, 21:+9, 22:+10, 23:+11,<br>- 24:+12, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch1VrefCtlOffset;<br>-<br>-/** Offset 0x0673 - Ch0 Clk PI Code Offset<br>- Offset to be applied to DDRCLKCH0_CR_DDRCRCLKPICODE.PiSettingRank[0-3]<br>- 0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch0ClkPiCodeOffset;<br>-<br>-/** Offset 0x0674 - Ch1 Clk PI Code Offset<br>- Offset to be applied to DDRCLKCH1_CR_DDRCRCLKPICODE.PiSettingRank[0-3]<br>- 0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch1ClkPiCodeOffset;<br>-<br>-/** Offset 0x0675 - Ch0 RcvEn Offset<br>- Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RcvEn<br>- 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch0RcvEnOffset;<br>-<br>-/** Offset 0x0676 - Ch1 RcvEn Offset<br>- Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.RcvEn<br>- 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch1RcvEnOffset;<br>-<br>-/** Offset 0x0677 - Ch0 Rx Dqs Offset<br>- Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset<br>- 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch0RxDqsOffset;<br>-<br>-/** Offset 0x0678 - Ch1 Rx Dqs Offset<br>- Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset<br>- 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch1RxDqsOffset;<br>-<br>-/** Offset 0x0679 - Ch0 Tx Dq Offset<br>- Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset<br>- 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch0TxDqOffset;<br>-<br>-/** Offset 0x067A - Ch1 Tx Dq Offset<br>- Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset<br>- 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch1TxDqOffset;<br>-<br>-/** Offset 0x067B - Ch0 Tx Dqs Offset<br>- Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset<br>- 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch0TxDqsOffset;<br>-<br>-/** Offset 0x067C - Ch1 Tx Dqs Offset<br>- Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset<br>- 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch1TxDqsOffset;<br>-<br>-/** Offset 0x067D - Ch0 Vref Offset<br>- Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset<br>- 0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch0VrefOffset;<br>-<br>-/** Offset 0x067E - Ch1 Vref Offset<br>- Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.VrefOffset<br>- 0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM<br>-**/<br>- UINT8 Ch1VrefOffset;<br>-<br>-/** Offset 0x067F - tRRSG<br>- Delay between Read-to-Read commands in the same Bank Group for DDR4 or Same Rank<br>- for DDR3/LPDDR3. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tRRSG;<br>-<br>-/** Offset 0x0680 - tRRDG<br>- Delay between Read-to-Read commands in different Bank Group for DDR4 or Same Rank<br>- for DDR3/LPDDR3. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tRRDG;<br>-<br>-/** Offset 0x0681 - tRRDR<br>- Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tRRDR;<br>-<br>-/** Offset 0x0682 - tRRDD<br>- Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tRRDD;<br>-<br>-/** Offset 0x0683 - tWRSG<br>- Delay between Write-to-Read commands in the same Bank Group for DDR4 or Same Rank<br>- for DDR3/LPDDR3. 0-Auto, Range 4-86.<br>-**/<br>- UINT8 tWRSG;<br>-<br>-/** Offset 0x0684 - tWRDG<br>- Delay between Write-to-Read commands in different Bank Group for DDR4 or Same Rank<br>- for DDR3/LPDDR3. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tWRDG;<br>-<br>-/** Offset 0x0685 - tWRDR<br>- Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tWRDR;<br>-<br>-/** Offset 0x0686 - tWRDD<br>- Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tWRDD;<br>-<br>-/** Offset 0x0687 - tWWSG<br>- Delay between Write-to-Write commands in the same Bank Group for DDR4 or Same Rank<br>- for DDR3/LPDDR3. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tWWSG;<br>-<br>-/** Offset 0x0688 - tWWDG<br>- Delay between Write-to-Write commands in different Bank Group for DDR4 or Same Rank<br>- for DDR3/LPDDR3. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tWWDG;<br>-<br>-/** Offset 0x0689 - tWWDR<br>- Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tWWDR;<br>-<br>-/** Offset 0x068A - tWWDD<br>- Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tWWDD;<br>-<br>-/** Offset 0x068B - tRWSG<br>- Delay between Read-to-Write commands in the same Bank Group for DDR4 or Same Rank<br>- for DDR3/LPDDR3. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tRWSG;<br>-<br>-/** Offset 0x068C - tRWDG<br>- Delay between Read-to-Write commands in different Bank Group for DDR4 or Same Rank<br>- for DDR3/LPDDR3. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tRWDG;<br>-<br>-/** Offset 0x068D - tRWDR<br>- Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tRWDR;<br>-<br>-/** Offset 0x068E - tRWDD<br>- Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54.<br>-**/<br>- UINT8 tRWDD;<br>-<br>-/** Offset 0x068F - DCTT Test<br>- Select which test to run<br>- 0:Basic walking memory test, 1:Row Hammer test<br>-**/<br>- UINT8 DcttTest;<br>-<br>-/** Offset 0x0690 - DCTT: Iterations on Row<br>- Number of repetitions on a Row<br>-**/<br>- UINT8 DcttRhIterationOnRow;<br>-<br>-/** Offset 0x0691 - Page Close Delay Prompt<br>- SubSequence Delay value used to ensure the page closes (In DClks)<br>-**/<br>- UINT8 DcttRhPageCloseDelay;<br>-<br>-/** Offset 0x0692 - Row Hammer Refresh<br>- Enable/Disables refreshes during the Row Hammer Test<br>- $EN_DIS<br>-**/<br>- UINT8 DcttRhRefreshEnable;<br>-<br>-/** Offset 0x0693 - Data Base<br>- Select which data pattern that is used as the base pattern<br>- 0:Zeros, 1:Ones, 2:Five, 3:A<br>-**/<br>- UINT8 DcttDataBase;<br>-<br>-/** Offset 0x0694 - DCTT: Row Hammer Count<br>- Number of Hammers for a given Row.<br>-**/<br>- UINT32 DcttRhHammerCount;<br>-<br>-/** Offset 0x0698 - Row swizzle<br>- Select which Row swizzle algorithm to use during Row Hammer test<br>- 0:No Swizzle, 1:3xOr1_3xOr2, 2:01234567EFCDAB89<br>-**/<br>- UINT8 DcttRowSwizzleType;<br>-<br>-/** Offset 0x0699 - Refresh Multiplier<br>- Multiplier applied to tREFI<br>-**/<br>- UINT8 DcttRefreshMultiplier;<br>-<br>-/** Offset 0x069A - Bank Disable Mask<br>- Bit Mask Bank Disable for per-Bank tests (Row Hammer)<br>-**/<br>- UINT8 DcttBankDisableMask;<br>-<br>-/** Offset 0x069B - Clock Gate AB<br>- Clock Gate AB<br>- 0:Disable, 1:2 Cycles, 2:3 Cycles, 3:4 Cycles<br>-**/<br>- UINT8 ScramClockGateAB;<br>-<br>-/** Offset 0x069C - Clock Gate C<br>- Select which Row swizzle algorithm to use during Row Hammer test<br>- 0:Disable, 1:2 Cycles, 2:4 Cycles, 3:8 Cycles<br>-**/<br>- UINT8 ScramClockGateC;<br>-<br>-/** Offset 0x069D - Enable DBI AB<br>- Enable DBI AB<br>- $EN_DIS<br>-**/<br>- UINT8 ScramEnableDbiAB;<br>-<br>-/** Offset 0x069E - MRC Interpreter<br>- Select CMOS location match of DD01 or Ctrl-Break key or force entry<br>- 0:CMOS, 1:Break, 2:Force<br>-**/<br>- UINT8 Interpreter;<br>-<br>-/** Offset 0x069F - ODT mode<br>- ODT mode<br>- 0:Default, 1:Ctt, 2:Vtt, 3:Vddq, 4:Vss,5:Max<br>-**/<br>- UINT8 IoOdtMode;<br>-<br>-/** Offset 0x06A0 - Lock DPR register<br>- Lock DPR register. <b>0: Platform POR </b>; 1: Enable; 2: Disable<br>- 0:Platform POR, 1: Enable, 2: Disable<br>-**/<br>- UINT8 TestMenuDprLock;<br>-<br>-/** Offset 0x06A1 - PerBankRefresh<br>- Control of Per Bank Refresh feature for LPDDR DRAMs<br>- $EN_DIS<br>-**/<br>- UINT8 PerBankRefresh;<br>-<br>-/** Offset 0x06A2 - Command Tristate<br>- Enables/Disable Command Tristate<br>- $EN_DIS<br>-**/<br>- UINT8 CmdTriStateDis;<br>-<br>-/** Offset 0x06A3<br>-**/<br>- UINT8 MrcRestrictedRsvd[1];<br>-<br>-/** Offset 0x06A4<br>-**/<br>- UINT8 ReservedFspmRestrictedUpd[26];<br>-} FSP_M_RESTRICTED_CONFIG;<br>-<br> /** Fsp M UPD Configuration<br> **/<br> typedef struct {<br>@@ -3343,10 +2646,6 @@<br> FSP_M_TEST_CONFIG FspmTestConfig;<br> <br> /** Offset 0x05B0<br>-**/<br>- FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;<br>-<br>-/** Offset 0x06BE<br> **/<br> UINT16 UpdTerminator;<br> } FSPM_UPD;<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>index ac660eb..2a2412d 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>@@ -1793,9 +1793,10 @@<br> UINT8 PchScsEmmcHs400DriverStrength;<br> <br> /** Offset 0x06FA - PCH SerialIo I2C Pads Termination<br>- 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak<br>- pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination<br>- respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.<br>+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,<br>+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5<br>+ pads termination respectively. One byte for each controller, byte0 for I2C0, byte1<br>+ for I2C1, and so on.<br> 0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU<br> **/<br> UINT8 PchSerialIoI2cPadsTermination[6];<br>@@ -2927,11 +2928,18 @@<br> **/<br> UINT8 C1StateUnDemotion;<br> <br>-/** Offset 0x08A2 - ReservedCpuPostMemTest<br>+/** Offset 0x08A2 - CpuWakeUpTimer<br>+ Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased<br>+ to 180 seconds. 0: Disable; <b>1: Enable</b><br>+ $EN_DIS<br>+**/<br>+ UINT8 CpuWakeUpTimer;<br>+<br>+/** Offset 0x08A3 - ReservedCpuPostMemTest<br> Reserved for CPU Post-Mem Test<br> $EN_DIS<br> **/<br>- UINT8 ReservedCpuPostMemTest[24];<br>+ UINT8 ReservedCpuPostMemTest[23];<br> <br> /** Offset 0x08BA - SgxSinitDataFromTpm<br> SgxSinitDataFromTpm default values<br>@@ -3080,16 +3088,9 @@<br> **/<br> UINT8 PchXhciOcLock;<br> <br>-/** Offset 0x0A61 - PCH USB Access Control setting<br>- This policy option controls setting the Access Control (ACCTRL) bit in XHCC1 which<br>- will lock write access to registers controlled by its functionality.<br>- $EN_DIS<br>+/** Offset 0x0A61<br> **/<br>- UINT8 PchXhciAcLock;<br>-<br>-/** Offset 0x0A62<br>-**/<br>- UINT8 UnusedUpdSpace26[16];<br>+ UINT8 UnusedUpdSpace26[17];<br> <br> /** Offset 0x0A72 - Skip POSTBOOT SAI<br> This skip the Post Boot Sai programming. 0: Set Post Boot Sai; 1: Skip Post Boot Sai.<br>@@ -3108,906 +3109,6 @@<br> UINT8 ReservedFspsTestUpd[12];<br> } FSP_S_TEST_CONFIG;<br> <br>-/** Fsp S Restricted Configuration<br>-**/<br>-typedef struct {<br>-<br>-/** Offset 0x0A80<br>-**/<br>- UINT32 Signature;<br>-<br>-/** Offset 0x0A84<br>-**/<br>- UINT8 UnusedUpdSpace27;<br>-<br>-/** Offset 0x0A85 - Enable or disable GNA Error Check Disable Bit<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 TestGnaErrorCheckDis;<br>-<br>-/** Offset 0x0A86 - Enable or disable VT-d DmaPassThrough<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 DmaPassThrough;<br>-<br>-/** Offset 0x0A87 - Enable or disable VT-d CCHit2pend<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 CCHit2pend;<br>-<br>-/** Offset 0x0A88 - Enable or disable VT-d ContextInvalidation<br>- 0(Default)=Disable, 1=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 ContextInvalidation;<br>-<br>-/** Offset 0x0A89 - Enable or disable VT-d IotlbInvalidation<br>- 0(Default)=Disable, 1=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 IotlbInvalidation;<br>-<br>-/** Offset 0x0A8A - Enable or disable VT-d ContextCacheDis<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 ContextCacheDis;<br>-<br>-/** Offset 0x0A8B - Enable or disable VT-d L1Disable<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 L1Disable;<br>-<br>-/** Offset 0x0A8C - Enable or disable VT-d L2Disable<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 L2Disable;<br>-<br>-/** Offset 0x0A8D - Enable or disable VT-d L3Disable<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 L3Disable;<br>-<br>-/** Offset 0x0A8E - Enable or disable VT-d L1Hit2PendDis<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 L1Hit2PendDis;<br>-<br>-/** Offset 0x0A8F - Enable or disable VT-d L3Hit2PendDis<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 L3Hit2PendDis;<br>-<br>-/** Offset 0x0A90 - Enable or disable VT-d InvQueueCohDis<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 InvQueueCohDis;<br>-<br>-/** Offset 0x0A91 - Enable or disable VT-d SuperPageCap<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 SuperPageCap;<br>-<br>-/** Offset 0x0A92 - Enable or disable VT-d QueueInvCapDis<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 QueueInvCapDis;<br>-<br>-/** Offset 0x0A93 - Enable or disable VT-d IntrRemapCapDis<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 TestIntrRemapCapDis;<br>-<br>-/** Offset 0x0A94 - Enable or disable VT-d SnoopControl<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 SnoopControl;<br>-<br>-/** Offset 0x0A95 - Enable or disable VT-d RemapReverseCtrl<br>- 0=Disable, 1(Default)=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 RemapReverseCtrl;<br>-<br>-/** Offset 0x0A96 - Enable or disable VT-d SvPolicyEnable<br>- 0(Default)=Disable, 1=Enable<br>- $EN_DIS<br>-**/<br>- UINT8 VtdSvPolicyEnable;<br>-<br>-/** Offset 0x0A97 - Sa Graphics Pei Test Force Wake<br>- Test Force Wake<br>-**/<br>- UINT8 SaTestForceWake;<br>-<br>-/** Offset 0x0A98 - Sa Graphics Pei Test Gfx Pause<br>- Test Gfx Pause<br>-**/<br>- UINT8 SaTestGfxPause;<br>-<br>-/** Offset 0x0A99 - Sa Graphics Pei Test Graphics Freq Modify<br>- Test Graphics Freq Modify<br>-**/<br>- UINT8 SaTestGraphicsFreqModify;<br>-<br>-/** Offset 0x0A9A - Sa Graphics Pei Test PmLock<br>- Test PmLock<br>-**/<br>- UINT8 SaTestPmLock;<br>-<br>-/** Offset 0x0A9B - Sa Graphics Pei Test Pavp Heavy Mode<br>- Test Pavp Heavy Mode<br>-**/<br>- UINT8 SaTestPavpHeavyMode;<br>-<br>-/** Offset 0x0A9C - Sa Graphics Pei Test Dop ClockGating<br>- Test Dop ClockGating<br>-**/<br>- UINT8 SaTestDopClockGating;<br>-<br>-/** Offset 0x0A9D - Sa Graphics Pei Test Unsolicited Attack Override<br>- Test Unsolicited Attack Override<br>-**/<br>- UINT8 SaTestUnsolicitedAttackOverride;<br>-<br>-/** Offset 0x0A9E - Sa Graphics Pei Test WOPCM Support<br>- Test WOPCM Support<br>-**/<br>- UINT8 SaTestWOPCMSupport;<br>-<br>-/** Offset 0x0A9F - Sa Graphics Pei Test Pavp Asmf<br>- Test Pavp Asmf<br>-**/<br>- UINT8 SaTestPavpAsmf;<br>-<br>-/** Offset 0x0AA0 - Sa Graphics Pei Test Power Gating<br>- Test Power Gating<br>-**/<br>- UINT8 SaTestPowerGating;<br>-<br>-/** Offset 0x0AA1 - Sa Graphics Pei Test Unit Level ClockGating<br>- Test Unit Level ClockGating<br>-**/<br>- UINT8 SaTestUnitLevelClockGating;<br>-<br>-/** Offset 0x0AA2 - Sa Graphics Pei Test Auto TearDown<br>- Test Auto TearDown<br>-**/<br>- UINT8 SaTestAutoTearDown;<br>-<br>-/** Offset 0x0AA3 - Sa Graphics Pei Test Graphics Video Freq<br>- Test Graphics Video Freq<br>-**/<br>- UINT8 SaTestGraphicsVideoFreq;<br>-<br>-/** Offset 0x0AA4 - Sa Graphics Pei Test WOPCM Size<br>- Test WOPCM Size<br>-**/<br>- UINT8 SaTestWOPCMSize;<br>-<br>-/** Offset 0x0AA5 - Sa Graphics Pei Test Graphics Freq Req<br>- Test Graphics Freq Req<br>-**/<br>- UINT8 SaTestGraphicsFreqReq;<br>-<br>-/** Offset 0x0AA6 - Sa Test Peg Aspm L0s Aggression<br>- Test Peg Aspm L0s Aggression<br>-**/<br>- UINT8 SaTestPegAspmL0sAggression[4];<br>-<br>-/** Offset 0x0AAA - Sa Clear CorrUnCorrErr Enable<br>- Clear CorrUnCorrErr Enable<br>- $EN_DIS<br>-**/<br>- UINT8 SaClearCorrUnCorrErrEnable;<br>-<br>-/** Offset 0x0AAB - Sa SvPegArifen<br>- SvPegArifen<br>-**/<br>- UINT8 SaSvPegArifen[4];<br>-<br>-/** Offset 0x0AAF - Sa Peg0 Completion Timeout<br>- Peg0 Completion Timeout<br>-**/<br>- UINT8 SaPeg0CompletionTimeout;<br>-<br>-/** Offset 0x0AB0 - Sa Peg1 Completion Timeout<br>- Peg1 Completion Timeout<br>-**/<br>- UINT8 SaPeg1CompletionTimeout;<br>-<br>-/** Offset 0x0AB1 - Sa Peg2 Completion Timeout<br>- Peg2 Completion Timeout<br>-**/<br>- UINT8 SaPeg2CompletionTimeout;<br>-<br>-/** Offset 0x0AB2 - Sa Peg3 Completion Timeout<br>- Peg3 Completion Timeout<br>-**/<br>- UINT8 SaPeg3CompletionTimeout;<br>-<br>-/** Offset 0x0AB3 - Sa Sv Peg Compliance Deemphasis<br>- SvPegComplianceDeemphasis<br>-**/<br>- UINT8 SaSvPegComplianceDeemphasis[4];<br>-<br>-/** Offset 0x0AB7 - Sa Sv Peg TxLn Staggering Mode<br>- SvPegTxLnStaggeringMode<br>-**/<br>- UINT8 SaSvPegTxLnStaggeringMode[4];<br>-<br>-/** Offset 0x0ABB - Sa Sv Peg TxLane Staggering Interval<br>- SvPegTxLaneStaggeringInterval<br>-**/<br>- UINT8 SaSvPegTxLaneStaggeringInterval[4];<br>-<br>-/** Offset 0x0ABF - Sa Sv Peg RxLn Staggering Mode<br>- SvPegRxLnStaggeringMode<br>-**/<br>- UINT8 SaSvPegRxLnStaggeringMode[4];<br>-<br>-/** Offset 0x0AC3 - Sa Sv Peg RxLane Staggering Interval<br>- SvPegRxLaneStaggeringInterval<br>-**/<br>- UINT8 SaSvPegRxLaneStaggeringInterval[4];<br>-<br>-/** Offset 0x0AC7 - Sa Test MpllOffSen<br>- TestMpllOffSen<br>-**/<br>- UINT8 SaTestMpllOffSen;<br>-<br>-/** Offset 0x0AC8 - Sa Test MdllOffSen<br>- TestMdllOffSen<br>-**/<br>- UINT8 SaTestMdllOffSen;<br>-<br>-/** Offset 0x0AC9 - Sa Test Mode Edram Internal<br>- Edram Enable Option<br>-**/<br>- UINT8 SaTestModeEdramInternal;<br>-<br>-/** Offset 0x0ACA - Sa Test Security Lock<br>- Enable/Disable Security lock<br>-**/<br>- UINT8 SaTestSecurityLock;<br>-<br>-/** Offset 0x0ACB<br>-**/<br>- UINT8 UnusedUpdSpace28[49];<br>-<br>-/** Offset 0x0AFC - SaPostMemRestrictedRsvd<br>- Reserved for SA Post-Mem Restricted<br>- $EN_DIS<br>-**/<br>- UINT8 SaPostMemRestrictedRsvd[22];<br>-<br>-/** Offset 0x0B12 - CpuPostMemRestrictedRsvd<br>- Reserved for CPU Post-Mem Restricted<br>- $EN_DIS<br>-**/<br>- UINT8 CpuPostMemRestrictedRsvd[16];<br>-<br>-/** Offset 0x0B22 - BiosGuardModulePtr<br>- BiosGuardModulePtr default values<br>-**/<br>- UINT8 EnableSgx7a;<br>-<br>-/** Offset 0x0B23 - SgxDebugMode<br>- SgxDebugMode default values<br>-**/<br>- UINT8 SgxDebugMode;<br>-<br>-/** Offset 0x0B24 - SvLtEnable<br>- SvLtEnable default values<br>-**/<br>- UINT8 SvLtEnable;<br>-<br>-/** Offset 0x0B25 - SelectiveEnableSgx<br>- SelectiveEnableSgx default values<br>-**/<br>- UINT8 SelectiveEnableSgx;<br>-<br>-/** Offset 0x0B26 - EpcOffset<br>- EpcOffset default values<br>-**/<br>- UINT64 EpcOffset;<br>-<br>-/** Offset 0x0B2E - EpcLength<br>- EpcLength default values<br>-**/<br>- UINT64 EpcLength;<br>-<br>-/** Offset 0x0B36 - SgxLCP<br>- SgxLCP default values<br>-**/<br>- UINT8 SgxLCP;<br>-<br>-/** Offset 0x0B37 - EpcLength<br>- EpcLength default values<br>-**/<br>- UINT64 SgxLEPubKeyHash0;<br>-<br>-/** Offset 0x0B3F - EpcLength<br>- EpcLength default values<br>-**/<br>- UINT64 SgxLEPubKeyHash1;<br>-<br>-/** Offset 0x0B47 - EpcLength<br>- EpcLength default values<br>-**/<br>- UINT64 SgxLEPubKeyHash2;<br>-<br>-/** Offset 0x0B4F - EpcLength<br>- EpcLength default values<br>-**/<br>- UINT64 SgxLEPubKeyHash3;<br>-<br>-/** Offset 0x0B57 - CpuPostMemRestrictedRsvd<br>- Reserved for CPU Post-Mem Restricted<br>- $EN_DIS<br>-**/<br>- UINT8 SecurityRestrictedRsvd[1];<br>-<br>-/** Offset 0x0B58 - MEM CLOSED State on PCH side<br>- Enable/Disable MEM CLOSED State on PCH side.<br>- $EN_DIS<br>-**/<br>- UINT8 PchDmiTestMemCloseStateEn;<br>-<br>-/** Offset 0x0B59 - Optimized Buffer Flush/Fill (OBFF) protocol for internal on PCH side<br>- enable/disable Optimized Buffer Flush/Fill (OBFF) protocol for internal on PCH side.<br>- $EN_DIS<br>-**/<br>- UINT8 PchDmiTestInternalObffEn;<br>-<br>-/** Offset 0x0B5A - Determines if force extended transmission of FTS ordered sets<br>- Determines if force extended transmission of FTS ordered sets when exiting L0s prior<br>- to entering L0.<br>-**/<br>- UINT8 PchDmiTestDmiExtSync;<br>-<br>-/** Offset 0x0B5B - Optimized Buffer Flush/Fill (OBFF) protocol for external on PCH side<br>- Enable/Disable Optimized Buffer Flush/Fill (OBFF) protocol for external on PCH side.<br>- $EN_DIS<br>-**/<br>- UINT8 PchDmiTestExternalObffEn;<br>-<br>-/** Offset 0x0B5C - Client Obff Enable<br>- Client Obff Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 PchDmiTestClientObffEn;<br>-<br>-/** Offset 0x0B5D - CxObff Entry Delay<br>- CxObff Entry Delay.<br>-**/<br>- UINT8 PchDmiTestCxObffEntryDelay;<br>-<br>-/** Offset 0x0B5E<br>-**/<br>- UINT8 UnusedUpdSpace29;<br>-<br>-/** Offset 0x0B5F - Pch Tc Lock Down<br>- Pch Tc Lock Down.<br>- $EN_DIS<br>-**/<br>- UINT8 PchDmiTestPchTcLockDown;<br>-<br>-/** Offset 0x0B60 - Enable DMI ASPM after booting to OS<br>- Enable DMI ASPM after booting to OS.<br>- $EN_DIS<br>-**/<br>- UINT8 PchDmiTestDelayEnDmiAspm;<br>-<br>-/** Offset 0x0B61 - Dmi Aspm Ctrl<br>- Dmi Aspm Ctrl.<br>- $EN_DIS<br>-**/<br>- UINT8 PchDmiTestDmiAspmCtrl;<br>-<br>-/** Offset 0x0B62 - DMI Secure Reg Lock<br>- DMI Secure Reg Lock.<br>- 0: POR (Enable), 1: Enable, 2: Disable<br>-**/<br>- UINT8 PchDmiTestDmiSecureRegLock;<br>-<br>-/** Offset 0x0B63<br>-**/<br>- UINT8 UnusedUpdSpace30;<br>-<br>-/** Offset 0x0B64 - Configuration Lockdown (BCLD)<br>- 0: POR (Enable), 1: Enable, 2: Disable.<br>- 0: POR (Enable), 1: Enable, 2: Disable<br>-**/<br>- UINT8 PchHdaTestConfigLockdown;<br>-<br>-/** Offset 0x0B65 - Low Frequency Link Clock Source (LFLCS)<br>- 0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL).<br>- 0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL)<br>-**/<br>- UINT8 PchHdaTestLowFreqLinkClkSrc;<br>-<br>-/** Offset 0x0B66<br>-**/<br>- UINT8 UnusedUpdSpace31[4];<br>-<br>-/** Offset 0x0B6A - PCH Lan Test WOL Fast Support<br>- Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm.<br>- $EN_DIS<br>-**/<br>- UINT8 PchLanTestPchWOLFastSupport;<br>-<br>-/** Offset 0x0B6B - Smi Unlock bit for SV policy<br>- 0: Lock; 1: Unlock.<br>- $EN_DIS<br>-**/<br>- UINT8 PchLockDownTestSmiUnlock;<br>-<br>-/** Offset 0x0B6C - PchPostMemRestrictedRsvd<br>- Reserved for PCH Post-Mem Restricted Reserved<br>- $EN_DIS<br>-**/<br>- UINT8 PchPostMemRestrictedRsvd[24];<br>-<br>-/** Offset 0x0B84 - Gen3 EQ Phase2 Tx override<br>- Coefficient requested by the remote device is ignored.<br>-**/<br>- UINT8 PcieRpTestEqPh2Override[24];<br>-<br>-/** Offset 0x0B9C - Tx preset to use when TestEqPh2Override is set<br>- Tx preset to use when TestEqPh2Override is set.<br>-**/<br>- UINT8 PcieRpTestEqPh2Preset[24];<br>-<br>-/** Offset 0x0BB4 - Enable/Disable ASPM Optionality Compliance<br>- Enable/Disable ASPM Optionality Compliance.<br>-**/<br>- UINT8 PcieRpTestAspmOc[24];<br>-<br>-/** Offset 0x0BCC - Force LTR Override<br>- Force LTR Override.<br>-**/<br>- UINT8 PcieRpTestForceLtrOverride[24];<br>-<br>-/** Offset 0x0BE4<br>-**/<br>- UINT8 UnusedUpdSpace32[72];<br>-<br>-/** Offset 0x0C2C - PCH Pcie bem<br>- PCH Pcie bem.<br>-**/<br>- UINT8 PcieTestPchPciebem;<br>-<br>-/** Offset 0x0C2D - PCH Pcie Test bem Port Index<br>- PCH Pcie Test bem Port Index.<br>-**/<br>- UINT8 PcieTestPchPciebemPortIndex;<br>-<br>-/** Offset 0x0C2E - PCH Test PcieRp dbc gen<br>- PCH Test PcieRp dbc gen.<br>-**/<br>- UINT8 PcieTestPchPcieRpdbcgen;<br>-<br>-/** Offset 0x0C2F - PCH Test PcieRp dlc gen<br>- PCH Test PcieRp dlc gen.<br>-**/<br>- UINT8 PcieTestPchPcieRpdlcgen;<br>-<br>-/** Offset 0x0C30 - PCH Test Pcie Dcgeisma<br>- PCH Test Pcie Dcgeisma.<br>-**/<br>- UINT8 PcieTestPchPcieDcgeisma;<br>-<br>-/** Offset 0x0C31 - PCH Test PcieRp scgen<br>- PCH Test PcieRp scgen.<br>-**/<br>- UINT8 PcieTestPchPcieRpscgen;<br>-<br>-/** Offset 0x0C32 - PCH Test Pcie Srdbcgen<br>- PCH Test Pcie Srdbcgen.<br>-**/<br>- UINT8 PcieTestPchPcieSrdbcgen;<br>-<br>-/** Offset 0x0C33 - PCH Test Pcie Scptcge<br>- PCH Test Pcie Scptcge.<br>-**/<br>- UINT8 PcieTestPchPcieScptcge;<br>-<br>-/** Offset 0x0C34 - PCH Test Pcie Fdppge<br>- PCH Test Pcie Fdppge.<br>-**/<br>- UINT8 PcieTestPchPcieFdppge;<br>-<br>-/** Offset 0x0C35 - PCH Test Pcie Phyclpge<br>- PCH Test Pcie Phyclpge.<br>-**/<br>- UINT8 PcieTestPchPciePhyclpge;<br>-<br>-/** Offset 0x0C36 - PCH Test Pcie Fdcpge<br>- PCH Test Pcie Fdcpge.<br>-**/<br>- UINT8 PcieTestPchPcieFdcpge;<br>-<br>-/** Offset 0x0C37 - PCH Test Pcie Detscpge<br>- PCH Test Pcie Detscpge.<br>-**/<br>- UINT8 PcieTestPchPcieDetscpge;<br>-<br>-/** Offset 0x0C38 - PCH Test Pcie L23 rdyscpge<br>- PCH Test Pcie L23 rdyscpge.<br>-**/<br>- UINT8 PcieTestPchPcieL23rdyscpge;<br>-<br>-/** Offset 0x0C39 - PCH Test Pcie Disscpge<br>- PCH Test Pcie Disscpge.<br>-**/<br>- UINT8 PcieTestPchPcieDisscpge;<br>-<br>-/** Offset 0x0C3A - PCH Test Pcie L1 scpge<br>- PCH Test Pcie L1 scpge.<br>-**/<br>- UINT8 PcieTestPchPcieL1scpge;<br>-<br>-/** Offset 0x0C3B - PCH Pcie Test Lane Eq En<br>- PCH PcieTest Lane Eq En.<br>-**/<br>- UINT8 PcieTestLaneEqEn;<br>-<br>-/** Offset 0x0C3C - PCH Pcie Test Sw Eq Override<br>- PCH Pcie bem.<br>-**/<br>- UINT8 PcieTestSwEqOverride;<br>-<br>-/** Offset 0x0C3D - PCH Pcie Test Sw Eq Dwell Time Us<br>- PCH Pcie Test Sw Eq Dwell Time Us.<br>-**/<br>- UINT16 PcieTestSwEqDwellTimeUs;<br>-<br>-/** Offset 0x0C3F - PCH Pcie Test Sw Eq Error Threshold<br>- PCH Pcie Test Sw Eq Error Threshold.<br>-**/<br>- UINT16 PcieTestSwEqErrorThreshold;<br>-<br>-/** Offset 0x0C41 - PCH Pcie Test Sw Eq Rec Threshold<br>- PCH Pcie Test Sw Eq Rec Threshold.<br>-**/<br>- UINT16 PcieTestSwEqRecThreshold;<br>-<br>-/** Offset 0x0C43 - PCH Pcie Test Sw Eq Retrain Timeout Ms<br>- PCH Pcie Test Sw Eq Retrain Timeout Ms.<br>-**/<br>- UINT16 PcieTestSwEqRetrainTimeoutMs;<br>-<br>-/** Offset 0x0C45 - PCH Pcie Test Sw Eq Recovery Wait<br>- PCH Pcie Test Sw Eq Recovery Wait.<br>-**/<br>- UINT16 PcieTestSwEqRecoveryWait;<br>-<br>-/** Offset 0x0C47 - PCH Pm Register Lock<br>- PCH Pm Register Lock.<br>-**/<br>- UINT8 PchPmTestPchPmRegisterLock;<br>-<br>-/** Offset 0x0C48 - PCH Pm Test SlpS0 CsMe PgQDis<br>- CPPM VRIC CSME Power Gated Qualification Disable.<br>-**/<br>- UINT8 PchPmTestSlpS0CsMePgQDis;<br>-<br>-/** Offset 0x0C49 - PCH Pm Test Slp S0 Gbe Disc QDis<br>- CPPM VRIC GbE Disconnected Qualification Disable.<br>-**/<br>- UINT8 PchPmTestSlpS0GbeDiscQDis;<br>-<br>-/** Offset 0x0C4A - PCH Pm Test Slp S0A Dsp D3 QDis<br>- CPPM VRIC Audio DSP is in D3 Qualification Disable.<br>-**/<br>- UINT8 PchPmTestSlpS0ADspD3QDis;<br>-<br>-/** Offset 0x0C4B - PCH Pm Test Slp S0 Xhci D3QDis<br>- CPPM VRIC XHCI is in D3 Qualification Disable.<br>-**/<br>- UINT8 PchPmTestSlpS0XhciD3QDis;<br>-<br>-/** Offset 0x0C4C - PCH Pm Test Slp S0 Lpio D3QDis<br>- CPPM VRIC LPIO is in D3 Qualification Disable.<br>-**/<br>- UINT8 PchPmTestSlpS0LpioD3QDis;<br>-<br>-/** Offset 0x0C4D - PCH Pm Test Slp S0 Icc Pll W BEn<br>- CPPM VRIC ICC PLL Wake Block Enable.<br>-**/<br>- UINT8 PchPmTestSlpS0IccPllWBEn;<br>-<br>-/** Offset 0x0C4E - PCH Pm Test Slp S0 PUGB En<br>- PCH Pm CPPM VRIC Power Ungate Block Enable.<br>-**/<br>- UINT8 PchPmTestSlpS0PUGBEn;<br>-<br>-/** Offset 0x0C4F - PCH Pm Test Clear Power Sts<br>- @todo ADD DESCRIPTION. Policy for SV usage. NO USE..<br>-**/<br>- UINT8 PchPmTestPchClearPowerSts;<br>-<br>-/** Offset 0x0C50 - PCH Sata Test Rst Pcie Storage Test Mode<br>- PCIe Storage remapping Test Mode to override existing PCIe Storage remapping POR<br>- setting for development purpose.<br>-**/<br>- UINT8 SataTestRstPcieStorageTestMode[3];<br>-<br>-/** Offset 0x0C53 - PCH Sata Test Rst Pcie Storage Port Config Check<br>- Enable/Disable Port Configuration Check for RST PCIe Storage Remapping.<br>-**/<br>- UINT8 SataTestRstPcieStoragePortConfigCheck[3];<br>-<br>-/** Offset 0x0C56 - PCH Sata Test Rst Pcie Storage Device Interface<br>- Select the device interface (AHCI/NVME) for remapped device. NO USE.<br>-**/<br>- UINT8 SataTestRstPcieStorageDeviceInterface[3];<br>-<br>-/** Offset 0x0C59 - PCH Sata Test Rst Pcie Storage Device Bar Size Check<br>- Enable/Disable Device BAR Size Check for remapped device.<br>-**/<br>- UINT8 SataTestRstPcieStorageDeviceBarSizeCheck[3];<br>-<br>-/** Offset 0x0C5C - PCH Sata Test Rst Pcie Storage Device Bar Select<br>- Select the device BAR (BAR0-BAR5) that will be used for Remapping.<br>-**/<br>- UINT8 SataTestRstPcieStorageDeviceBarSelect[3];<br>-<br>-/** Offset 0x0C5F - PCH Sata Test Rst Pcie Storage Device Interrupt<br>- Select the device interrupt (Legacy/MSIX) for remapped device.<br>-**/<br>- UINT8 SataTestRstPcieStorageDeviceInterrupt[3];<br>-<br>-/** Offset 0x0C62 - PCH Sata Test Rst Pcie Storage Aspm Programming<br>- Enable/Disable ASPM Programming for remapped device.<br>-**/<br>- UINT8 SataTestRstPcieStorageAspmProgramming[3];<br>-<br>-/** Offset 0x0C65 - PCH Sata Test Rst Pcie Storage Save Restore<br>- Enable/Disable ASPM Programming for remapped device.<br>-**/<br>- UINT8 SataTestRstPcieStorageSaveRestore[3];<br>-<br>-/** Offset 0x0C68 - Latency Tolerance Reporting Mechanism<br>- Latency Tolerance Reporting Mechanism.<br>-**/<br>- UINT8 SataTestLtrEnable;<br>-<br>-/** Offset 0x0C69 - Latency Tolerance Reporting Mechanism<br>- Latency Tolerance Reporting Mechanism.<br>-**/<br>- UINT8 SataTestLtrConfigLock;<br>-<br>-/** Offset 0x0C6A - Latency Tolerance Reporting Mechanism<br>- Latency Tolerance Reporting Mechanism.<br>-**/<br>- UINT8 SataTestLtrOverride;<br>-<br>-/** Offset 0x0C6B - Latency Tolerance Reporting Mechanism<br>- Latency Tolerance Reporting Mechanism.<br>-**/<br>- UINT8 SataTestSnoopLatencyOverrideMultiplier;<br>-<br>-/** Offset 0x0C6C - Latency Tolerance Reporting Mechanism<br>- Latency Tolerance Reporting Mechanism.<br>-**/<br>- UINT16 SataTestSnoopLatencyOverrideValue;<br>-<br>-/** Offset 0x0C6E - Latency Tolerance Reporting Mechanism<br>- Latency Tolerance Reporting Mechanism.<br>-**/<br>- UINT8 SataTestSataAssel;<br>-<br>-/** Offset 0x0C6F<br>-**/<br>- UINT8 UnusedUpdSpace33[2];<br>-<br>-/** Offset 0x0C71 - This locks down Enables the thermal sensor<br>- 0: Disabled, 1: Enabled.<br>- $EN_DIS<br>-**/<br>- UINT8 PchTestTselLock;<br>-<br>-/** Offset 0x0C72 - This locks down Catastrophic Power-Down Enable and Catastrophic Trip Point Register<br>- 0: Disabled, 1: Enabled.<br>- $EN_DIS<br>-**/<br>- UINT8 PchTestTscLock;<br>-<br>-/** Offset 0x0C73 - This locks down PHL and PHLC<br>- 0: Disabled, 1: Enabled.<br>- $EN_DIS<br>-**/<br>- UINT8 PchTestPhlcLock;<br>-<br>-/** Offset 0x0C74<br>-**/<br>- UINT8 UnusedUpdSpace34[10];<br>-<br>-/** Offset 0x0C7E - USB EP Type Lock Policy<br>- USB EP Type Lock Policy.<br>-**/<br>- UINT32 PchTestEPTypeLockPolicy;<br>-<br>-/** Offset 0x0C82 - USB EP Type Lock Policy Control 1<br>- USB EP Type Lock Policy Control 1.<br>-**/<br>- UINT32 PchTestEPTypeLockPolicyPortControl1;<br>-<br>-/** Offset 0x0C86 - USB EP Type Lock Policy Control 2<br>- USB EP Type Lock Policy Control 2.<br>-**/<br>- UINT32 PchTestEPTypeLockPolicyPortControl2;<br>-<br>-/** Offset 0x0C8A<br>-**/<br>- UINT8 UnusedUpdSpace35[4];<br>-<br>-/** Offset 0x0C8E - Xhci Controller Enable<br>- 0: Disable; 1: Enable.<br>-**/<br>- UINT8 PchTestControllerEnabled;<br>-<br>-/** Offset 0x0C8F<br>-**/<br>- UINT8 UnusedUpdSpace36;<br>-<br>-/** Offset 0x0C90 - Unlock to enable NOA for SV usage<br>- 1: Unlock to enable NOA usage. 0: Set Xhci OC registers, Set Xhci OCCDone bit, XHCI<br>- Access Control Bit.<br>- $EN_DIS<br>-**/<br>- UINT8 PchTestUnlockUsbForSvNoa;<br>-<br>-/** Offset 0x0C91 - Enable XHCI Clock Gating for SV usage<br>- 1: Enable XHCI Clock Gating. 0: Disable XHCI Clock Gating. Policy for SV usage.<br>- $EN_DIS<br>-**/<br>- UINT8 PchTestClkGatingXhci;<br>-<br>-/** Offset 0x0C92 - Restricted Cyclone Pcie Switch WA<br>- Restricted Cyclone Pcie Switch WA.<br>-**/<br>- UINT8 PchTestCyclonePcieSwitchWA;<br>-<br>-/** Offset 0x0C93 - Restricted Pch Root Port<br>- Restricted Pch Root Port.<br>-**/<br>- UINT8 PchTestPchRootPort;<br>-<br>-/** Offset 0x0C94<br>-**/<br>- UINT8 UnusedUpdSpace37[2];<br>-<br>-/** Offset 0x0C96 - Restricted Flash Lock Down<br>- Restricted Flash Lock Down.<br>-**/<br>- UINT8 PchTestFlashLockDown;<br>-<br>-/** Offset 0x0C97<br>-**/<br>- UINT8 UnusedUpdSpace38[2];<br>-<br>-/** Offset 0x0C99 - PCH PMC ER Debug mode<br>- Disable/Enable Energy Reporting Debug Mode.<br>- $EN_DIS<br>-**/<br>- UINT8 TestPchPmErDebugMode;<br>-<br>-/** Offset 0x0C9A<br>-**/<br>- UINT8 UnusedUpdSpace39[2];<br>-<br>-/** Offset 0x0C9C - USB2/TS LDO Dynamic Shutdown<br>- Enable/Disable USB2/TS LDO Dynamic Shutdown<br>- 0: POR, 1: force enable, 2: force disable<br>-**/<br>- UINT8 TestUsbTsLdoShutdown;<br>-<br>-/** Offset 0x0C9D - OPI PLL Power Gating<br>- OPI PLL Power Gating.<br>- 0: POR, 1: force enable, 2: force disable<br>-**/<br>- UINT8 PchDmiTestOpiPllPowerGating;<br>-<br>-/** Offset 0x0C9E - HDA Power/Clock Gating (PGD/CGD)<br>- Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:<br>- FORCE_ENABLE, 2: FORCE_DISABLE.<br>- 0: POR, 1: Force Enable, 2: Force Disable<br>-**/<br>- UINT8 PchHdaTestPowerClockGating;<br>-<br>-/** Offset 0x0C9F - CNVi BT Core<br>- Enable/Disable CNVi BT Core. 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.<br>- 0: POR, 1: Force Enable, 2: Force Disable<br>-**/<br>- UINT8 TestCnviBtCore;<br>-<br>-/** Offset 0x0CA0 - CNVi BT Wireless Charging <br>- Enable/Disable CNVi BT Wireless Charging. 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.<br>- 0: POR, 1: Force Enable, 2: Force Disable<br>-**/<br>- UINT8 TestCnviBtWirelessCharging;<br>-<br>-/** Offset 0x0CA1 - CNVi WiFi LTR<br>- Enable/Disable CNVi WiFi LTR. 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.<br>- 0: POR, 1: Force Enable, 2: Force Disable<br>-**/<br>- UINT8 TestCnviWifiLtrEn;<br>-<br>-/** Offset 0x0CA2 - PCH Pm Latch events C10 exit<br>- PCH Pm Latch events C10 exit Enable.<br>- 0: POR, 1: force enable, 2: force disable<br>-**/<br>- UINT8 TestPchPmLatchEventsC10Exit;<br>-<br>-/** Offset 0x0CA3 - CNVi LTE Coexistence<br>- Enable/Disable MFUART2 connection for coexistence between LTE and Wi-Fi/BT. 0: PLATFORM_POR,<br>- 1: FORCE_ENABLE, 2: FORCE_DISABLE.<br>- 0: POR, 1: Force Enable, 2: Force Disable<br>-**/<br>- UINT8 TestCnviLteCoex;<br>-<br>-/** Offset 0x0CA4 - PCIE Allow L0s with Gen3<br>- Allows PCH rootports to have both L0s and Gen3 speed enabled at the same time.<br>- $EN_DIS<br>-**/<br>- UINT8 PcieAllowL0sWithGen3;<br>-<br>-/** Offset 0x0CA5 - CNVi BT Interface<br>- This option configures BT device interface to either USB or UART<br>- 0:UART, 1:USB<br>-**/<br>- UINT8 TestCnviBtInterface;<br>-<br>-/** Offset 0x0CA6 - CNVi BT Uart Type<br>- This is a test option which allows configuration of UART type for BT communication<br>- 0:Serial IO Uart0, 1:ISH Uart0, 2:Uart over external pads<br>-**/<br>- UINT8 TestCnviBtUartType;<br>-<br>-/** Offset 0x0CA7 - Enable/Disable DMI L1 entry disable mode <br>- Enable/Disable DMI L1 entry disable mode.<br>-**/<br>- UINT8 PcieRpTestDmiL1Edm[24];<br>-<br>-/** Offset 0x0CBF - PchSiliconRestrictedRsvd<br>- Reserved for PCH Post-Mem Restricted<br>- $EN_DIS<br>-**/<br>- UINT8 PchSiliconRestrictedRsvd[3];<br>-<br>-/** Offset 0x0CC2 - Si Config SvPolicyEnable.<br>- Platform specific common policies that used by several silicon components. SvPolicyEnable.<br>- $EN_DIS<br>-**/<br>- UINT8 SiSvPolicyEnable;<br>-<br>-/** Offset 0x0CC3 - Si Config HsleWorkaround<br>- Enable/Disable HSLE model specific workarounds<br>- $EN_DIS<br>-**/<br>- UINT8 HsleWorkaround;<br>-<br>-/** Offset 0x0CC4<br>-**/<br>- UINT8 ReservedFspsRestrictedUpd[4];<br>-} FSP_S_RESTRICTED_CONFIG;<br>-<br> /** Fsp S UPD Configuration<br> **/<br> typedef struct {<br>@@ -4025,10 +3126,6 @@<br> FSP_S_TEST_CONFIG FspsTestConfig;<br> <br> /** Offset 0x0A80<br>-**/<br>- FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig;<br>-<br>-/** Offset 0x0CC8<br> **/<br> UINT16 UpdTerminator;<br> } FSPS_UPD;<br></pre><p>To view, visit <a href="https://review.coreboot.org/22052">change 22052</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22052"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I065edbeffdaf555ea7d54ec3fdce56d026789c52 </div>
<div style="display:none"> Gerrit-Change-Number: 22052 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>