<p>Youness Alaoui would like Matt DeVillier to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/22048">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">purism/librem_skl: add new variant Librem 15 v3<br><br>Add new board librem15v3 as a variant of the librem_skl baseboard.<br><br>Changes from the librem13v2:<br>- Change board name and version<br>- Change GPIO A18, A19, A20, D9, D10 and D11 from NC to GPIO<br>- Enable PCI device 1c.4<br>- Change USB port definitions in devicetree<br><br>Change-Id: I7c762a34f5b961c908e4a29ec331da4b0dea9986<br>Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm><br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/purism/librem_skl/Kconfig<br>M src/mainboard/purism/librem_skl/Kconfig.name<br>A src/mainboard/purism/librem_skl/variants/librem15v3/board_info.txt<br>A src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb<br>A src/mainboard/purism/librem_skl/variants/librem15v3/include/variant/gpio.h<br>5 files changed, 432 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/22048/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig<br>index de6b167..fc77518 100644<br>--- a/src/mainboard/purism/librem_skl/Kconfig<br>+++ b/src/mainboard/purism/librem_skl/Kconfig<br>@@ -18,6 +18,7 @@<br> config VARIANT_DIR<br> string<br> default "librem13v2" if BOARD_PURISM_LIBREM13_V2<br>+ default "librem15v3" if BOARD_PURISM_LIBREM15_V3<br> <br> config MAINBOARD_VENDOR<br> string<br>@@ -26,14 +27,17 @@<br> config MAINBOARD_FAMILY<br> string<br> default "Librem 13" if BOARD_PURISM_LIBREM13_V2<br>+ default "Librem 15" if BOARD_PURISM_LIBREM15_V3<br> <br> config MAINBOARD_PART_NUMBER<br> string<br> default "Librem 13 v2" if BOARD_PURISM_LIBREM13_V2<br>+ default "Librem 15 v3" if BOARD_PURISM_LIBREM15_V3<br> <br> config MAINBOARD_VERSION<br> string<br> default "2.0" if BOARD_PURISM_LIBREM13_V2<br>+ default "3.0" if BOARD_PURISM_LIBREM15_V3<br> <br> config MAINBOARD_DIR<br> string<br>@@ -42,6 +46,7 @@<br> config DEVICETREE<br> string<br> default "variants/librem13v2/devicetree.cb" if BOARD_PURISM_LIBREM13_V2<br>+ default "variants/librem15v3/devicetree.cb" if BOARD_PURISM_LIBREM15_V3<br> <br> config MAX_CPUS<br> int<br>diff --git a/src/mainboard/purism/librem_skl/Kconfig.name b/src/mainboard/purism/librem_skl/Kconfig.name<br>index 06fa372..3f43f68 100644<br>--- a/src/mainboard/purism/librem_skl/Kconfig.name<br>+++ b/src/mainboard/purism/librem_skl/Kconfig.name<br>@@ -1,3 +1,7 @@<br> config BOARD_PURISM_LIBREM13_V2<br> bool "Librem 13 v2"<br> select BOARD_PURISM_BASEBOARD_LIBREM_SKL<br>+<br>+config BOARD_PURISM_LIBREM15_V3<br>+ bool "Librem 15 v3"<br>+ select BOARD_PURISM_BASEBOARD_LIBREM_SKL<br>diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/board_info.txt b/src/mainboard/purism/librem_skl/variants/librem15v3/board_info.txt<br>new file mode 100644<br>index 0000000..9617baf<br>--- /dev/null<br>+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/board_info.txt<br>@@ -0,0 +1,9 @@<br>+Vendor name: Purism<br>+Board name: Librem 15 v3<br>+Board URL: https://puri.sm/librem-15/<br>+Category: laptop<br>+ROM package: SOIC8<br>+ROM protocol: SPI<br>+ROM socketed: n<br>+Flashrom support: y<br>+Release year: 2017<br>diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb<br>new file mode 100644<br>index 0000000..647f054<br>--- /dev/null<br>+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb<br>@@ -0,0 +1,213 @@<br>+chip soc/intel/skylake<br>+<br>+ # Enable deep Sx states<br>+ register "deep_s3_enable_ac" = "0"<br>+ register "deep_s3_enable_dc" = "0"<br>+ register "deep_s5_enable_ac" = "0"<br>+ register "deep_s5_enable_dc" = "0"<br>+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"<br>+<br>+ # GPE configuration<br>+ # Note that GPE events called out in ASL code rely on this<br>+ # route. i.e. If this route changes then the affected GPE<br>+ # offset bits also need to be changed.<br>+ register "gpe0_dw0" = "GPP_C"<br>+ register "gpe0_dw1" = "GPP_D"<br>+ register "gpe0_dw2" = "GPP_E"<br>+<br>+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f<br>+ register "gen1_dec" = "0x00fc0801"<br>+ register "gen2_dec" = "0x000c0201"<br>+<br>+ # Enable "Intel Speed Shift Technology"<br>+ register "speed_shift_enable" = "1"<br>+<br>+ # Enable DPTF<br>+ register "dptf_enable" = "1"<br>+<br>+ # FSP Configuration<br>+ register "ProbelessTrace" = "0"<br>+ register "EnableLan" = "0"<br>+ register "EnableSata" = "1"<br>+ register "SataSalpSupport" = "0"<br>+ register "SataMode" = "0"<br>+ register "SataPortsEnable[0]" = "1"<br>+ register "SataPortsEnable[1]" = "0"<br>+ register "SataPortsEnable[2]" = "1"<br>+ register "SataPortsDevSlp[0]" = "0"<br>+ register "SataPortsDevSlp[2]" = "0"<br>+ register "SataSpeedLimit" = "2"<br>+ register "EnableAzalia" = "1"<br>+ register "DspEnable" = "0"<br>+ register "IoBufferOwnership" = "0"<br>+ register "EnableTraceHub" = "0"<br>+ register "XdciEnable" = "0"<br>+ register "SsicPortEnable" = "0"<br>+ register "SmbusEnable" = "1"<br>+ register "Cio2Enable" = "0"<br>+ register "ScsEmmcEnabled" = "0"<br>+ register "ScsEmmcHs400Enabled" = "0"<br>+ register "ScsSdCardEnabled" = "0"<br>+ register "IshEnable" = "0"<br>+ register "PttSwitch" = "0"<br>+ register "InternalGfx" = "1"<br>+ register "SkipExtGfxScan" = "1"<br>+ register "Device4Enable" = "1"<br>+ register "HeciEnabled" = "0"<br>+ register "FspSkipMpInit" = "1"<br>+ register "SaGv" = "3"<br>+ register "SerialIrqConfigSirqEnable" = "1"<br>+ register "PmConfigSlpS3MinAssert" = "2" # 50ms<br>+ register "PmConfigSlpS4MinAssert" = "1" # 1s<br>+ register "PmConfigSlpSusMinAssert" = "3" # 500ms<br>+ register "PmConfigSlpAMinAssert" = "3" # 2s<br>+ register "PmTimerDisabled" = "0"<br>+<br>+ register "pirqa_routing" = "PCH_IRQ11"<br>+ register "pirqb_routing" = "PCH_IRQ10"<br>+ register "pirqc_routing" = "PCH_IRQ11"<br>+ register "pirqd_routing" = "PCH_IRQ11"<br>+ register "pirqe_routing" = "PCH_IRQ11"<br>+ register "pirqf_routing" = "PCH_IRQ11"<br>+ register "pirqg_routing" = "PCH_IRQ11"<br>+ register "pirqh_routing" = "PCH_IRQ11"<br>+<br>+ # VR Settings Configuration for 4 Domains<br>+ #+----------------+-------+-------+-------------+-------+<br>+ #| Domain/Setting | SA | IA | GT Unsliced | GT |<br>+ #+----------------+-------+-------+-------------+-------+<br>+ #| Psi1Threshold | 20A | 20A | 20A | 20A |<br>+ #| Psi2Threshold | 4A | 5A | 5A | 5A |<br>+ #| Psi3Threshold | 1A | 1A | 1A | 1A |<br>+ #| Psi3Enable | 1 | 1 | 1 | 1 |<br>+ #| Psi4Enable | 1 | 1 | 1 | 1 |<br>+ #| ImonSlope | 0 | 0 | 0 | 0 |<br>+ #| ImonOffset | 0 | 0 | 0 | 0 |<br>+ #| IccMax | 7A | 34A | 35A | 35A |<br>+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |<br>+ #+----------------+-------+-------+-------------+-------+<br>+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{<br>+ .vr_config_enable = 1,<br>+ .psi1threshold = VR_CFG_AMP(20),<br>+ .psi2threshold = VR_CFG_AMP(4),<br>+ .psi3threshold = VR_CFG_AMP(1),<br>+ .psi3enable = 1,<br>+ .psi4enable = 1,<br>+ .imon_slope = 0x0,<br>+ .imon_offset = 0x0,<br>+ .icc_max = VR_CFG_AMP(7),<br>+ .voltage_limit = 1520,<br>+ }"<br>+<br>+ register "domain_vr_config[VR_IA_CORE]" = "{<br>+ .vr_config_enable = 1,<br>+ .psi1threshold = VR_CFG_AMP(20),<br>+ .psi2threshold = VR_CFG_AMP(5),<br>+ .psi3threshold = VR_CFG_AMP(1),<br>+ .psi3enable = 1,<br>+ .psi4enable = 1,<br>+ .imon_slope = 0x0,<br>+ .imon_offset = 0x0,<br>+ .icc_max = VR_CFG_AMP(34),<br>+ .voltage_limit = 1520,<br>+ }"<br>+<br>+ register "domain_vr_config[VR_GT_UNSLICED]" = "{<br>+ .vr_config_enable = 1,<br>+ .psi1threshold = VR_CFG_AMP(20),<br>+ .psi2threshold = VR_CFG_AMP(5),<br>+ .psi3threshold = VR_CFG_AMP(1),<br>+ .psi3enable = 1,<br>+ .psi4enable = 1,<br>+ .imon_slope = 0x0,<br>+ .imon_offset = 0x0,<br>+ .icc_max = VR_CFG_AMP(35),<br>+ .voltage_limit = 1520,<br>+ }"<br>+<br>+ register "domain_vr_config[VR_GT_SLICED]" = "{<br>+ .vr_config_enable = 1,<br>+ .psi1threshold = VR_CFG_AMP(20),<br>+ .psi2threshold = VR_CFG_AMP(5),<br>+ .psi3threshold = VR_CFG_AMP(1),<br>+ .psi3enable = 1,<br>+ .psi4enable = 1,<br>+ .imon_slope = 0x0,<br>+ .imon_offset = 0x0,<br>+ .icc_max = VR_CFG_AMP(35),<br>+ .voltage_limit = 1520,<br>+ }"<br>+<br>+ # Enable Root Ports 5 and 9<br>+ register "PcieRpEnable[4]" = "1"<br>+ register "PcieRpEnable[8]" = "1"<br>+ # Enable CLKREQ# for RP9<br>+ register "PcieRpClkReqSupport[8]" = "0"<br>+ # ClkReq for NVMe - Bruteforced (no other value works)<br>+ register "PcieRpClkReqNumber[8]" = "2"<br>+<br>+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port<br>+ register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)<br>+ register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)<br>+ register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)<br>+ register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)<br>+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth<br>+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera<br>+ register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD<br>+<br>+ # OC0 should be for Type-C but it seems to not have been wired, according to<br>+ # the available schematics, even though it is labeled as USB_OC_TYPEC.<br>+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port<br>+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)<br>+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)<br>+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port<br>+<br>+ # PL2 override 25W<br>+ register "tdp_pl2_override" = "25"<br>+<br>+ # Send an extra VR mailbox command for the PS4 exit issue<br>+ register "SendVrMbxCmd" = "2"<br>+<br>+ # Lock Down<br>+ register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"<br>+<br>+ device cpu_cluster 0 on<br>+ device lapic 0 on end<br>+ end<br>+ device domain 0 on<br>+ device pci 00.0 on end # Host Bridge<br>+ device pci 02.0 on end # Integrated Graphics Device<br>+ device pci 14.0 on end # USB xHCI<br>+ device pci 14.1 on end # USB xDCI (OTG)<br>+ device pci 14.2 on end # Thermal Subsystem<br>+ device pci 16.0 on end # Management Engine Interface 1<br>+ device pci 16.1 off end # Management Engine Interface 2<br>+ device pci 16.2 off end # Management Engine IDE-R<br>+ device pci 16.3 off end # Management Engine KT Redirection<br>+ device pci 16.4 off end # Management Engine Interface 3<br>+ device pci 17.0 on end # SATA<br>+ device pci 1c.0 on end # PCI Express Port 1<br>+ device pci 1c.1 off end # PCI Express Port 2<br>+ device pci 1c.2 off end # PCI Express Port 3<br>+ device pci 1c.3 off end # PCI Express Port 4<br>+ device pci 1c.4 on end # PCI Express Port 5<br>+ device pci 1c.5 off end # PCI Express Port 6<br>+ device pci 1c.6 off end # PCI Express Port 7<br>+ device pci 1c.7 off end # PCI Express Port 8<br>+ device pci 1d.0 on end # PCI Express Port 9<br>+ device pci 1d.1 off end # PCI Express Port 10<br>+ device pci 1d.2 off end # PCI Express Port 11<br>+ device pci 1d.3 off end # PCI Express Port 12<br>+ device pci 1f.0 on<br>+ chip ec/purism/librem<br>+ device pnp 0c09.0 on end<br>+ end<br>+ end # LPC Interface<br>+ device pci 1f.1 on end # P2SB<br>+ device pci 1f.2 on end # Power Management Controller<br>+ device pci 1f.3 on end # Intel HDA<br>+ device pci 1f.4 on end # SMBus<br>+ device pci 1f.5 on end # PCH SPI<br>+ device pci 1f.6 off end # GbE<br>+ end<br>+end<br>diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/include/variant/gpio.h b/src/mainboard/purism/librem_skl/variants/librem15v3/include/variant/gpio.h<br>new file mode 100644<br>index 0000000..9c22f00<br>--- /dev/null<br>+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/include/variant/gpio.h<br>@@ -0,0 +1,201 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef MAINBOARD_GPIO_H<br>+#define MAINBOARD_GPIO_H<br>+<br>+#include <soc/gpe.h><br>+#include <soc/gpio.h><br>+<br>+#ifndef __ACPI__<br>+<br>+/* Pad configuration in ramstage. */<br>+static const struct pad_config gpio_table[] = {<br>+/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),<br>+/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),<br>+/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),<br>+/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),<br>+/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),<br>+/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),<br>+/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),<br>+/* PIRQA# */ PAD_CFG_NC(GPP_A7),<br>+/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),<br>+/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),<br>+/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),<br>+/* PME# */ PAD_CFG_NC(GPP_A11),<br>+/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),<br>+/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),<br>+/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),<br>+/* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),<br>+/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),<br>+/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),<br>+/* ISH_GP0 */ PAD_CFG_GPI(GPP_A18, NONE, DEEP),<br>+/* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP),<br>+/* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP),<br>+/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),<br>+/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),<br>+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),<br>+<br>+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),<br>+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),<br>+/* VRALERT# */ PAD_CFG_NC(GPP_B2),<br>+/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),<br>+/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),<br>+/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),<br>+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),<br>+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),<br>+/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),<br>+/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),<br>+/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),<br>+/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),<br>+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),<br>+/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),<br>+/* SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),<br>+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),<br>+/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16),<br>+/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),<br>+/* GSPI0_MOSI */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),<br>+/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),<br>+/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),<br>+/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),<br>+/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),<br>+/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),<br>+<br>+/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),<br>+/* SMBDATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),<br>+/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),<br>+/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),<br>+/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),<br>+/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP),<br>+/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */<br>+/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */<br>+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),<br>+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),<br>+/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),<br>+/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),<br>+/* UART1_RXD */ PAD_CFG_NC(GPP_C12),<br>+/* UART1_TXD */ PAD_CFG_NC(GPP_C13),<br>+/* UART1_RTS# */ PAD_CFG_NC(GPP_C14),<br>+/* UART1_CTS# */ PAD_CFG_NC(GPP_C15),<br>+/* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP),<br>+/* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP),<br>+/* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP),<br>+/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),<br>+/* UART2_RXD */ PAD_CFG_NC(GPP_C20),<br>+/* UART2_TXD */ PAD_CFG_NC(GPP_C21),<br>+/* UART2_RTS# */ PAD_CFG_NC(GPP_C22),<br>+/* UART2_CTS# */ PAD_CFG_NC(GPP_C23),<br>+<br>+/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),<br>+/* SPI1_CLK */ PAD_CFG_NC(GPP_D1),<br>+/* SPI1_MISO */ PAD_CFG_NC(GPP_D2),<br>+/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),<br>+/* FASHTRIG */ PAD_CFG_NC(GPP_D4),<br>+/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),<br>+/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),<br>+/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),<br>+/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),<br>+/* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP),<br>+/* ISH_SPI_CLK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),<br>+/* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP),<br>+/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),<br>+/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),<br>+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),<br>+/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),<br>+/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),<br>+/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),<br>+/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),<br>+/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),<br>+/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),<br>+/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),<br>+/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22),<br>+/* I2S_MCLK */ PAD_CFG_NC(GPP_D23),<br>+<br>+/* SATAXPCI0 */ PAD_CFG_NC(GPP_E0),<br>+/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),<br>+/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),<br>+/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),<br>+/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),<br>+/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),<br>+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),<br>+/* CPU_GP1 */ PAD_CFG_NC(GPP_E7),<br>+/* SATALED# */ PAD_CFG_NC(GPP_E8),<br>+/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),<br>+/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),<br>+/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),<br>+/* USB2_OC3# */ PAD_CFG_NC(GPP_E12),<br>+/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),<br>+/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),<br>+/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15),<br>+/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NONE),<br>+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),<br>+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),<br>+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),<br>+/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),<br>+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),<br>+/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),<br>+/* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP),<br>+<br>+/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),<br>+/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),<br>+/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),<br>+/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),<br>+/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),<br>+/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),<br>+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),<br>+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),<br>+/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),<br>+/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),<br>+/* I2C5_SDA */ PAD_CFG_NC(GPP_F10),<br>+/* I2C5_SCL */ PAD_CFG_NC(GPP_F11),<br>+/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),<br>+/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),<br>+/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),<br>+/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),<br>+/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),<br>+/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),<br>+/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),<br>+/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),<br>+/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),<br>+/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),<br>+/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),<br>+/* RSVD */ PAD_CFG_NC(GPP_F23),<br>+<br>+/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),<br>+/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),<br>+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),<br>+/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),<br>+/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),<br>+/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),<br>+/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),<br>+/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1),<br>+<br>+/* BATLOW# */ PAD_CFG_NC(GPD0),<br>+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1),<br>+/* LAN_WAKE# */ PAD_CFG_NC(GPD2),<br>+/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),<br>+/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1),<br>+/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1),<br>+/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1),<br>+/* RSVD */ PAD_CFG_NC(GPD7),<br>+/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1),<br>+/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1),<br>+/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1),<br>+/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),<br>+};<br>+<br>+#endif<br>+<br>+#endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/22048">change 22048</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7c762a34f5b961c908e4a29ec331da4b0dea9986 </div>
<div style="display:none"> Gerrit-Change-Number: 22048 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Youness Alaoui <snifikino@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Matt DeVillier <matt.devillier@gmail.com> </div>