<p>Youness Alaoui would like Matt DeVillier to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/22046">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">purism/librem13v2: migrate from FSP 1.1 to 2.0<br><br>Migrate the Librem13v2 from using FSP 1.1 to<br>the public/GitHub FSP 2.0 Skylake/Kabylake release:<br><br>- select FSP 2.0 in Kconfig<br>- adjust romstage/ramstage functions as required<br>- refactor pei_data functions<br>- remove VR_RING domain from devicetree (unsupported in FSP 2.0)<br>- add SataSpeedLimit parameter to work around power-related issue<br> when operating at SATA 6.0Gbps speed<br><br>TEST: build/boot Librem13v2, observe successful boot, lack of<br>SATA-related errors in dmesg.<br><br>Change-Id: Iedcc18d7279409ccd36deb0001567b0aa5197adf<br>Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm><br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/purism/librem13v2/Kconfig<br>M src/mainboard/purism/librem13v2/devicetree.cb<br>M src/mainboard/purism/librem13v2/pei_data.c<br>A src/mainboard/purism/librem13v2/pei_data.h<br>M src/mainboard/purism/librem13v2/ramstage.c<br>M src/mainboard/purism/librem13v2/romstage.c<br>6 files changed, 80 insertions(+), 67 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/22046/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig<br>index 8522797..5a27955 100644<br>--- a/src/mainboard/purism/librem13v2/Kconfig<br>+++ b/src/mainboard/purism/librem13v2/Kconfig<br>@@ -9,6 +9,7 @@<br> select SOC_INTEL_SKYLAKE<br> # Workaround for EC/KBC IRQ1<br> select SERIRQ_CONTINUOUS_MODE<br>+ select MAINBOARD_USES_FSP2_0<br> <br> config IRQ_SLOT_COUNT<br> int<br>diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb<br>index fd095f2..4caeb01 100644<br>--- a/src/mainboard/purism/librem13v2/devicetree.cb<br>+++ b/src/mainboard/purism/librem13v2/devicetree.cb<br>@@ -36,6 +36,7 @@<br> register "SataPortsEnable[2]" = "1"<br> register "SataPortsDevSlp[0]" = "0"<br> register "SataPortsDevSlp[2]" = "0"<br>+ register "SataSpeedLimit" = "2"<br> register "EnableAzalia" = "1"<br> register "DspEnable" = "0"<br> register "IoBufferOwnership" = "0"<br>@@ -71,20 +72,20 @@<br> register "pirqg_routing" = "PCH_IRQ11"<br> register "pirqh_routing" = "PCH_IRQ11"<br> <br>- # VR Settings Configuration for 5 Domains<br>- #+----------------+-------+-------+-------------+-------------+-------+<br>- #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |<br>- #+----------------+-------+-------+-------------+-------------+-------+<br>- #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |<br>- #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |<br>- #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |<br>- #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |<br>- #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |<br>- #| ImonSlope | 0 | 0 | 0 | 0 | 0 |<br>- #| ImonOffset | 0 | 0 | 0 | 0 | 0 |<br>- #| IccMax | 7A | 34A | 34A | 35A | 35A |<br>- #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |<br>- #+----------------+-------+-------+-------------+-------------+-------+<br>+ # VR Settings Configuration for 4 Domains<br>+ #+----------------+-------+-------+-------------+-------+<br>+ #| Domain/Setting | SA | IA | GT Unsliced | GT |<br>+ #+----------------+-------+-------+-------------+-------+<br>+ #| Psi1Threshold | 20A | 20A | 20A | 20A |<br>+ #| Psi2Threshold | 4A | 5A | 5A | 5A |<br>+ #| Psi3Threshold | 1A | 1A | 1A | 1A |<br>+ #| Psi3Enable | 1 | 1 | 1 | 1 |<br>+ #| Psi4Enable | 1 | 1 | 1 | 1 |<br>+ #| ImonSlope | 0 | 0 | 0 | 0 |<br>+ #| ImonOffset | 0 | 0 | 0 | 0 |<br>+ #| IccMax | 7A | 34A | 35A | 35A |<br>+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |<br>+ #+----------------+-------+-------+-------------+-------+<br> register "domain_vr_config[VR_SYSTEM_AGENT]" = "{<br> .vr_config_enable = 1,<br> .psi1threshold = VR_CFG_AMP(20),<br>@@ -99,19 +100,6 @@<br> }"<br> <br> register "domain_vr_config[VR_IA_CORE]" = "{<br>- .vr_config_enable = 1,<br>- .psi1threshold = VR_CFG_AMP(20),<br>- .psi2threshold = VR_CFG_AMP(5),<br>- .psi3threshold = VR_CFG_AMP(1),<br>- .psi3enable = 1,<br>- .psi4enable = 1,<br>- .imon_slope = 0x0,<br>- .imon_offset = 0x0,<br>- .icc_max = VR_CFG_AMP(34),<br>- .voltage_limit = 1520,<br>- }"<br>-<br>- register "domain_vr_config[VR_RING]" = "{<br> .vr_config_enable = 1,<br> .psi1threshold = VR_CFG_AMP(20),<br> .psi2threshold = VR_CFG_AMP(5),<br>diff --git a/src/mainboard/purism/librem13v2/pei_data.c b/src/mainboard/purism/librem13v2/pei_data.c<br>index 730b730..0be917d 100644<br>--- a/src/mainboard/purism/librem13v2/pei_data.c<br>+++ b/src/mainboard/purism/librem13v2/pei_data.c<br>@@ -3,6 +3,7 @@<br> *<br> * Copyright (C) 2015 Google Inc.<br> * Copyright (C) 2015 Intel Corporation<br>+ * Copyright (C) 2017 Purism SPC.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -18,8 +19,9 @@<br> #include <string.h><br> #include <soc/pei_data.h><br> #include <soc/pei_wrapper.h><br>+#include "pei_data.h"<br> <br>-void mainboard_fill_pei_data(struct pei_data *pei_data)<br>+void mainboard_fill_dq_map_data(void *dq_map_ptr)<br> {<br> /* DQ byte map */<br> const u8 dq_map[2][12] = {<br>@@ -27,21 +29,37 @@<br> 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },<br> { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,<br> 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };<br>+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));<br>+}<br>+<br>+void mainboard_fill_dqs_map_data(void *dqs_map_ptr)<br>+{<br> /* DQS CPU<>DRAM map */<br> const u8 dqs_map[2][8] = {<br> { 0, 1, 3, 2, 4, 5, 6, 7 },<br> { 1, 0, 4, 5, 2, 3, 6, 7 } };<br>+ memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));<br>+}<br> <br>+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)<br>+{<br> /* Rcomp resistor */<br> const u16 RcompResistor[3] = { 121, 81, 100 };<br>+ memcpy(rcomp_ptr, RcompResistor,<br>+ sizeof(RcompResistor));<br>+}<br> <br>+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)<br>+{<br> /* Rcomp target */<br> const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };<br>+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));<br>+}<br> <br>- memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));<br>- memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));<br>- memcpy(pei_data->RcompResistor, RcompResistor,<br>- sizeof(RcompResistor));<br>- memcpy(pei_data->RcompTarget, RcompTarget,<br>- sizeof(RcompTarget));<br>+void mainboard_fill_pei_data(struct pei_data *pei_data)<br>+{<br>+ mainboard_fill_dq_map_data(&pei_data->dq_map);<br>+ mainboard_fill_dqs_map_data(&pei_data->dqs_map);<br>+ mainboard_fill_rcomp_res_data(&pei_data->RcompResistor);<br>+ mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget);<br> }<br>diff --git a/src/mainboard/purism/librem13v2/pei_data.h b/src/mainboard/purism/librem13v2/pei_data.h<br>new file mode 100644<br>index 0000000..320d980<br>--- /dev/null<br>+++ b/src/mainboard/purism/librem13v2/pei_data.h<br>@@ -0,0 +1,24 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Purism SPC.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef _MAINBOARD_PEI_DATA_H_<br>+#define _MAINBOARD_PEI_DATA_H_<br>+<br>+void mainboard_fill_dq_map_data(void *dq_map_ptr);<br>+void mainboard_fill_dqs_map_data(void *dqs_map_ptr);<br>+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);<br>+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);<br>+<br>+#endif<br>diff --git a/src/mainboard/purism/librem13v2/ramstage.c b/src/mainboard/purism/librem13v2/ramstage.c<br>index d22e145..7051714 100644<br>--- a/src/mainboard/purism/librem13v2/ramstage.c<br>+++ b/src/mainboard/purism/librem13v2/ramstage.c<br>@@ -3,6 +3,7 @@<br> *<br> * Copyright (C) 2015 Intel Corporation<br> * Copyright (C) 2015 Google Inc.<br>+ * Copyright (C) 2017 Purism SPC.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -17,7 +18,7 @@<br> #include <soc/ramstage.h><br> #include "gpio.h"<br> <br>-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)<br>+void mainboard_silicon_init_params(FSP_SIL_UPD *params)<br> {<br> /* Configure pads prior to SiliconInit() in case there's any<br> * dependencies during hardware initialization. */<br>diff --git a/src/mainboard/purism/librem13v2/romstage.c b/src/mainboard/purism/librem13v2/romstage.c<br>index fc940e1..48db885 100644<br>--- a/src/mainboard/purism/librem13v2/romstage.c<br>+++ b/src/mainboard/purism/librem13v2/romstage.c<br>@@ -4,6 +4,7 @@<br> * Copyright (C) 2007-2010 coresystems GmbH<br> * Copyright (C) 2015 Google Inc.<br> * Copyright (C) 2015 Intel Corporation<br>+ * Copyright (C) 2017 Purism SPC.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -17,49 +18,29 @@<br> <br> #include <string.h><br> #include <assert.h><br>-#include <arch/acpi.h><br>-#include <soc/pei_data.h><br>-#include <soc/pei_wrapper.h><br> #include <soc/romstage.h><br> #include <spd_bin.h><br>+#include "pei_data.h"<br> <br>-void mainboard_romstage_entry(struct romstage_params *params)<br>+void mainboard_memory_init_params(FSPM_UPD *mupd)<br> {<br>- /* Fill out PEI DATA */<br>- mainboard_fill_pei_data(params->pei_data);<br>- /* Initliaze memory */<br>- romstage_common(params);<br>-}<br>-<br>-void mainboard_memory_init_params(struct romstage_params *params,<br>- MEMORY_INIT_UPD *memory_params)<br>-{<br>+ FSP_M_CONFIG *mem_cfg;<br> struct spd_block blk = {<br> .addr_map = { 0x50 },<br> };<br>+<br>+ mem_cfg = &mupd->FspmConfig;<br> <br> get_spd_smbus(&blk);<br> dump_spd_info(&blk);<br> assert(blk.spd_array[0][0] != 0);<br> <br>- memory_params->MemorySpdDataLen = blk.len;<br>- memory_params->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];<br>- memory_params->MemorySpdPtr01 = 0;<br>- memory_params->MemorySpdPtr10 = 0;<br>- memory_params->MemorySpdPtr11 = 0;<br>+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);<br>+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);<br>+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);<br>+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);<br> <br>- memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],<br>- sizeof(params->pei_data->dq_map[0]));<br>- memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],<br>- sizeof(params->pei_data->dq_map[1]));<br>- memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],<br>- sizeof(params->pei_data->dqs_map[0]));<br>- memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],<br>- sizeof(params->pei_data->dqs_map[1]));<br>- memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,<br>- sizeof(params->pei_data->RcompResistor));<br>- memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,<br>- sizeof(params->pei_data->RcompTarget));<br>- memory_params->DqPinsInterleaved = TRUE;<br>-<br>+ mem_cfg->DqPinsInterleaved = TRUE;<br>+ mem_cfg->MemorySpdDataLen = blk.len;<br>+ mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/22046">change 22046</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22046"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iedcc18d7279409ccd36deb0001567b0aa5197adf </div>
<div style="display:none"> Gerrit-Change-Number: 22046 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Youness Alaoui <snifikino@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Matt DeVillier <matt.devillier@gmail.com> </div>