<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22026">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">DMP Vortex86ex board & chip: Remove - using LATE_CBMEM_INIT<br><br>All boards and chips that are still using LATE_CBMEM_INIT are being<br>removed as previously discussed.<br><br>If these boards and chips are updated to not use LATE_CBMEM_INIT, they<br>can be restored to the active codebase from the 4.8 branch.<br><br>chips:<br>soc/dmp/vortex86ex<br><br>Mainboards:<br>mainboard/dmp/vortex86ex<br><br>Change-Id: Iee7b6005cc2964b2346aaf4dbd9b2d2112b7403f<br>Signed-off-by: Martin Roth <gaumless@gmail.com><br>---<br>M src/cpu/Makefile.inc<br>D src/cpu/dmp/Kconfig<br>D src/cpu/dmp/Makefile.inc<br>D src/cpu/dmp/dmp_post_code.h<br>D src/cpu/dmp/vortex86ex/Kconfig<br>D src/cpu/dmp/vortex86ex/Makefile.inc<br>D src/cpu/dmp/vortex86ex/biosdata.S<br>D src/cpu/dmp/vortex86ex/biosdata.ld<br>D src/cpu/dmp/vortex86ex/biosdata_ex.S<br>D src/cpu/dmp/vortex86ex/biosdata_ex.ld<br>D src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc<br>D src/mainboard/dmp/Kconfig<br>D src/mainboard/dmp/Kconfig.name<br>D src/mainboard/dmp/vortex86ex/Kconfig<br>D src/mainboard/dmp/vortex86ex/Kconfig.name<br>D src/mainboard/dmp/vortex86ex/board_info.txt<br>D src/mainboard/dmp/vortex86ex/devicetree.cb<br>D src/mainboard/dmp/vortex86ex/hda_verb.c<br>D src/mainboard/dmp/vortex86ex/irq_tables.c<br>D src/mainboard/dmp/vortex86ex/romstage.c<br>D src/soc/dmp/vortex86ex/Kconfig<br>D src/soc/dmp/vortex86ex/Makefile.inc<br>D src/soc/dmp/vortex86ex/audio.c<br>D src/soc/dmp/vortex86ex/chip.h<br>D src/soc/dmp/vortex86ex/hard_reset.c<br>D src/soc/dmp/vortex86ex/ide_sd_sata.c<br>D src/soc/dmp/vortex86ex/northbridge.c<br>D src/soc/dmp/vortex86ex/northbridge.h<br>D src/soc/dmp/vortex86ex/raminit.c<br>D src/soc/dmp/vortex86ex/southbridge.c<br>D src/soc/dmp/vortex86ex/southbridge.h<br>D src/soc/dmp/vortex86ex/xgi_oprom.c<br>32 files changed, 0 insertions(+), 4,456 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/22026/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc<br>index f74e354..174baf5 100644<br>--- a/src/cpu/Makefile.inc<br>+++ b/src/cpu/Makefile.inc<br>@@ -3,7 +3,6 @@<br> ################################################################################<br> subdirs-y += allwinner<br> subdirs-y += amd<br>-subdirs-y += dmp<br> subdirs-y += armltd<br> subdirs-y += imgtec<br> subdirs-y += intel<br>diff --git a/src/cpu/dmp/Kconfig b/src/cpu/dmp/Kconfig<br>deleted file mode 100644<br>index aabaf05..0000000<br>--- a/src/cpu/dmp/Kconfig<br>+++ /dev/null<br>@@ -1,16 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2013 DMP Electronics Inc.<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-source src/cpu/dmp/vortex86ex/Kconfig<br>diff --git a/src/cpu/dmp/Makefile.inc b/src/cpu/dmp/Makefile.inc<br>deleted file mode 100644<br>index a5fb5b6..0000000<br>--- a/src/cpu/dmp/Makefile.inc<br>+++ /dev/null<br>@@ -1,16 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2013 DMP Electronics Inc.<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-subdirs-$(CONFIG_CPU_DMP_VORTEX86EX) += vortex86ex<br>diff --git a/src/cpu/dmp/dmp_post_code.h b/src/cpu/dmp/dmp_post_code.h<br>deleted file mode 100644<br>index 4a61c9a..0000000<br>--- a/src/cpu/dmp/dmp_post_code.h<br>+++ /dev/null<br>@@ -1,30 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef DMP_POST_CODE_H<br>-#define DMP_POST_CODE_H<br>-<br>-/* DMP Vortex86EX specific POST codes */<br>-<br>-#define POST_DMP_KBD_FW_UPLOAD 0x06<br>-#define POST_DMP_KBD_CHK_READY 0x07<br>-#define POST_DMP_KBD_IS_READY 0x08<br>-#define POST_DMP_KBD_IS_BAD 0x09<br>-#define POST_DMP_KBD_FW_VERIFY_ERR 0x82<br>-#define POST_DMP_ID_ERR 0x85<br>-#define POST_DMP_DRAM_TEST_ERR 0x86<br>-#define POST_DMP_DRAM_SIZING_ERR 0x77<br>-<br>-#endif /* DMP_POST_CODE_H*/<br>diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig<br>deleted file mode 100644<br>index 1af7ec4..0000000<br>--- a/src/cpu/dmp/vortex86ex/Kconfig<br>+++ /dev/null<br>@@ -1,76 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2013 DMP Electronics Inc.<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-config CPU_DMP_VORTEX86EX<br>- bool<br>-<br>-if CPU_DMP_VORTEX86EX<br>-<br>-config CPU_SPECIFIC_OPTIONS<br>- def_bool y<br>- select ARCH_BOOTBLOCK_X86_32<br>- select ARCH_VERSTAGE_X86_32<br>- select ARCH_ROMSTAGE_X86_32<br>- select ARCH_RAMSTAGE_X86_32<br>- select UDELAY_TSC<br>-<br>-# ROM Strap PLL config setting :<br>-<br>-choice<br>- prompt "ROM Strap PLL config"<br>- default PLL_300_300_33<br>-<br>-config PLL_200_200_33<br>- bool "CPU=200Mhz/DRAM=200Mhz/PCI=33Mhz"<br>-<br>-config PLL_300_300_33<br>- bool "CPU=300Mhz/DRAM=300Mhz/PCI=33Mhz"<br>-<br>-config PLL_300_300_100<br>- bool "CPU=300Mhz/DRAM=300Mhz/PCI=100Mhz"<br>-<br>-config PLL_400_200_33<br>- bool "CPU=400Mhz/DRAM=200Mhz/PCI=33Mhz"<br>-<br>-config PLL_400_200_100<br>- bool "CPU=400Mhz/DRAM=200Mhz/PCI=100Mhz"<br>-<br>-config PLL_400_400_33<br>- bool "CPU=400Mhz/DRAM=400Mhz/PCI=33Mhz"<br>-<br>-config PLL_500_250_33<br>- bool "CPU=500Mhz/DRAM=250Mhz/PCI=33Mhz"<br>-<br>-config PLL_500_500_33<br>- bool "CPU=500Mhz/DRAM=500Mhz/PCI=33Mhz"<br>-<br>-config PLL_400_300_33<br>- bool "CPU=400Mhz/DRAM=300Mhz/PCI=33Mhz"<br>-<br>-config PLL_400_300_100<br>- bool "CPU=400Mhz/DRAM=300Mhz/PCI=100Mhz"<br>-<br>-config PLL_444_333_33<br>- bool "CPU=444Mhz/DRAM=333Mhz/PCI=33Mhz"<br>-<br>-config PLL_466_350_33<br>- bool "CPU=466Mhz/DRAM=350Mhz/PCI=33Mhz"<br>-<br>-config PLL_500_375_33<br>- bool "CPU=500Mhz/DRAM=375Mhz/PCI=33Mhz"<br>-<br>-endchoice<br>-<br>-endif<br>diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc<br>deleted file mode 100644<br>index 6b4d0ba..0000000<br>--- a/src/cpu/dmp/vortex86ex/Makefile.inc<br>+++ /dev/null<br>@@ -1,27 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2013 DMP Electronics Inc.<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-subdirs-y += ../../x86/tsc<br>-subdirs-y += ../../x86/mtrr<br>-subdirs-y += ../../x86/lapic<br>-subdirs-y += ../../x86/cache<br>-subdirs-y += ../../x86/smm<br>-<br>-bootblock-y += biosdata.ld<br>-bootblock-y += biosdata_ex.ld<br>-bootblock-y += biosdata.S<br>-bootblock-y += biosdata_ex.S<br>-<br>-ROMCCFLAGS := -mcpu=i386 -O2<br>diff --git a/src/cpu/dmp/vortex86ex/biosdata.S b/src/cpu/dmp/vortex86ex/biosdata.S<br>deleted file mode 100644<br>index 0441f4f..0000000<br>--- a/src/cpu/dmp/vortex86ex/biosdata.S<br>+++ /dev/null<br>@@ -1,80 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>- .section ".dmp_reserved", "a", @progbits<br>-<br>- .skip 0x3c000 - 0x3bc00, 0xff<br>-<br>-.previous<br>-<br>- .section ".dmp_kbd_fw_part2", "a", @progbits<br>-<br>- .skip 0x3d000 - 0x3c000, 0xff<br>-<br>-.previous<br>-<br>- .section ".dmp_mtbf_low_cnt", "a", @progbits<br>-<br>- .skip 0x3e000 - 0x3d000, 0xff<br>-<br>-.previous<br>-<br>- .section ".dmp_kbd_fw_part1", "a", @progbits<br>-<br>- #include "dmp_kbd_fw_part1.inc"<br>-<br>-.previous<br>-<br>- .section ".dmp_spi_flash_disk_driver", "a", @progbits<br>-<br>- .skip 0x3f800 - 0x3f000, 0xff<br>-<br>-.previous<br>-<br>- .section ".dmp_frontdoor", "a", @progbits<br>-<br>- .skip 0x3fd00 - 0x3f800, 0xff<br>-<br>-.previous<br>-<br>- .section ".dmp_isoinfo", "a", @progbits<br>-<br>- .skip 26 * 16, 0xff<br>-<br>-.previous<br>-<br>- .section ".dmp_isodata_checksum", "a", @progbits<br>-<br>- .skip 8, 0xff<br>-<br>-.previous<br>-<br>- .section ".dmp_mac", "a", @progbits<br>-<br>- .skip 6, 0xff<br>-<br>-.previous<br>-<br>- .section ".dmp_mtbf_limit", "a", @progbits<br>-<br>- .skip 3, 0xff<br>-<br>-.previous<br>-<br>- .section ".dmp_isodata", "a", @progbits<br>-<br>- .skip 32, 0xff<br>-<br>-.previous<br>diff --git a/src/cpu/dmp/vortex86ex/biosdata.ld b/src/cpu/dmp/vortex86ex/biosdata.ld<br>deleted file mode 100644<br>index 8d5f020..0000000<br>--- a/src/cpu/dmp/vortex86ex/biosdata.ld<br>+++ /dev/null<br>@@ -1,80 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-SECTIONS {<br>-<br>- /* Vortex86 ROM fixed data areas used range is too big, we need<br>- * to move bootblock from default address to another place,<br>- * otherwise .dmp_frontdoor section can't be included.<br>- * Address before ..fbc00 is available.<br>- */<br>- ROMLOC_MIN = 0xffffbc00 - (_erom - _rom + 16) -<br>- (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);<br>-<br>- . = 0xffffbc00;<br>- .dmp_reserved (.): {<br>- KEEP(*(.dmp_reserved))<br>- }<br>-<br>- . = 0xffffc000;<br>- .dmp_kbd_fw_part2 (.): {<br>- KEEP(*(.dmp_kbd_fw_part2))<br>- }<br>-<br>- . = 0xffffd000;<br>- .dmp_mtbf_low_cnt (.): {<br>- KEEP(*(.dmp_mtbf_low_cnt))<br>- }<br>-<br>- . = 0xffffe000;<br>- .dmp_kbd_fw_part1 (.): {<br>- KEEP(*(.dmp_kbd_fw_part1))<br>- }<br>-<br>- . = 0xfffff000;<br>- .dmp_spi_flash_disk_driver (.): {<br>- KEEP(*(.dmp_spi_flash_disk_driver))<br>- }<br>-<br>- . = 0xfffff800;<br>- .dmp_frontdoor (.): {<br>- KEEP(*(.dmp_frontdoor))<br>- }<br>-<br>- . = 0xfffffe00;<br>- .dmp_isoinfo (.): {<br>- KEEP(*(.dmp_isoinfo))<br>- }<br>-<br>- . = 0xffffffa0;<br>- .dmp_isodata_checksum (.): {<br>- KEEP(*(.dmp_isodata_checksum))<br>- }<br>-<br>- . = 0xffffffb0;<br>- .dmp_mac (.): {<br>- KEEP(*(.dmp_mac))<br>- }<br>-<br>- . = 0xffffffb8;<br>- .dmp_mtbf_limit (.): {<br>- KEEP(*(.dmp_mtbf_limit))<br>- }<br>-<br>- . = 0xffffffc0;<br>- .dmp_isodata (.): {<br>- KEEP(*(.dmp_isodata))<br>- }<br>-}<br>diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.S b/src/cpu/dmp/vortex86ex/biosdata_ex.S<br>deleted file mode 100644<br>index 6686bb7..0000000<br>--- a/src/cpu/dmp/vortex86ex/biosdata_ex.S<br>+++ /dev/null<br>@@ -1,170 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/*<br>-PLL Freq = 25 * NS /(MS * 2^RS)<br>-CPU Freq = PLL/(CPU_DIV+2)<br>-DRAM Freq = PLL/2(DRAM_DIV+1)<br>-<br>-DDR3<br>-CPU/DRAM/PCI B6 B7 BB BC BD BF<br>-200/200/33 30 03 0F 02 8F 07<br>-300/300/33 48 03 0F 02 1F 07<br>-300/300/33 48 03 0F 3A DF 07 ; write leveling disable, CPU bypass disable<br>-300/300/33 48 03 0F 22 3F 07 ; CPU bypass disable<br>-300/300/100 48 03 23 02 7F 07<br>-400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing<br>-400/200/100 60 43 23 02 4F 07<br>-400/400/33 60 03 0F 02 BF 09<br>-500/250/33 50 42 0F 02 DF 07<br>-500/500/33 78 03 0F 02 4F 09<br>-400/300/33 90 53 0F 02 3F 07<br>-400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable<br>-400/300/100 90 53 23 02 9F 07<br>-444/333/33 A0 53 0F 02 5F 08<br>-466/350/33 A8 53 0F 02 DF 09<br>-500/375/33 B4 53 0F 02 AF 09<br>-*/<br>-<br>-#if IS_ENABLED(CONFIG_PLL_200_200_33)<br>- // 200/200/33 30 03 0F 02 8F 07<br>- byte_fffb6 = 0x30<br>- byte_fffb7 = 0x03<br>- byte_fffbb = 0x0f<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x07<br>-#elif IS_ENABLED(CONFIG_PLL_300_300_33)<br>- // 300/300/33 48 03 0F 02 1F 07<br>- byte_fffb6 = 0x48<br>- byte_fffb7 = 0x03<br>- byte_fffbb = 0x0f<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x07<br>-#elif IS_ENABLED(CONFIG_PLL_300_300_100)<br>- // 300/300/100 48 03 23 02 7F 07<br>- byte_fffb6 = 0x48<br>- byte_fffb7 = 0x03<br>- byte_fffbb = 0x23<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x07<br>-#elif IS_ENABLED(CONFIG_PLL_400_200_33)<br>- // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing<br>- byte_fffb6 = 0x60<br>- byte_fffb7 = 0x43<br>- byte_fffbb = 0x0f<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x07<br>-#elif IS_ENABLED(CONFIG_PLL_400_200_100)<br>- // 400/200/100 60 43 23 02 4F 07<br>- byte_fffb6 = 0x60<br>- byte_fffb7 = 0x43<br>- byte_fffbb = 0x23<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x07<br>-#elif IS_ENABLED(CONFIG_PLL_400_400_33)<br>- // 400/400/33 60 03 0F 02 BF 09<br>- byte_fffb6 = 0x60<br>- byte_fffb7 = 0x03<br>- byte_fffbb = 0x0f<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x09<br>-#elif IS_ENABLED(CONFIG_PLL_500_250_33)<br>- // 500/250/33 50 42 0F 02 DF 07<br>- byte_fffb6 = 0x50<br>- byte_fffb7 = 0x42<br>- byte_fffbb = 0x0f<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x07<br>-#elif IS_ENABLED(CONFIG_PLL_500_500_33)<br>- // 500/500/33 78 03 0F 02 4F 09<br>- byte_fffb6 = 0x78<br>- byte_fffb7 = 0x03<br>- byte_fffbb = 0x0f<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x09<br>-#elif IS_ENABLED(CONFIG_PLL_400_300_33)<br>- // 400/300/33 90 53 0F 02 3F 07<br>- byte_fffb6 = 0x90<br>- byte_fffb7 = 0x53<br>- byte_fffbb = 0x0f<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x07<br>-#elif IS_ENABLED(CONFIG_PLL_400_300_100)<br>- // 400/300/100 90 53 23 02 9F 07<br>- byte_fffb6 = 0x90<br>- byte_fffb7 = 0x53<br>- byte_fffbb = 0x23<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x07<br>-#elif IS_ENABLED(CONFIG_PLL_444_333_33)<br>- // 444/333/33 A0 53 0F 02 5F 08<br>- byte_fffb6 = 0xa0<br>- byte_fffb7 = 0x53<br>- byte_fffbb = 0x0f<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x08<br>-#elif IS_ENABLED(CONFIG_PLL_466_350_33)<br>- // 466/350/33 A8 53 0F 02 DF 09<br>- byte_fffb6 = 0xa8<br>- byte_fffb7 = 0x53<br>- byte_fffbb = 0x0f<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x09<br>-#elif IS_ENABLED(CONFIG_PLL_500_375_33)<br>- // 500/375/33 B4 53 0F 02 AF 09<br>- byte_fffb6 = 0xb4<br>- byte_fffb7 = 0x53<br>- byte_fffbb = 0x0f<br>- byte_fffbc = 0x02<br>- byte_fffbe = 0xff<br>- byte_fffbf = 0x09<br>-#else<br>- #error Error Strap PLL config.<br>-#endif<br>-<br>-tmp_sum = byte_fffb6 + byte_fffb7 + byte_fffbb + byte_fffbc<br>-pll_checksum = ((tmp_sum >> 8) & 0x3) + ((tmp_sum >> 4) & 0x0f) + (tmp_sum & 0x0f)<br>-<br>-byte_fffbd = ((pll_checksum & 0x0f) << 4) | 0x0f<br>-<br>- .section ".a9123_crossbar_config", "a", @progbits<br>-<br>- .skip 0x3fdf0 - 0x3fd00, 0xff<br>-<br>-.previous<br>-<br>- .section ".a9123_strap_1", "a", @progbits<br>-<br>- .byte byte_fffb6, byte_fffb7<br>-<br>-.previous<br>-<br>- .section ".a9123_strap_2", "a", @progbits<br>-<br>- .byte byte_fffbb, byte_fffbc, byte_fffbd, byte_fffbe, byte_fffbf<br>-<br>-.previous<br>diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.ld b/src/cpu/dmp/vortex86ex/biosdata_ex.ld<br>deleted file mode 100644<br>index 04e23c3..0000000<br>--- a/src/cpu/dmp/vortex86ex/biosdata_ex.ld<br>+++ /dev/null<br>@@ -1,31 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-SECTIONS {<br>- . = 0xfffffd00;<br>- .a9123_crossbar_config (.): {<br>- KEEP(*(.a9123_crossbar_config))<br>- }<br>-<br>- . = 0xffffffb6;<br>- .a9123_strap_1 (.): {<br>- KEEP(*(.a9123_strap_1))<br>- }<br>-<br>- . = 0xffffffbb;<br>- .a9123_strap_2 (.): {<br>- KEEP(*(.a9123_strap_2))<br>- }<br>-}<br>diff --git a/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc b/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc<br>deleted file mode 100644<br>index 302b0cb..0000000<br>--- a/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc<br>+++ /dev/null<br>@@ -1,527 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>- .byte 0x02, 0x04, 0xa3, 0x02, 0x0a, 0xfb, 0xef, 0x75<br>- .byte 0xf0, 0x03, 0xa4, 0xff, 0xae, 0x07, 0x1f, 0xee<br>- .byte 0x70, 0xfa, 0x22, 0x02, 0x0a, 0xd5, 0x12, 0x09<br>- .byte 0x5e, 0x7f, 0x30, 0x12, 0x05, 0xfb, 0x90, 0xe0<br>- .byte 0x00, 0x74, 0x16, 0xf0, 0x12, 0x0d, 0xda, 0xc2<br>- .byte 0x92, 0xc2, 0x93, 0xc2, 0x90, 0xd2, 0x91, 0xd2<br>- .byte 0xb8, 0xd2, 0xba, 0xd2, 0x88, 0xd2, 0xa8, 0xd2<br>- .byte 0x8a, 0xd2, 0xaa, 0x7d, 0x44, 0xe4, 0xff, 0x12<br>- .byte 0x0e, 0x3a, 0x7d, 0x4d, 0x0f, 0x12, 0x0e, 0x3a<br>- .byte 0x7d, 0x26, 0x0f, 0x12, 0x0e, 0x3a, 0x7d, 0x50<br>- .byte 0x0f, 0x12, 0x0e, 0x3a, 0x12, 0x0e, 0x59, 0xd2<br>- .byte 0xaf, 0x7f, 0xb1, 0x12, 0x0e, 0xf5, 0x90, 0x0f<br>- .byte 0xfe, 0xe4, 0x93, 0xff, 0xb4, 0x55, 0x0a, 0xa3<br>- .byte 0xe4, 0x93, 0xb4, 0xaa, 0x04, 0xd2, 0x08, 0x80<br>- .byte 0x10, 0xef, 0xb4, 0x12, 0x0c, 0x90, 0x0f, 0xff<br>- .byte 0xe4, 0x93, 0xb4, 0x34, 0x04, 0xc2, 0x08, 0xc2<br>- .byte 0x12, 0x12, 0x03, 0x6c, 0x12, 0x0d, 0xa6, 0x12<br>- .byte 0x01, 0x08, 0x30, 0x01, 0x27, 0x30, 0x12, 0x1f<br>- .byte 0x20, 0x00, 0x1c, 0x30, 0x11, 0x19, 0x12, 0x0d<br>- .byte 0x25, 0x12, 0x09, 0xc4, 0x30, 0x08, 0x05, 0xc2<br>- .byte 0x1a, 0x12, 0x0a, 0x26, 0x12, 0x0d, 0x92, 0xd2<br>- .byte 0x00, 0x12, 0x0d, 0x3b, 0x12, 0x07, 0xc2, 0x12<br>- .byte 0x0d, 0xda, 0xc2, 0x01, 0x12, 0x03, 0x6c, 0x12<br>- .byte 0x07, 0x2e, 0x30, 0x12, 0xc4, 0x30, 0x00, 0xc1<br>- .byte 0x90, 0xd0, 0x00, 0xe0, 0x30, 0xe0, 0xba, 0xc2<br>- .byte 0xaf, 0x12, 0x0e, 0x07, 0x50, 0x0e, 0x12, 0x0e<br>- .byte 0xb6, 0x12, 0x0e, 0xbc, 0xd2, 0x1a, 0x12, 0x0a<br>- .byte 0x26, 0x12, 0x0d, 0x3b, 0xd2, 0xaf, 0x80, 0xa1<br>- .byte 0xae, 0x03, 0xab, 0x05, 0x53, 0x1a, 0xef, 0x90<br>- .byte 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0xad, 0x07, 0x8e<br>- .byte 0x33, 0x7f, 0x20, 0x12, 0x0d, 0x51, 0x43, 0x1a<br>- .byte 0x10, 0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0x22<br>- .byte 0xda, 0x7e, 0x10, 0x09, 0x14, 0x12, 0x0d, 0xa6<br>- .byte 0x90, 0xe0, 0x00, 0xe0, 0xff, 0x20, 0xe1, 0x03<br>- .byte 0x02, 0x02, 0xc8, 0xc2, 0xa8, 0xc2, 0xaa, 0x20<br>- .byte 0x04, 0x03, 0x30, 0x07, 0x05, 0xd2, 0xa8, 0xd2<br>- .byte 0xaa, 0x22, 0xef, 0xa2, 0xe3, 0x92, 0x1c, 0x90<br>- .byte 0xf0, 0x00, 0xe0, 0xf5, 0x2c, 0x12, 0x0e, 0x2f<br>- .byte 0xd2, 0xa8, 0xd2, 0xaa, 0x30, 0x1c, 0x03, 0x02<br>- .byte 0x01, 0xee, 0xc2, 0x1d, 0xc2, 0x1e, 0x20, 0x17<br>- .byte 0x03, 0x02, 0x01, 0xd4, 0xe5, 0x18, 0x24, 0xe1<br>- .byte 0x60, 0x3b, 0x24, 0x54, 0x70, 0x03, 0x02, 0x01<br>- .byte 0xd0, 0x24, 0xfa, 0x60, 0x14, 0x14, 0x60, 0x1e<br>- .byte 0x14, 0x60, 0x1f, 0x14, 0x60, 0x23, 0x24, 0x74<br>- .byte 0x70, 0x6c, 0xaf, 0x2c, 0x12, 0x05, 0xfb, 0x80<br>- .byte 0x67, 0xe5, 0x2c, 0x30, 0xe1, 0x04, 0xd2, 0x90<br>- .byte 0x80, 0x5e, 0xc2, 0x90, 0x80, 0x5a, 0xc2, 0x1f<br>- .byte 0x80, 0x02, 0xd2, 0x1f, 0x85, 0x2c, 0x2f, 0x80<br>- .byte 0x46, 0xd2, 0x1e, 0x80, 0x4b, 0xe5, 0x2c, 0x70<br>- .byte 0x1a, 0x12, 0x0c, 0xed, 0x12, 0x08, 0xf2, 0x85<br>- .byte 0x38, 0x12, 0x85, 0x39, 0x13, 0x85, 0x3a, 0x14<br>- .byte 0x85, 0x09, 0x15, 0x85, 0x0a, 0x16, 0x85, 0x0b<br>- .byte 0x17, 0x80, 0x2d, 0xe5, 0x2c, 0xc3, 0x94, 0x01<br>- .byte 0x40, 0x13, 0xe5, 0x2c, 0xd3, 0x94, 0x06, 0x50<br>- .byte 0x0c, 0xc2, 0x1f, 0x74, 0x11, 0x25, 0x2c, 0xf8<br>- .byte 0xe6, 0xf5, 0x2f, 0x80, 0x0a, 0xe5, 0x2c, 0xb4<br>- .byte 0x07, 0x0e, 0xc2, 0x1f, 0x85, 0x3b, 0x2f, 0xd2<br>- .byte 0x20, 0x12, 0x0d, 0xb8, 0x80, 0x02, 0xd2, 0x1d<br>- .byte 0xc2, 0x17, 0x80, 0x02, 0xd2, 0x1d, 0x30, 0x1d<br>- .byte 0x07, 0xaf, 0x2c, 0x12, 0x05, 0x2f, 0x80, 0x08<br>- .byte 0x30, 0x1e, 0x05, 0xaf, 0x2c, 0x12, 0x05, 0x97<br>- .byte 0x12, 0x0e, 0x85, 0x02, 0x02, 0xc2, 0xc2, 0x1d<br>- .byte 0xe5, 0x2c, 0x12, 0x0b, 0x21, 0x02, 0xb7, 0x1f<br>- .byte 0x02, 0x35, 0x20, 0x02, 0xb7, 0x60, 0x02, 0x56<br>- .byte 0xa7, 0x02, 0x5d, 0xa8, 0x02, 0x64, 0xa9, 0x02<br>- .byte 0x48, 0xaa, 0x02, 0x64, 0xab, 0x02, 0x6d, 0xad<br>- .byte 0x02, 0x74, 0xae, 0x02, 0x41, 0xc0, 0x02, 0xb7<br>- .byte 0xcb, 0x02, 0x7b, 0xd0, 0x02, 0xb7, 0xd1, 0x02<br>- .byte 0xb7, 0xd2, 0x02, 0xb7, 0xd3, 0x02, 0xb7, 0xd4<br>- .byte 0x02, 0x98, 0xdd, 0x02, 0x8d, 0xdf, 0x02, 0xa8<br>- .byte 0xfe, 0x00, 0x00, 0x02, 0xb5, 0x12, 0x0a, 0x83<br>- .byte 0x8f, 0x2d, 0xc2, 0x1f, 0x85, 0x2d, 0x2f, 0x80<br>- .byte 0x28, 0xc2, 0x1f, 0x75, 0x2f, 0xff, 0x80, 0x21<br>- .byte 0x7f, 0x30, 0x12, 0x05, 0xfb, 0xc2, 0x1f, 0x75<br>- .byte 0x2f, 0x55, 0xc2, 0x20, 0x80, 0x4b, 0x12, 0x0e<br>- .byte 0x8d, 0xd2, 0x1d, 0x80, 0x5a, 0x12, 0x0e, 0xe6<br>- .byte 0xd2, 0x1d, 0x80, 0x53, 0xc2, 0x1f, 0xe4, 0xf5<br>- .byte 0x2f, 0xd2, 0x20, 0x80, 0x34, 0x12, 0x0e, 0x94<br>- .byte 0xd2, 0x1d, 0x80, 0x43, 0x12, 0x0e, 0xf0, 0xd2<br>- .byte 0x1d, 0x80, 0x3c, 0x75, 0x2e, 0x01, 0x30, 0x90<br>- .byte 0x03, 0x43, 0x2e, 0x02, 0xc2, 0x1f, 0x85, 0x2e<br>- .byte 0x2f, 0xd2, 0x20, 0x80, 0x14, 0xd2, 0x90, 0xc2<br>- .byte 0x1f, 0x85, 0x0f, 0x2f, 0xd2, 0x20, 0x80, 0x09<br>- .byte 0xc2, 0x90, 0xc2, 0x1f, 0x85, 0x0f, 0x2f, 0xd2<br>- .byte 0x20, 0x12, 0x0d, 0xb8, 0xd2, 0x1d, 0x80, 0x0f<br>- .byte 0xc2, 0x91, 0x7f, 0x05, 0x12, 0x00, 0x06, 0xd2<br>- .byte 0x91, 0xd2, 0x1d, 0x80, 0x02, 0xd2, 0x1d, 0x30<br>- .byte 0x1d, 0x03, 0x12, 0x0e, 0x85, 0xd2, 0x17, 0x85<br>- .byte 0x2c, 0x18, 0x20, 0x01, 0x03, 0x12, 0x0d, 0xda<br>- .byte 0x22, 0x44, 0x4d, 0x26, 0x50, 0x00, 0xff, 0x43<br>- .byte 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58, 0x64, 0x44<br>- .byte 0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59, 0x65, 0x38<br>- .byte 0x2a, 0x70, 0x1d, 0x10, 0x02, 0x5a, 0x66, 0x71<br>- .byte 0x2c, 0x1f, 0x1e, 0x11, 0x03, 0x5b, 0x67, 0x2e<br>- .byte 0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c, 0x68, 0x39<br>- .byte 0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d, 0x69, 0x31<br>- .byte 0x30, 0x23, 0x22, 0x15, 0x07, 0x5e, 0x6a, 0x72<br>- .byte 0x32, 0x24, 0x16, 0x08, 0x09, 0x5f, 0x6b, 0x33<br>- .byte 0x25, 0x17, 0x18, 0x0b, 0x0a, 0x60, 0x6c, 0x34<br>- .byte 0x35, 0x26, 0x27, 0x19, 0x0c, 0x61, 0x6d, 0x73<br>- .byte 0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e, 0x3a, 0x36<br>- .byte 0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76, 0x55, 0x56<br>- .byte 0x77, 0x78, 0x79, 0x7a, 0x0e, 0x7b, 0x7c, 0x4f<br>- .byte 0x7d, 0x4b, 0x47, 0x7e, 0x7f, 0x6f, 0x52, 0x53<br>- .byte 0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45, 0x57, 0x4e<br>- .byte 0x51, 0x4a, 0x37, 0x49, 0x46, 0x54, 0x00, 0x00<br>- .byte 0x00, 0x41, 0x54, 0x00, 0x01, 0x01, 0x02, 0x01<br>- .byte 0x02, 0x02, 0x03, 0x01, 0x02, 0x02, 0x03, 0x02<br>- .byte 0x03, 0x03, 0x04, 0x14, 0x23, 0x14, 0x3a, 0x14<br>- .byte 0x4d, 0x42, 0x32, 0x23, 0x20, 0x0c, 0x03, 0x02<br>- .byte 0x04, 0x08, 0xc2, 0x1a, 0xc2, 0x1b, 0xe5, 0x10<br>- .byte 0x30, 0xe7, 0x57, 0xe5, 0x11, 0xae, 0x10, 0x78<br>- .byte 0x06, 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, 0xf9<br>- .byte 0xf5, 0x26, 0xff, 0x12, 0x0d, 0xca, 0x8f, 0x27<br>- .byte 0xe5, 0x10, 0xc4, 0x13, 0x13, 0x54, 0x03, 0xff<br>- .byte 0xe5, 0x27, 0x54, 0x01, 0xb5, 0x07, 0x05, 0xe4<br>- .byte 0x7f, 0x01, 0x80, 0x02, 0x7f, 0x00, 0xef, 0x30<br>- .byte 0xe0, 0x04, 0xd2, 0x1b, 0x80, 0x24, 0x20, 0x13<br>- .byte 0x1f, 0xaf, 0x26, 0x12, 0x07, 0x79, 0xaf, 0x26<br>- .byte 0x12, 0x09, 0xf6, 0x8e, 0x28, 0x8f, 0x29, 0xe5<br>- .byte 0x29, 0xf4, 0x70, 0x03, 0xe5, 0x28, 0xf4, 0x60<br>- .byte 0x09, 0x85, 0x29, 0x26, 0xd2, 0x1a, 0x80, 0x02<br>- .byte 0xd2, 0x1a, 0x30, 0x1a, 0x1b, 0xc2, 0x27, 0x7f<br>- .byte 0x07, 0x12, 0x0b, 0x6c, 0xc2, 0x27, 0x7f, 0x06<br>- .byte 0x12, 0x0b, 0x6c, 0xa2, 0x13, 0x92, 0x25, 0x85<br>- .byte 0x26, 0x31, 0x12, 0x08, 0xbb, 0xc2, 0x0c, 0x22<br>- .byte 0x30, 0x1b, 0x10, 0xa2, 0x13, 0x92, 0x21, 0x75<br>- .byte 0x30, 0xff, 0xd2, 0x22, 0xc2, 0x23, 0xd2, 0x24<br>- .byte 0x02, 0x06, 0xee, 0xc2, 0x0c, 0x12, 0x0e, 0x7d<br>- .byte 0x22, 0xe4, 0xf5, 0x26, 0xf5, 0x27, 0x75, 0x28<br>- .byte 0x0f, 0x75, 0x29, 0xff, 0xe5, 0x27, 0x25, 0x29<br>- .byte 0xff, 0xe5, 0x26, 0x35, 0x28, 0xc3, 0x13, 0xf5<br>- .byte 0x2a, 0xef, 0x13, 0xf5, 0x2b, 0xff, 0xae, 0x2a<br>- .byte 0x12, 0x0e, 0x15, 0xbf, 0xff, 0x0e, 0xe5, 0x2b<br>- .byte 0x24, 0xff, 0xf5, 0x29, 0xe5, 0x2a, 0x34, 0xff<br>- .byte 0xf5, 0x28, 0x80, 0x47, 0xef, 0x70, 0x0d, 0xe5<br>- .byte 0x2b, 0x24, 0x01, 0xf5, 0x27, 0xe4, 0x35, 0x2a<br>- .byte 0xf5, 0x26, 0x80, 0x37, 0x75, 0x2c, 0xff, 0xe4<br>- .byte 0xf5, 0x2d, 0xe5, 0x2c, 0xc3, 0x13, 0xf5, 0x2c<br>- .byte 0xb5, 0x07, 0x1c, 0xe5, 0x2b, 0xae, 0x2a, 0x78<br>- .byte 0x03, 0xc3, 0x33, 0xce, 0x33, 0xce, 0xd8, 0xf9<br>- .byte 0x7c, 0x00, 0x25, 0x2d, 0xff, 0xec, 0x3e, 0xcf<br>- .byte 0x24, 0x01, 0xcf, 0x34, 0x00, 0xfe, 0x22, 0x05<br>- .byte 0x2d, 0xe5, 0x2d, 0xb4, 0x07, 0xd4, 0x7e, 0xff<br>- .byte 0x7f, 0xff, 0x22, 0xd3, 0xe5, 0x27, 0x95, 0x29<br>- .byte 0xe5, 0x28, 0x64, 0x80, 0xf8, 0xe5, 0x26, 0x64<br>- .byte 0x80, 0x98, 0x40, 0x80, 0xe5, 0x27, 0xae, 0x26<br>- .byte 0x78, 0x03, 0xc3, 0x33, 0xce, 0x33, 0xce, 0xd8<br>- .byte 0xf9, 0xff, 0x22, 0x78, 0x7f, 0xe4, 0xf6, 0xd8<br>- .byte 0xfd, 0x75, 0x81, 0x3b, 0x02, 0x04, 0xea, 0x02<br>- .byte 0x00, 0x16, 0xe4, 0x93, 0xa3, 0xf8, 0xe4, 0x93<br>- .byte 0xa3, 0x40, 0x03, 0xf6, 0x80, 0x01, 0xf2, 0x08<br>- .byte 0xdf, 0xf4, 0x80, 0x29, 0xe4, 0x93, 0xa3, 0xf8<br>- .byte 0x54, 0x07, 0x24, 0x0c, 0xc8, 0xc3, 0x33, 0xc4<br>- .byte 0x54, 0x0f, 0x44, 0x20, 0xc8, 0x83, 0x40, 0x04<br>- .byte 0xf4, 0x56, 0x80, 0x01, 0x46, 0xf6, 0xdf, 0xe4<br>- .byte 0x80, 0x0b, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20<br>- .byte 0x40, 0x80, 0x90, 0x08, 0x80, 0xe4, 0x7e, 0x01<br>- .byte 0x93, 0x60, 0xbc, 0xa3, 0xff, 0x54, 0x3f, 0x30<br>- .byte 0xe5, 0x09, 0x54, 0x1f, 0xfe, 0xe4, 0x93, 0xa3<br>- .byte 0x60, 0x01, 0x0e, 0xcf, 0x54, 0xc0, 0x25, 0xe0<br>- .byte 0x60, 0xa8, 0x40, 0xb8, 0xe4, 0x93, 0xa3, 0xfa<br>- .byte 0xe4, 0x93, 0xa3, 0xf8, 0xe4, 0x93, 0xa3, 0xc8<br>- .byte 0xc5, 0x82, 0xc8, 0xca, 0xc5, 0x83, 0xca, 0xf0<br>- .byte 0xa3, 0xc8, 0xc5, 0x82, 0xc8, 0xca, 0xc5, 0x83<br>- .byte 0xca, 0xdf, 0xe9, 0xde, 0xe7, 0x80, 0xbe, 0xd2<br>- .byte 0x0d, 0xc2, 0x96, 0xd2, 0x0e, 0xd2, 0x10, 0xc2<br>- .byte 0x94, 0x8f, 0x08, 0x12, 0x0d, 0xca, 0xef, 0x13<br>- .byte 0xb3, 0x92, 0x14, 0xd2, 0x16, 0xe4, 0xf5, 0x0c<br>- .byte 0x7f, 0x28, 0x12, 0x00, 0x06, 0xc2, 0x97, 0xd2<br>- .byte 0x03, 0xc2, 0x0a, 0x7f, 0xe8, 0x7e, 0xfd, 0x12<br>- .byte 0x0c, 0x79, 0xc2, 0x0d, 0xd2, 0x96, 0x30, 0x16<br>- .byte 0x16, 0x12, 0x0e, 0x62, 0x50, 0xf8, 0xc2, 0xaf<br>- .byte 0xd2, 0x97, 0xc2, 0x21, 0x12, 0x06, 0xe5, 0xc2<br>- .byte 0x16, 0xe4, 0xf5, 0x0c, 0xd2, 0xaf, 0x22, 0x7f<br>- .byte 0xe8, 0x7e, 0xfd, 0x12, 0x0c, 0x79, 0x20, 0x04<br>- .byte 0x12, 0x20, 0x0a, 0x0f, 0x12, 0x0e, 0x62, 0x50<br>- .byte 0xf5, 0xc2, 0xaf, 0xc2, 0x21, 0x12, 0x06, 0xe5<br>- .byte 0xd2, 0xaf, 0x22, 0x12, 0x07, 0x2e, 0x22, 0xd2<br>- .byte 0x10, 0xc2, 0x94, 0xd2, 0x0a, 0xd2, 0x0d, 0xc2<br>- .byte 0x96, 0x8f, 0x08, 0x12, 0x0d, 0xca, 0xef, 0x13<br>- .byte 0xb3, 0x92, 0x14, 0xd2, 0x16, 0xe4, 0xf5, 0x0e<br>- .byte 0x7f, 0x28, 0x12, 0x00, 0x06, 0xc2, 0x95, 0xd2<br>- .byte 0x05, 0xc2, 0x0e, 0x7f, 0xe8, 0x7e, 0xfd, 0x12<br>- .byte 0x0c, 0x79, 0xc2, 0x10, 0xd2, 0x94, 0x30, 0x16<br>- .byte 0x14, 0x12, 0x0e, 0x62, 0x50, 0xf8, 0xc2, 0xaf<br>- .byte 0xd2, 0x95, 0x12, 0x06, 0xe3, 0xc2, 0x16, 0xe4<br>- .byte 0xf5, 0x0e, 0xd2, 0xaf, 0x22, 0x7f, 0xe8, 0x7e<br>- .byte 0xfd, 0x12, 0x0c, 0x79, 0x20, 0x07, 0x10, 0x20<br>- .byte 0x0e, 0x0d, 0x12, 0x0e, 0x62, 0x50, 0xf5, 0xc2<br>- .byte 0xaf, 0x12, 0x06, 0xe3, 0xd2, 0xaf, 0x22, 0x12<br>- .byte 0x07, 0x2e, 0x22, 0xad, 0x07, 0xed, 0x30, 0xe6<br>- .byte 0x04, 0xd2, 0x0f, 0x80, 0x02, 0xc2, 0x0f, 0xed<br>- .byte 0x30, 0xe5, 0x05, 0x12, 0x0e, 0x8d, 0x80, 0x03<br>- .byte 0x12, 0x0e, 0xe6, 0xed, 0x30, 0xe4, 0x05, 0x12<br>- .byte 0x0e, 0x94, 0x80, 0x03, 0x12, 0x0e, 0xf0, 0xed<br>- .byte 0x30, 0xe2, 0x04, 0xd2, 0x27, 0x80, 0x02, 0xc2<br>- .byte 0x27, 0x7f, 0x02, 0x12, 0x0b, 0x6c, 0xed, 0x30<br>- .byte 0xe1, 0x05, 0x12, 0x0f, 0x14, 0x80, 0x03, 0x12<br>- .byte 0x0f, 0x11, 0xed, 0x30, 0xe0, 0x0b, 0x12, 0x0f<br>- .byte 0x1a, 0x20, 0x11, 0x08, 0xd2, 0x11, 0xd2, 0x01<br>- .byte 0x22, 0x12, 0x0f, 0x17, 0x22, 0x7f, 0x02, 0x12<br>- .byte 0x00, 0x06, 0x20, 0x94, 0x42, 0xa2, 0x95, 0x92<br>- .byte 0x18, 0x05, 0x0e, 0xe5, 0x0e, 0xb4, 0x01, 0x12<br>- .byte 0x20, 0x18, 0x0a, 0xd2, 0x07, 0xd2, 0x0a, 0xd2<br>- .byte 0x0d, 0xc2, 0x96, 0x80, 0x19, 0xe4, 0xf5, 0x0e<br>- .byte 0x80, 0x14, 0xe5, 0x0e, 0xb4, 0x0b, 0x0f, 0xd2<br>- .byte 0x0e, 0xd2, 0x10, 0xc2, 0x94, 0xd2, 0x13, 0xd2<br>- .byte 0x0c, 0xe4, 0xf5, 0x0e, 0xc2, 0x07, 0xe5, 0x10<br>- .byte 0xc3, 0x13, 0xf5, 0x10, 0xe5, 0x11, 0x13, 0xf5<br>- .byte 0x11, 0x30, 0x18, 0x03, 0x43, 0x10, 0x80, 0x22<br>- .byte 0x7f, 0x02, 0x12, 0x00, 0x06, 0x20, 0x96, 0x42<br>- .byte 0xa2, 0x97, 0x92, 0x19, 0x05, 0x0c, 0xe5, 0x0c<br>- .byte 0xb4, 0x01, 0x12, 0x20, 0x19, 0x0a, 0xd2, 0x04<br>- .byte 0xd2, 0x0e, 0xd2, 0x10, 0xc2, 0x94, 0x80, 0x19<br>- .byte 0xe4, 0xf5, 0x0c, 0x80, 0x14, 0xe5, 0x0c, 0xb4<br>- .byte 0x0b, 0x0f, 0xd2, 0x0a, 0xd2, 0x0d, 0xc2, 0x96<br>- .byte 0xc2, 0x13, 0xd2, 0x0c, 0xe4, 0xf5, 0x0c, 0xc2<br>- .byte 0x04, 0xe5, 0x10, 0xc3, 0x13, 0xf5, 0x10, 0xe5<br>- .byte 0x11, 0x13, 0xf5, 0x11, 0x30, 0x19, 0x03, 0x43<br>- .byte 0x10, 0x80, 0x22, 0xd2, 0x21, 0x75, 0x30, 0xfe<br>- .byte 0xd2, 0x22, 0xd2, 0x23, 0xc2, 0x24, 0xd2, 0x0a<br>- .byte 0xd2, 0x0d, 0xc2, 0x96, 0xd2, 0x0e, 0xd2, 0x10<br>- .byte 0xc2, 0x94, 0xa2, 0x23, 0x92, 0x27, 0x7f, 0x06<br>- .byte 0x12, 0x0b, 0x6c, 0xa2, 0x24, 0x92, 0x27, 0x7f<br>- .byte 0x07, 0x12, 0x0b, 0x6c, 0x30, 0x22, 0x0c, 0xa2<br>- .byte 0x21, 0x92, 0x25, 0x85, 0x30, 0x31, 0x12, 0x08<br>- .byte 0xbb, 0x80, 0x10, 0xa2, 0x21, 0x92, 0x26, 0x85<br>- .byte 0x30, 0x32, 0x12, 0x0b, 0xf9, 0xc2, 0x92, 0xc2<br>- .byte 0x93, 0xd2, 0x09, 0xc2, 0x0c, 0x22, 0x20, 0x04<br>- .byte 0x03, 0x30, 0x07, 0x44, 0x7f, 0xe8, 0x7e, 0xfd<br>- .byte 0x12, 0x0c, 0x79, 0x20, 0x04, 0x03, 0x30, 0x07<br>- .byte 0x37, 0x12, 0x0e, 0x62, 0x50, 0xf5, 0xc2, 0xaf<br>- .byte 0x20, 0x04, 0x03, 0x30, 0x07, 0x26, 0x30, 0x04<br>- .byte 0x04, 0xc2, 0x1f, 0x80, 0x02, 0xd2, 0x1f, 0xe4<br>- .byte 0xf5, 0x0c, 0xc2, 0x04, 0xf5, 0x0e, 0xc2, 0x07<br>- .byte 0x12, 0x0e, 0xeb, 0x12, 0x0e, 0x80, 0xd2, 0xaf<br>- .byte 0xa2, 0x1f, 0x92, 0x21, 0x75, 0x30, 0xff, 0x12<br>- .byte 0x06, 0xe8, 0x80, 0xc7, 0xd2, 0xaf, 0x80, 0xc3<br>- .byte 0x22, 0xe5, 0x19, 0x60, 0x03, 0xb4, 0x02, 0x09<br>- .byte 0xe5, 0x0d, 0x90, 0x03, 0x63, 0x93, 0x6f, 0x60<br>- .byte 0x0b, 0xe5, 0x19, 0x64, 0x01, 0x70, 0x2d, 0xef<br>- .byte 0x64, 0xf0, 0x70, 0x28, 0x05, 0x19, 0xe5, 0x19<br>- .byte 0xd3, 0x94, 0x02, 0x40, 0x24, 0xe4, 0xf5, 0x19<br>- .byte 0x05, 0x0d, 0xe5, 0x0d, 0x94, 0x09, 0x40, 0x19<br>- .byte 0x75, 0x2a, 0x05, 0xe4, 0xff, 0x12, 0x0c, 0x3b<br>- .byte 0x7f, 0x07, 0x12, 0x0c, 0x3b, 0xd5, 0x2a, 0xf3<br>- .byte 0xe4, 0xf5, 0x0d, 0x22, 0xe4, 0xf5, 0x0d, 0xf5<br>- .byte 0x19, 0x22, 0xe5, 0x3b, 0x64, 0x15, 0x70, 0x41<br>- .byte 0x12, 0x0c, 0xed, 0xe5, 0x3a, 0x30, 0xe0, 0x05<br>- .byte 0x75, 0x26, 0x80, 0x80, 0x03, 0xe4, 0xf5, 0x26<br>- .byte 0xe5, 0x3a, 0xc3, 0x13, 0xf5, 0x3a, 0xe5, 0x39<br>- .byte 0x30, 0xe0, 0x03, 0x43, 0x3a, 0x80, 0xe5, 0x39<br>- .byte 0xc3, 0x13, 0xf5, 0x39, 0xe5, 0x38, 0x30, 0xe0<br>- .byte 0x03, 0x43, 0x39, 0x80, 0xc2, 0xb6, 0x90, 0xd0<br>- .byte 0x01, 0xe4, 0xf0, 0xa3, 0xe5, 0x26, 0xf0, 0xa3<br>- .byte 0xe5, 0x3a, 0xf0, 0xa3, 0xe5, 0x39, 0xf0, 0xd2<br>- .byte 0xb6, 0x22, 0x20, 0x94, 0x37, 0x05, 0x0e, 0xe5<br>- .byte 0x0e, 0xd3, 0x94, 0x08, 0x50, 0x12, 0xe5, 0x08<br>- .byte 0x30, 0xe0, 0x04, 0xd2, 0x95, 0x80, 0x02, 0xc2<br>- .byte 0x95, 0xe5, 0x08, 0xc3, 0x13, 0xf5, 0x08, 0x22<br>- .byte 0xe5, 0x0e, 0xb4, 0x09, 0x05, 0xa2, 0x14, 0x92<br>- .byte 0x95, 0x22, 0xe5, 0x0e, 0xb4, 0x0a, 0x03, 0xd2<br>- .byte 0x95, 0x22, 0xe5, 0x0e, 0xb4, 0x0b, 0x05, 0xc2<br>- .byte 0x16, 0xe4, 0xf5, 0x0e, 0x22, 0x20, 0x96, 0x37<br>- .byte 0x05, 0x0c, 0xe5, 0x0c, 0xd3, 0x94, 0x08, 0x50<br>- .byte 0x12, 0xe5, 0x08, 0x30, 0xe0, 0x04, 0xd2, 0x97<br>- .byte 0x80, 0x02, 0xc2, 0x97, 0xe5, 0x08, 0xc3, 0x13<br>- .byte 0xf5, 0x08, 0x22, 0xe5, 0x0c, 0xb4, 0x09, 0x05<br>- .byte 0xa2, 0x14, 0x92, 0x97, 0x22, 0xe5, 0x0c, 0xb4<br>- .byte 0x0a, 0x03, 0xd2, 0x97, 0x22, 0xe5, 0x0c, 0xb4<br>- .byte 0x0b, 0x05, 0xc2, 0x16, 0xe4, 0xf5, 0x0c, 0x22<br>- .byte 0x01, 0x0c, 0x00, 0xc1, 0x04, 0xc1, 0x0a, 0xc1<br>- .byte 0x83, 0xc1, 0x0c, 0xc1, 0x09, 0xc1, 0x02, 0xc1<br>- .byte 0x16, 0xc1, 0x08, 0x01, 0x0e, 0x00, 0xc1, 0x07<br>- .byte 0xc1, 0x0e, 0xc1, 0x85, 0xc1, 0x8b, 0xc1, 0x86<br>- .byte 0xc1, 0x8f, 0xc1, 0x12, 0xc1, 0x00, 0xc1, 0x11<br>- .byte 0xc1, 0x01, 0xc1, 0x17, 0x01, 0x0d, 0x00, 0x01<br>- .byte 0x19, 0x00, 0x01, 0x1a, 0x00, 0x01, 0x34, 0x03<br>- .byte 0xc1, 0x29, 0x00, 0xa2, 0x25, 0x92, 0x26, 0x85<br>- .byte 0x31, 0x32, 0x12, 0x0b, 0xf9, 0xc2, 0x92, 0xc2<br>- .byte 0x93, 0x20, 0x25, 0x03, 0x20, 0x06, 0x06, 0x30<br>- .byte 0x25, 0x1d, 0x30, 0x0b, 0x1a, 0x7f, 0x69, 0x7e<br>- .byte 0x00, 0x12, 0x0c, 0x79, 0x12, 0x0e, 0x62, 0x50<br>- .byte 0xfb, 0x12, 0x0e, 0xb0, 0x50, 0x09, 0x20, 0x25<br>- .byte 0x04, 0xd2, 0x92, 0x80, 0x02, 0xd2, 0x93, 0xd2<br>- .byte 0x09, 0x22, 0x90, 0x0f, 0xfc, 0xe4, 0x93, 0xfe<br>- .byte 0x74, 0x01, 0x93, 0xff, 0xc3, 0x95, 0x3a, 0xf5<br>- .byte 0x0b, 0xee, 0x95, 0x39, 0xf5, 0x0a, 0x90, 0x0f<br>- .byte 0xfb, 0xe4, 0x93, 0xc3, 0x95, 0x38, 0xf5, 0x09<br>- .byte 0xc3, 0xef, 0x95, 0x3a, 0xee, 0x95, 0x39, 0x50<br>- .byte 0x02, 0x15, 0x09, 0xe5, 0x09, 0x30, 0xe7, 0x07<br>- .byte 0xe4, 0xf5, 0x09, 0xf5, 0x0a, 0xf5, 0x0b, 0x22<br>- .byte 0x05, 0x35, 0xaf, 0x35, 0xae, 0x07, 0xee, 0x14<br>- .byte 0x13, 0x13, 0x13, 0x54, 0x1f, 0xfd, 0xee, 0x54<br>- .byte 0x07, 0xff, 0x70, 0x06, 0xf5, 0x26, 0xf5, 0x27<br>- .byte 0x80, 0x15, 0x74, 0xff, 0x7e, 0x00, 0xa8, 0x07<br>- .byte 0x08, 0x80, 0x06, 0xce, 0xa2, 0xe7, 0x13, 0xce<br>- .byte 0x13, 0xd8, 0xf8, 0xf5, 0x27, 0x8e, 0x26, 0xaf<br>- .byte 0x05, 0xad, 0x27, 0x02, 0x0c, 0x5a, 0xe4, 0xff<br>- .byte 0x7e, 0x01, 0xef, 0xc3, 0x94, 0x08, 0x50, 0x27<br>- .byte 0xef, 0x60, 0x1d, 0x64, 0x01, 0x60, 0x19, 0xef<br>- .byte 0x64, 0x03, 0x60, 0x14, 0xee, 0x44, 0x02, 0x54<br>- .byte 0xfe, 0x90, 0xe0, 0x00, 0xf0, 0x54, 0xf4, 0xfd<br>- .byte 0xee, 0x54, 0xf4, 0x6d, 0x60, 0x02, 0xd3, 0x22<br>- .byte 0x0f, 0xee, 0x25, 0xe0, 0xfe, 0x80, 0xd3, 0xc3<br>- .byte 0x22, 0xad, 0x07, 0xac, 0x06, 0xed, 0x24, 0xff<br>- .byte 0xff, 0xec, 0x34, 0xff, 0xfe, 0xef, 0x78, 0x03<br>- .byte 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, 0xf9, 0xff<br>- .byte 0xed, 0x54, 0x07, 0xfd, 0x70, 0x04, 0xf5, 0x26<br>- .byte 0x80, 0x0d, 0x74, 0xff, 0xa8, 0x05, 0x08, 0x80<br>- .byte 0x02, 0xc3, 0x13, 0xd8, 0xfc, 0xf5, 0x26, 0xad<br>- .byte 0x26, 0x02, 0x0a, 0xad, 0xc2, 0x28, 0x20, 0x29<br>- .byte 0x0f, 0x12, 0x0f, 0x0d, 0x8f, 0x3b, 0xe5, 0x3b<br>- .byte 0xb4, 0x15, 0x03, 0x75, 0x34, 0x1f, 0xd2, 0x29<br>- .byte 0x12, 0x0a, 0x56, 0x8f, 0x35, 0xe5, 0x35, 0x30<br>- .byte 0xe0, 0x0c, 0x12, 0x0d, 0x7d, 0x12, 0x09, 0x28<br>- .byte 0xe4, 0xf5, 0x36, 0xf5, 0x37, 0x22, 0x12, 0x04<br>- .byte 0x09, 0x8e, 0x36, 0x8f, 0x37, 0x22, 0x20, 0x0f<br>- .byte 0x03, 0x7e, 0x00, 0x22, 0xbf, 0xf0, 0x07, 0xd2<br>- .byte 0x15, 0x7e, 0xff, 0x7f, 0xff, 0x22, 0xef, 0xc3<br>- .byte 0x94, 0x85, 0x40, 0x03, 0x7e, 0x00, 0x22, 0xef<br>- .byte 0x90, 0x02, 0xce, 0x93, 0xfe, 0x70, 0x02, 0xfe<br>- .byte 0x22, 0x30, 0x15, 0x03, 0x43, 0x06, 0x80, 0xc2<br>- .byte 0x15, 0xaf, 0x06, 0x7e, 0x00, 0x22, 0xa2, 0x1a<br>- .byte 0x92, 0x28, 0x05, 0x37, 0xe5, 0x37, 0x70, 0x02<br>- .byte 0x05, 0x36, 0xc3, 0xe5, 0x36, 0x94, 0x80, 0x50<br>- .byte 0x07, 0xaf, 0x37, 0xae, 0x36, 0x02, 0x09, 0x91<br>- .byte 0xe5, 0x35, 0xc3, 0x94, 0x10, 0x50, 0x0e, 0x12<br>- .byte 0x09, 0x28, 0x12, 0x0d, 0x7d, 0x12, 0x09, 0x28<br>- .byte 0xe4, 0xf5, 0x36, 0xf5, 0x37, 0x22, 0xe4, 0xff<br>- .byte 0x12, 0x0e, 0x23, 0x7e, 0xff, 0xe4, 0xf5, 0x26<br>- .byte 0xe5, 0x26, 0xb4, 0x08, 0x07, 0x7f, 0x01, 0x12<br>- .byte 0x0e, 0x23, 0x7e, 0xff, 0xee, 0xb5, 0x07, 0x03<br>- .byte 0xaf, 0x26, 0x22, 0xee, 0xc3, 0x13, 0xfe, 0x05<br>- .byte 0x26, 0xe5, 0x26, 0xd3, 0x94, 0x10, 0x40, 0xe0<br>- .byte 0x7f, 0xff, 0x22, 0xe4, 0xff, 0x30, 0x0f, 0x02<br>- .byte 0x7f, 0x40, 0x20, 0x05, 0x03, 0x43, 0x07, 0x20<br>- .byte 0x20, 0x03, 0x03, 0x43, 0x07, 0x10, 0x90, 0xe0<br>- .byte 0x00, 0xe0, 0x30, 0xe2, 0x03, 0x43, 0x07, 0x04<br>- .byte 0x30, 0x0b, 0x03, 0x43, 0x07, 0x02, 0x30, 0x06<br>- .byte 0x03, 0x43, 0x07, 0x01, 0x22, 0x8e, 0x27, 0x8f<br>- .byte 0x28, 0x8d, 0x29, 0x12, 0x0e, 0x74, 0xe5, 0x27<br>- .byte 0x24, 0xd0, 0xf5, 0x2a, 0xe5, 0x28, 0xf5, 0x2b<br>- .byte 0x12, 0x0e, 0xa2, 0x85, 0x29, 0x2f, 0xab, 0x2b<br>- .byte 0xad, 0x2a, 0xaf, 0x34, 0x12, 0x0b, 0x47, 0x12<br>- .byte 0x0e, 0xa9, 0x02, 0x0d, 0xea, 0xc0, 0xe0, 0xc0<br>- .byte 0xf0, 0xc0, 0xd0, 0x75, 0xd0, 0x00, 0xc0, 0x06<br>- .byte 0xc0, 0x07, 0x20, 0x10, 0x0b, 0x30, 0x16, 0x05<br>- .byte 0x12, 0x08, 0x0a, 0x80, 0x03, 0x12, 0x06, 0x4d<br>- .byte 0xd0, 0x07, 0xd0, 0x06, 0xd0, 0xd0, 0xd0, 0xf0<br>- .byte 0xd0, 0xe0, 0x32, 0xc0, 0xe0, 0xc0, 0xf0, 0xc0<br>- .byte 0xd0, 0x75, 0xd0, 0x00, 0xc0, 0x06, 0xc0, 0x07<br>- .byte 0x20, 0x0d, 0x0b, 0x30, 0x16, 0x05, 0x12, 0x08<br>- .byte 0x45, 0x80, 0x03, 0x12, 0x06, 0x98, 0xd0, 0x07<br>- .byte 0xd0, 0x06, 0xd0, 0xd0, 0xd0, 0xf0, 0xd0, 0xe0<br>- .byte 0x32, 0xd0, 0x83, 0xd0, 0x82, 0xf8, 0xe4, 0x93<br>- .byte 0x70, 0x12, 0x74, 0x01, 0x93, 0x70, 0x0d, 0xa3<br>- .byte 0xa3, 0x93, 0xf8, 0x74, 0x01, 0x93, 0xf5, 0x82<br>- .byte 0x88, 0x83, 0xe4, 0x73, 0x74, 0x02, 0x93, 0x68<br>- .byte 0x60, 0xef, 0xa3, 0xa3, 0xa3, 0x80, 0xdf, 0xae<br>- .byte 0x03, 0xab, 0x05, 0x53, 0x1a, 0xef, 0x90, 0xd0<br>- .byte 0x00, 0xe5, 0x1a, 0xf0, 0xad, 0x07, 0x8e, 0x33<br>- .byte 0x7f, 0x02, 0x12, 0x0d, 0x51, 0xaf, 0x2f, 0x12<br>- .byte 0x0c, 0xd0, 0x43, 0x1a, 0x10, 0x90, 0xd0, 0x00<br>- .byte 0xe5, 0x1a, 0xf0, 0x22, 0x74, 0x01, 0xa8, 0x07<br>- .byte 0x08, 0x80, 0x02, 0xc3, 0x33, 0xd8, 0xfc, 0xff<br>- .byte 0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02, 0xfe, 0xef<br>- .byte 0x30, 0x27, 0x04, 0x42, 0x06, 0x80, 0x03, 0xf4<br>- .byte 0x52, 0x06, 0x90, 0xe0, 0x00, 0xee, 0xf0, 0x22<br>- .byte 0x12, 0x0e, 0x07, 0x40, 0x05, 0x12, 0x01, 0x05<br>- .byte 0x80, 0xf6, 0x12, 0x0e, 0xc8, 0x12, 0x0e, 0xd4<br>- .byte 0xc2, 0x1f, 0x75, 0x2f, 0xee, 0xa2, 0x06, 0x92<br>- .byte 0x20, 0x12, 0x0d, 0xb8, 0x90, 0xd0, 0x00, 0xe0<br>- .byte 0x30, 0xe1, 0xf9, 0x22, 0xae, 0x03, 0xab, 0x05<br>- .byte 0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00, 0xe5, 0x1a<br>- .byte 0xf0, 0xad, 0x07, 0x8e, 0x33, 0x7f, 0x03, 0x12<br>- .byte 0x0d, 0x51, 0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10<br>- .byte 0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0x22, 0xe5<br>- .byte 0x1a, 0x54, 0x9f, 0xfd, 0x44, 0x20, 0xfe, 0x7c<br>- .byte 0x08, 0xef, 0x25, 0xe0, 0xff, 0x90, 0xd0, 0x00<br>- .byte 0xed, 0xf0, 0xe0, 0x30, 0xe4, 0x03, 0x43, 0x07<br>- .byte 0x01, 0x90, 0xd0, 0x00, 0xee, 0xf0, 0xdc, 0xe9<br>- .byte 0x22, 0x90, 0xf0, 0x00, 0xe5, 0x32, 0xf0, 0xf5<br>- .byte 0x0f, 0xa2, 0x26, 0x92, 0x27, 0x7f, 0x05, 0x12<br>- .byte 0x0b, 0x6c, 0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02<br>- .byte 0x54, 0xfe, 0xfe, 0xf0, 0x44, 0x01, 0xf0, 0xee<br>- .byte 0xf0, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00<br>- .byte 0xe5, 0x1a, 0xf0, 0x7f, 0x9f, 0x12, 0x0c, 0xd0<br>- .byte 0x12, 0x0b, 0xd7, 0x12, 0x0b, 0xd7, 0x12, 0x0b<br>- .byte 0xd7, 0x43, 0x1a, 0x10, 0x90, 0xd0, 0x00, 0xe5<br>- .byte 0x1a, 0xf0, 0x22, 0x8f, 0x2b, 0x7f, 0xed, 0x12<br>- .byte 0x05, 0x2f, 0xaf, 0x2b, 0x12, 0x05, 0x2f, 0x75<br>- .byte 0x2c, 0x0a, 0x7f, 0xe8, 0x7e, 0xfd, 0x12, 0x0c<br>- .byte 0x79, 0x12, 0x0e, 0x62, 0x50, 0xfb, 0xd5, 0x2c<br>- .byte 0xf1, 0x22, 0x8f, 0x28, 0x8d, 0x29, 0x12, 0x0e<br>- .byte 0x74, 0x12, 0x0e, 0xa2, 0xe5, 0x28, 0x24, 0xfe<br>- .byte 0xfb, 0x85, 0x29, 0x2f, 0x7d, 0xef, 0xaf, 0x34<br>- .byte 0x12, 0x0b, 0x47, 0x12, 0x0e, 0xa9, 0x02, 0x0d<br>- .byte 0xea, 0xad, 0x07, 0xac, 0x06, 0xc2, 0x8c, 0xed<br>- .byte 0xf4, 0xff, 0xec, 0xf4, 0xfe, 0xef, 0x24, 0x01<br>- .byte 0xfd, 0xe4, 0x3e, 0xf5, 0x8c, 0xaf, 0x05, 0x8f<br>- .byte 0x8a, 0xc2, 0x8d, 0xd2, 0x8c, 0x22, 0xad, 0x07<br>- .byte 0xac, 0x06, 0xc2, 0xca, 0xed, 0xf4, 0xff, 0xec<br>- .byte 0xf4, 0xfe, 0xef, 0x24, 0x01, 0xfd, 0xe4, 0x3e<br>- .byte 0xf5, 0xcd, 0xaf, 0x05, 0x8f, 0xcc, 0xc2, 0xcf<br>- .byte 0xd2, 0xca, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0<br>- .byte 0x00, 0xe5, 0x1a, 0xf0, 0x7f, 0x05, 0x12, 0x0c<br>- .byte 0xd0, 0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10, 0x90<br>- .byte 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0xef, 0x13, 0x22<br>- .byte 0xe5, 0x1a, 0x54, 0x9f, 0xfe, 0x44, 0x40, 0xfd<br>- .byte 0x7c, 0x08, 0x90, 0xd0, 0x00, 0xef, 0x33, 0xff<br>- .byte 0x50, 0x03, 0xed, 0x80, 0x01, 0xee, 0xf0, 0x44<br>- .byte 0x20, 0xf0, 0xdc, 0xf1, 0x22, 0x12, 0x0f, 0x04<br>- .byte 0x8e, 0x39, 0x8f, 0x3a, 0x12, 0x0f, 0x1d, 0x8f<br>- .byte 0x38, 0xe5, 0x38, 0x30, 0xe1, 0x03, 0x43, 0x39<br>- .byte 0x80, 0xe5, 0x38, 0x13, 0x13, 0x54, 0x3f, 0xf5<br>- .byte 0x38, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00<br>- .byte 0xe5, 0x1a, 0xf0, 0x7f, 0x05, 0x12, 0x0c, 0xd0<br>- .byte 0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10, 0x90, 0xd0<br>- .byte 0x00, 0xe5, 0x1a, 0xf0, 0x22, 0x12, 0x0e, 0xc8<br>- .byte 0x12, 0x0e, 0xd4, 0x90, 0xd0, 0x00, 0xe0, 0x20<br>- .byte 0xe1, 0x08, 0x12, 0x03, 0x6c, 0x12, 0x01, 0x05<br>- .byte 0x80, 0xf1, 0x22, 0x12, 0x0c, 0xed, 0x12, 0x08<br>- .byte 0xf2, 0xe5, 0x09, 0x70, 0x0b, 0xe5, 0x0a, 0x70<br>- .byte 0x07, 0xe5, 0x0b, 0x70, 0x03, 0x12, 0x0e, 0xda<br>- .byte 0x22, 0x8d, 0x31, 0x8b, 0x32, 0x12, 0x0c, 0xd0<br>- .byte 0xaf, 0x31, 0x12, 0x0c, 0xd0, 0xaf, 0x32, 0x12<br>- .byte 0x0c, 0xd0, 0xaf, 0x33, 0x02, 0x0c, 0xd0, 0x53<br>- .byte 0x1a, 0xef, 0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0<br>- .byte 0x12, 0x0c, 0xd0, 0x43, 0x1a, 0x10, 0x90, 0xd0<br>- .byte 0x00, 0xe5, 0x1a, 0xf0, 0x22, 0x12, 0x0e, 0x74<br>- .byte 0x12, 0x0e, 0xa2, 0xe4, 0xfb, 0x7d, 0xd0, 0xaf<br>- .byte 0x34, 0x12, 0x00, 0xe0, 0x12, 0x0e, 0xa9, 0x02<br>- .byte 0x0d, 0xea, 0x53, 0x1a, 0xfb, 0x90, 0xd0, 0x00<br>- .byte 0xe5, 0x1a, 0xf0, 0x53, 0x1a, 0xfd, 0xe5, 0x1a<br>- .byte 0xf0, 0x7f, 0x3c, 0x02, 0x00, 0x06, 0x30, 0x09<br>- .byte 0x0e, 0x12, 0x0e, 0xb0, 0x40, 0x09, 0xc2, 0x92<br>- .byte 0xc2, 0x93, 0xc2, 0x09, 0x12, 0x0e, 0x7d, 0x22<br>- .byte 0xa2, 0x1f, 0x92, 0x21, 0x85, 0x2f, 0x30, 0xa2<br>- .byte 0x20, 0x92, 0x22, 0xc2, 0x23, 0xc2, 0x24, 0x02<br>- .byte 0x06, 0xee, 0xef, 0xc4, 0x54, 0x0f, 0x90, 0x03<br>- .byte 0x53, 0x93, 0xfe, 0xef, 0x54, 0x0f, 0x93, 0x2e<br>- .byte 0xff, 0x22, 0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02<br>- .byte 0x54, 0xfe, 0xfe, 0xf0, 0x54, 0xfd, 0xf0, 0xee<br>- .byte 0xf0, 0x22, 0x12, 0x0e, 0xa2, 0x12, 0x0c, 0xb3<br>- .byte 0x92, 0x1b, 0x12, 0x0e, 0xa9, 0x20, 0x1b, 0xf2<br>- .byte 0x22, 0x30, 0x05, 0x09, 0x20, 0x0e, 0x06, 0x20<br>- .byte 0x02, 0x03, 0xd3, 0x80, 0x01, 0xc3, 0x22, 0x30<br>- .byte 0x03, 0x09, 0x20, 0x0a, 0x06, 0x20, 0x02, 0x03<br>- .byte 0xd3, 0x80, 0x01, 0xc3, 0x22, 0xaa, 0x06, 0xea<br>- .byte 0x24, 0xd0, 0xfd, 0xef, 0xfb, 0xaf, 0x34, 0x12<br>- .byte 0x0b, 0xb4, 0x22, 0xef, 0x24, 0xfe, 0xfb, 0x7d<br>- .byte 0xef, 0xaf, 0x34, 0x12, 0x0b, 0xb4, 0x22, 0xd2<br>- .byte 0x02, 0xd2, 0x0d, 0xc2, 0x96, 0xd2, 0x10, 0xc2<br>- .byte 0x94, 0x22, 0xef, 0x90, 0x02, 0xc9, 0x93, 0x6d<br>- .byte 0x60, 0x02, 0x80, 0xfe, 0x22, 0x12, 0x0d, 0xf9<br>- .byte 0x50, 0x04, 0xc2, 0x10, 0xd2, 0x94, 0x22, 0x12<br>- .byte 0x0e, 0x07, 0x50, 0x04, 0xc2, 0x0d, 0xd2, 0x96<br>- .byte 0x22, 0xe5, 0x89, 0x54, 0xf0, 0x44, 0x01, 0xf5<br>- .byte 0x89, 0x22, 0x30, 0x8d, 0x04, 0xc2, 0x8c, 0xd3<br>- .byte 0x22, 0xc3, 0x22, 0x30, 0xcf, 0x04, 0xc2, 0xca<br>- .byte 0xd3, 0x22, 0xc3, 0x22, 0x12, 0x0e, 0xa2, 0x12<br>- .byte 0x0e, 0xfa, 0x02, 0x0e, 0xa9, 0x12, 0x0e, 0xeb<br>- .byte 0xc2, 0x0e, 0x02, 0x0e, 0x45, 0xc2, 0x02, 0x12<br>- .byte 0x0e, 0x4f, 0x02, 0x0e, 0x45, 0xc2, 0x05, 0xd2<br>- .byte 0x10, 0xc2, 0x94, 0x22, 0xc2, 0x03, 0xd2, 0x0d<br>- .byte 0xc2, 0x96, 0x22, 0x90, 0xd0, 0x00, 0xe5, 0x1a<br>- .byte 0xf0, 0x22, 0x30, 0x28, 0x03, 0x12, 0x0b, 0x90<br>- .byte 0x22, 0x30, 0x28, 0x03, 0x12, 0x0d, 0x92, 0x22<br>- .byte 0x90, 0xe0, 0x00, 0xe0, 0x13, 0x22, 0x53, 0x1a<br>- .byte 0xfe, 0x02, 0x0e, 0x9b, 0x43, 0x1a, 0x01, 0x02<br>- .byte 0x0e, 0x9b, 0x53, 0x1a, 0xfd, 0x02, 0x0e, 0x9b<br>- .byte 0x43, 0x1a, 0x02, 0x02, 0x0e, 0x9b, 0x53, 0x1a<br>- .byte 0xfb, 0x02, 0x0e, 0x9b, 0x43, 0x1a, 0x04, 0x02<br>- .byte 0x0e, 0x9b, 0x53, 0x1a, 0x7f, 0x02, 0x0e, 0x9b<br>- .byte 0x43, 0x1a, 0x80, 0x02, 0x0e, 0x9b, 0xd2, 0x05<br>- .byte 0x02, 0x0e, 0x45, 0xc2, 0x0a, 0x02, 0x0e, 0x4f<br>- .byte 0xd2, 0x03, 0x02, 0x0e, 0x4f, 0x8f, 0x1a, 0x02<br>- .byte 0x0e, 0x9b, 0x7f, 0x06, 0x02, 0x0d, 0x67, 0x7f<br>- .byte 0x04, 0x02, 0x0d, 0x67, 0xae, 0x36, 0xaf, 0x37<br>- .byte 0x22, 0xe4, 0xf5, 0xc8, 0x22, 0x12, 0x0c, 0x1a<br>- .byte 0x22, 0xc2, 0x0b, 0x22, 0xd2, 0x0b, 0x22, 0xc2<br>- .byte 0x06, 0x22, 0xd2, 0x06, 0x22, 0xaf, 0x35, 0x22<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>- .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff<br>diff --git a/src/mainboard/dmp/Kconfig b/src/mainboard/dmp/Kconfig<br>deleted file mode 100644<br>index 055d88f..0000000<br>--- a/src/mainboard/dmp/Kconfig<br>+++ /dev/null<br>@@ -1,31 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2013 DMP Electronics Inc.<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-if VENDOR_DMP<br>-<br>-choice<br>- prompt "Mainboard model"<br>-<br>-source "src/mainboard/dmp/*/Kconfig.name"<br>-<br>-endchoice<br>-<br>-source "src/mainboard/dmp/*/Kconfig"<br>-<br>-config MAINBOARD_VENDOR<br>- string<br>- default "DMP"<br>-<br>-endif # VENDOR_DMP<br>diff --git a/src/mainboard/dmp/Kconfig.name b/src/mainboard/dmp/Kconfig.name<br>deleted file mode 100644<br>index ddce56a..0000000<br>--- a/src/mainboard/dmp/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config VENDOR_DMP<br>- bool "DMP"<br>diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig<br>deleted file mode 100644<br>index 9c4c178..0000000<br>--- a/src/mainboard/dmp/vortex86ex/Kconfig<br>+++ /dev/null<br>@@ -1,1352 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2013 DMP Electronics Inc.<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-if BOARD_DMP_EX<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_DMP_VORTEX86EX<br>- select SOC_DMP_VORTEX86EX<br>- select HAVE_PIRQ_TABLE<br>- select BOARD_ROMSIZE_KB_256<br>- select ROMCC<br>- select HAVE_DEBUG_RAM_SETUP<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default dmp/vortex86ex<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "Vortex86EX"<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 12<br>-<br>-config ID_SECTION_OFFSET<br>- # Vortex86 ROM fixed data areas used too big range, we need<br>- # to move ID from default address to another place.<br>- # 18K below top of ROM should be ok.<br>- hex<br>- default 0x4800<br>-<br>-# SPI I/O base address control.<br>-config I2C_BASE<br>- hex<br>- default 0xfb00<br>-<br>-menu "On-Chip Device Power Down Control"<br>-<br>- config TEMP_POWERDOWN<br>- bool "Temperature sensor power-down"<br>-<br>- config SATA_POWERDOWN<br>- bool "SATA power-down"<br>-<br>- config ADC_POWERDOWN<br>- bool "ADC power-down"<br>-<br>- config PCIE0_POWERDOWN<br>- bool "PCIE0 power-down"<br>-<br>- config MAC_POWERDOWN<br>- bool "MAC power-down"<br>-<br>- config USB1_POWERDOWN<br>- bool "USB2.0 Host Controller 1 power-down"<br>-<br>- config IDE_POWERDOWN<br>- bool "IDE power-down"<br>-<br>-endmenu<br>-<br>-menu "Watchdog Timer setting"<br>-<br>-config WDT1_INITIALIZE<br>- bool "Initialize WDT1"<br>- default n<br>-<br>-config WDT1_ENABLE<br>- depends on WDT1_INITIALIZE<br>- bool "Enable WDT1"<br>- default n<br>-<br>-choice<br>- depends on WDT1_INITIALIZE<br>- prompt "WDT1 Signal Select"<br>- default WDT1_SIGNAL_RESET<br>-<br>-config WDT1_SINGAL_NMI<br>- bool "NMI"<br>-config WDT1_SIGNAL_RESET<br>- bool "Reset"<br>-config WDT1_SIGNAL_SMI<br>- bool "SMI"<br>-<br>-endchoice<br>-<br>-endmenu<br>-<br>-menu "IDE controller setting"<br>-<br>-choice<br>- prompt "Operation Mode"<br>- default IDE_NATIVE_MODE<br>-<br>-config IDE_NATIVE_MODE<br>- bool "Native Mode"<br>-config IDE_LEGACY_MODE<br>- bool "Legacy Mode"<br>-<br>-endchoice<br>-<br>-config IDE1_ENABLE<br>- bool "IDE Primary channel Enable"<br>- default y<br>-<br>-config IDE2_ENABLE<br>- bool "IDE Secondary channel Enable"<br>- default y<br>-<br>-config IDE_STANDARD_COMPATIBLE<br>- bool "Standard IDE Compatible"<br>- default n<br>- help<br>- Built-in IDE controller PCI vendor/device ID is 17F3:1012, which<br>- is not recognized by some OSes.<br>-<br>- This option can change IDE controller PCI vendor/device ID to<br>- other value for software compatibility.<br>-<br>-config IDE_COMPATIBLE_SELECTION<br>- depends on IDE_STANDARD_COMPATIBLE<br>- hex "IDE Compatible Selection"<br>- default 0x808624db<br>- help<br>- IDE controller PCI vendor/device ID value setting.<br>-<br>- Higher 16-bit is vendor ID, lower 16-bit is device ID.<br>-<br>-endmenu<br>-<br>-# GPIO setting :<br>-menu "GPIO setting"<br>-<br>-# Begin of GPIO0<br>-config GPIO_P0_ENABLE<br>- bool "GPIO port 0 Enable"<br>- default n<br>-<br>-config GPIO_P0_DATA_ADDR<br>- hex "GPIO port 0 data address"<br>- depends on GPIO_P0_ENABLE<br>-<br>-config GPIO_P0_DIR_ADDR<br>- hex "GPIO port 0 direction address"<br>- depends on GPIO_P0_ENABLE<br>-<br>-config GPIO_P0_INIT_DIR<br>- hex "GPIO port 0 initial direction"<br>- default 0x00<br>- depends on GPIO_P0_ENABLE<br>-<br>-config GPIO_P0_INIT_DATA<br>- hex "GPIO port 0 initial data"<br>- depends on GPIO_P0_ENABLE<br>-# end of GPIO0<br>-<br>-# Begin of GPIO1<br>-config GPIO_P1_ENABLE<br>- bool "GPIO port 1 Enable"<br>- default n<br>-<br>-config GPIO_P1_DATA_ADDR<br>- hex "GPIO port 1 data address"<br>- depends on GPIO_P1_ENABLE<br>-<br>-config GPIO_P1_DIR_ADDR<br>- hex "GPIO port 1 direction address"<br>- depends on GPIO_P1_ENABLE<br>-<br>-config GPIO_P1_INIT_DIR<br>- hex "GPIO port 1 initial direction"<br>- default 0x00<br>- depends on GPIO_P1_ENABLE<br>-<br>-config GPIO_P1_INIT_DATA<br>- hex "GPIO port 1 initial data"<br>- depends on GPIO_P1_ENABLE<br>-# end of GPIO1<br>-<br>-# Begin of GPIO2<br>-config GPIO_P2_ENABLE<br>- bool "GPIO port 2 Enable"<br>- default n<br>-<br>-config GPIO_P2_DATA_ADDR<br>- hex "GPIO port 2 data address"<br>- depends on GPIO_P2_ENABLE<br>-<br>-config GPIO_P2_DIR_ADDR<br>- hex "GPIO port 2 direction address"<br>- depends on GPIO_P2_ENABLE<br>-<br>-config GPIO_P2_INIT_DIR<br>- hex "GPIO port 2 initial direction"<br>- default 0x00<br>- depends on GPIO_P2_ENABLE<br>-<br>-config GPIO_P2_INIT_DATA<br>- hex "GPIO port 2 initial data"<br>- depends on GPIO_P2_ENABLE<br>-# end of GPIO2<br>-<br>-# Begin of GPIO3<br>-config GPIO_P3_ENABLE<br>- bool "GPIO port 3 Enable"<br>- default n<br>-<br>-config GPIO_P3_DATA_ADDR<br>- hex "GPIO port 3 data address"<br>- depends on GPIO_P3_ENABLE<br>-<br>-config GPIO_P3_DIR_ADDR<br>- hex "GPIO port 3 direction address"<br>- depends on GPIO_P3_ENABLE<br>-<br>-config GPIO_P3_INIT_DIR<br>- hex "GPIO port 3 initial direction"<br>- default 0x00<br>- depends on GPIO_P3_ENABLE<br>-<br>-config GPIO_P3_INIT_DATA<br>- hex "GPIO port 3 initial data"<br>- depends on GPIO_P3_ENABLE<br>-# end of GPIO3<br>-<br>-# Begin of GPIO4<br>-config GPIO_P4_ENABLE<br>- bool "GPIO port 4 Enable"<br>- default n<br>-<br>-config GPIO_P4_DATA_ADDR<br>- hex "GPIO port 4 data address"<br>- depends on GPIO_P4_ENABLE<br>-<br>-config GPIO_P4_DIR_ADDR<br>- hex "GPIO port 4 direction address"<br>- depends on GPIO_P4_ENABLE<br>-<br>-config GPIO_P4_INIT_DIR<br>- hex "GPIO port 4 initial direction"<br>- default 0x00<br>- depends on GPIO_P4_ENABLE<br>-<br>-config GPIO_P4_INIT_DATA<br>- hex "GPIO port 4 initial data"<br>- depends on GPIO_P4_ENABLE<br>-# end of GPIO4<br>-<br>-# Begin of GPIO5<br>-config GPIO_P5_ENABLE<br>- bool "GPIO port 5 Enable"<br>- default n<br>-<br>-config GPIO_P5_DATA_ADDR<br>- hex "GPIO port 5 data address"<br>- depends on GPIO_P5_ENABLE<br>-<br>-config GPIO_P5_DIR_ADDR<br>- hex "GPIO port 5 direction address"<br>- depends on GPIO_P5_ENABLE<br>-<br>-config GPIO_P5_INIT_DIR<br>- hex "GPIO port 5 initial direction"<br>- default 0x00<br>- depends on GPIO_P5_ENABLE<br>-<br>-config GPIO_P5_INIT_DATA<br>- hex "GPIO port 5 initial data"<br>- depends on GPIO_P5_ENABLE<br>-# end of GPIO5<br>-<br>-# Begin of GPIO6<br>-config GPIO_P6_ENABLE<br>- bool "GPIO port 6 Enable"<br>- default n<br>-<br>-config GPIO_P6_DATA_ADDR<br>- hex "GPIO port 6 data address"<br>- depends on GPIO_P6_ENABLE<br>-<br>-config GPIO_P6_DIR_ADDR<br>- hex "GPIO port 6 direction address"<br>- depends on GPIO_P6_ENABLE<br>-<br>-config GPIO_P6_INIT_DIR<br>- hex "GPIO port 6 initial direction"<br>- default 0x00<br>- depends on GPIO_P6_ENABLE<br>-<br>-config GPIO_P6_INIT_DATA<br>- hex "GPIO port 6 initial data"<br>- depends on GPIO_P6_ENABLE<br>-# end of GPIO6<br>-<br>-# Begin of GPIO7<br>-config GPIO_P7_ENABLE<br>- bool "GPIO port 7 Enable"<br>- default n<br>-<br>-config GPIO_P7_DATA_ADDR<br>- hex "GPIO port 7 data address"<br>- depends on GPIO_P7_ENABLE<br>-<br>-config GPIO_P7_DIR_ADDR<br>- hex "GPIO port 7 direction address"<br>- depends on GPIO_P7_ENABLE<br>-<br>-config GPIO_P7_INIT_DIR<br>- hex "GPIO port 7 initial direction"<br>- default 0x00<br>- depends on GPIO_P7_ENABLE<br>-<br>-config GPIO_P7_INIT_DATA<br>- hex "GPIO port 7 initial data"<br>- depends on GPIO_P7_ENABLE<br>-# end of GPIO7<br>-<br>-# Begin of GPIO8<br>-config GPIO_P8_ENABLE<br>- bool "GPIO port 8 Enable"<br>- default n<br>-<br>-config GPIO_P8_DATA_ADDR<br>- hex "GPIO port 8 data address"<br>- depends on GPIO_P8_ENABLE<br>-<br>-config GPIO_P8_DIR_ADDR<br>- hex "GPIO port 8 direction address"<br>- depends on GPIO_P8_ENABLE<br>-<br>-config GPIO_P8_INIT_DIR<br>- hex "GPIO port 8 initial direction"<br>- default 0x00<br>- depends on GPIO_P8_ENABLE<br>-<br>-config GPIO_P8_INIT_DATA<br>- hex "GPIO port 8 initial data"<br>- depends on GPIO_P8_ENABLE<br>-# end of GPIO8<br>-<br>-# Begin of GPIO9<br>-config GPIO_P9_ENABLE<br>- bool "GPIO port 9 Enable"<br>- default n<br>-<br>-config GPIO_P9_DATA_ADDR<br>- hex "GPIO port 9 data address"<br>- depends on GPIO_P9_ENABLE<br>-<br>-config GPIO_P9_DIR_ADDR<br>- hex "GPIO port 9 direction address"<br>- depends on GPIO_P9_ENABLE<br>-<br>-config GPIO_P9_INIT_DIR<br>- hex "GPIO port 9 initial direction"<br>- default 0x00<br>- depends on GPIO_P9_ENABLE<br>-<br>-config GPIO_P9_INIT_DATA<br>- hex "GPIO port 9 initial data"<br>- depends on GPIO_P9_ENABLE<br>-# end of GPIO9<br>-<br>-endmenu<br>-<br>-# UART setting :<br>-menu "UART setting"<br>-<br>-# Begin of UART1<br>-config UART1_ENABLE<br>- bool "UART1 Enable"<br>- default y<br>-<br>-choice<br>- prompt "UART1 I/O port"<br>- default UART1_IO_PORT_3F8<br>- depends on UART1_ENABLE<br>-<br>-config UART1_IO_PORT_3F8<br>- bool "0x3f8, COM1"<br>-config UART1_IO_PORT_2F8<br>- bool "0x2f8, COM2"<br>-config UART1_IO_PORT_3E8<br>- bool "0x3e8, COM3"<br>-config UART1_IO_PORT_2E8<br>- bool "0x2e8, COM4"<br>-config UART1_IO_PORT_OTHER<br>- bool "Other"<br>-<br>-endchoice<br>-<br>-config UART1_IO_PORT_OTHER_INPUT<br>- hex "UART1 I/O port"<br>- depends on UART1_ENABLE && UART1_IO_PORT_OTHER<br>-<br>-config UART1_IO<br>- hex<br>- depends on UART1_ENABLE<br>- default 0x3f8 if UART1_IO_PORT_3F8<br>- default 0x2f8 if UART1_IO_PORT_2F8<br>- default 0x3e8 if UART1_IO_PORT_3E8<br>- default 0x2e8 if UART1_IO_PORT_2E8<br>- default UART1_IO_PORT_OTHER_INPUT if UART1_IO_PORT_OTHER<br>-<br>-choice<br>- prompt "UART1 IRQ"<br>- default UART1_IRQ4<br>- depends on UART1_ENABLE<br>-<br>-config UART1_IRQ_DISABLE<br>- bool "Disable"<br>-config UART1_IRQ3<br>- bool "IRQ3, COM2"<br>-config UART1_IRQ4<br>- bool "IRQ4, COM1"<br>-config UART1_IRQ5<br>- bool "IRQ5"<br>-config UART1_IRQ6<br>- bool "IRQ6"<br>-config UART1_IRQ7<br>- bool "IRQ7"<br>-config UART1_IRQ9<br>- bool "IRQ9"<br>-config UART1_IRQ10<br>- bool "IRQ10, COM3"<br>-config UART1_IRQ11<br>- bool "IRQ11, COM4"<br>-config UART1_IRQ12<br>- bool "IRQ12"<br>-config UART1_IRQ14<br>- bool "IRQ14"<br>-config UART1_IRQ15<br>- bool "IRQ15"<br>-<br>-endchoice<br>-<br>-config UART1_IRQ<br>- int<br>- depends on UART1_ENABLE<br>- default 0 if UART1_IRQ_DISABLE<br>- default 3 if UART1_IRQ3<br>- default 4 if UART1_IRQ4<br>- default 5 if UART1_IRQ5<br>- default 6 if UART1_IRQ6<br>- default 7 if UART1_IRQ7<br>- default 9 if UART1_IRQ9<br>- default 10 if UART1_IRQ10<br>- default 11 if UART1_IRQ11<br>- default 12 if UART1_IRQ12<br>- default 14 if UART1_IRQ14<br>- default 15 if UART1_IRQ15<br>-<br>-# end of UART1<br>-<br>-# Begin of UART2<br>-config UART2_ENABLE<br>- bool "UART2 Enable"<br>- default y<br>-<br>-choice<br>- prompt "UART2 I/O port"<br>- default UART2_IO_PORT_2F8<br>- depends on UART2_ENABLE<br>-<br>-config UART2_IO_PORT_3F8<br>- bool "0x3f8, COM1"<br>-config UART2_IO_PORT_2F8<br>- bool "0x2f8, COM2"<br>-config UART2_IO_PORT_3E8<br>- bool "0x3e8, COM3"<br>-config UART2_IO_PORT_2E8<br>- bool "0x2e8, COM4"<br>-config UART2_IO_PORT_OTHER<br>- bool "Other"<br>-<br>-endchoice<br>-<br>-config UART2_IO_PORT_OTHER_INPUT<br>- hex "UART2 I/O port"<br>- depends on UART2_ENABLE && UART2_IO_PORT_OTHER<br>-<br>-config UART2_IO<br>- hex<br>- depends on UART2_ENABLE<br>- default 0x3f8 if UART2_IO_PORT_3F8<br>- default 0x2f8 if UART2_IO_PORT_2F8<br>- default 0x3e8 if UART2_IO_PORT_3E8<br>- default 0x2e8 if UART2_IO_PORT_2E8<br>- default UART2_IO_PORT_OTHER_INPUT if UART2_IO_PORT_OTHER<br>-<br>-choice<br>- prompt "UART2 IRQ"<br>- default UART2_IRQ3<br>- depends on UART2_ENABLE<br>-<br>-config UART2_IRQ_DISABLE<br>- bool "Disable"<br>-config UART2_IRQ3<br>- bool "IRQ3, COM2"<br>-config UART2_IRQ4<br>- bool "IRQ4, COM1"<br>-config UART2_IRQ5<br>- bool "IRQ5"<br>-config UART2_IRQ6<br>- bool "IRQ6"<br>-config UART2_IRQ7<br>- bool "IRQ7"<br>-config UART2_IRQ9<br>- bool "IRQ9"<br>-config UART2_IRQ10<br>- bool "IRQ10, COM3"<br>-config UART2_IRQ11<br>- bool "IRQ11, COM4"<br>-config UART2_IRQ12<br>- bool "IRQ12"<br>-config UART2_IRQ14<br>- bool "IRQ14"<br>-config UART2_IRQ15<br>- bool "IRQ15"<br>-<br>-endchoice<br>-<br>-config UART2_IRQ<br>- int<br>- depends on UART2_ENABLE<br>- default 0 if UART2_IRQ_DISABLE<br>- default 3 if UART2_IRQ3<br>- default 4 if UART2_IRQ4<br>- default 5 if UART2_IRQ5<br>- default 6 if UART2_IRQ6<br>- default 7 if UART2_IRQ7<br>- default 9 if UART2_IRQ9<br>- default 10 if UART2_IRQ10<br>- default 11 if UART2_IRQ11<br>- default 12 if UART2_IRQ12<br>- default 14 if UART2_IRQ14<br>- default 15 if UART2_IRQ15<br>-<br>-# end of UART2<br>-<br>-# Begin of UART3<br>-config UART3_ENABLE<br>- bool "UART3 Enable"<br>- default y<br>-<br>-choice<br>- prompt "UART3 I/O port"<br>- default UART3_IO_PORT_3E8<br>- depends on UART3_ENABLE<br>-<br>-config UART3_IO_PORT_3F8<br>- bool "0x3f8, COM1"<br>-config UART3_IO_PORT_2F8<br>- bool "0x2f8, COM2"<br>-config UART3_IO_PORT_3E8<br>- bool "0x3e8, COM3"<br>-config UART3_IO_PORT_2E8<br>- bool "0x2e8, COM4"<br>-config UART3_IO_PORT_OTHER<br>- bool "Other"<br>-<br>-endchoice<br>-<br>-config UART3_IO_PORT_OTHER_INPUT<br>- hex "UART3 I/O port"<br>- depends on UART3_ENABLE && UART3_IO_PORT_OTHER<br>-<br>-config UART3_IO<br>- hex<br>- depends on UART3_ENABLE<br>- default 0x3f8 if UART3_IO_PORT_3F8<br>- default 0x2f8 if UART3_IO_PORT_2F8<br>- default 0x3e8 if UART3_IO_PORT_3E8<br>- default 0x2e8 if UART3_IO_PORT_2E8<br>- default UART3_IO_PORT_OTHER_INPUT if UART3_IO_PORT_OTHER<br>-<br>-choice<br>- prompt "UART3 IRQ"<br>- default UART3_IRQ10<br>- depends on UART3_ENABLE<br>-<br>-config UART3_IRQ_DISABLE<br>- bool "Disable"<br>-config UART3_IRQ3<br>- bool "IRQ3, COM2"<br>-config UART3_IRQ4<br>- bool "IRQ4, COM1"<br>-config UART3_IRQ5<br>- bool "IRQ5"<br>-config UART3_IRQ6<br>- bool "IRQ6"<br>-config UART3_IRQ7<br>- bool "IRQ7"<br>-config UART3_IRQ9<br>- bool "IRQ9"<br>-config UART3_IRQ10<br>- bool "IRQ10, COM3"<br>-config UART3_IRQ11<br>- bool "IRQ11, COM4"<br>-config UART3_IRQ12<br>- bool "IRQ12"<br>-config UART3_IRQ14<br>- bool "IRQ14"<br>-config UART3_IRQ15<br>- bool "IRQ15"<br>-<br>-endchoice<br>-<br>-config UART3_IRQ<br>- int<br>- depends on UART3_ENABLE<br>- default 0 if UART3_IRQ_DISABLE<br>- default 3 if UART3_IRQ3<br>- default 4 if UART3_IRQ4<br>- default 5 if UART3_IRQ5<br>- default 6 if UART3_IRQ6<br>- default 7 if UART3_IRQ7<br>- default 9 if UART3_IRQ9<br>- default 10 if UART3_IRQ10<br>- default 11 if UART3_IRQ11<br>- default 12 if UART3_IRQ12<br>- default 14 if UART3_IRQ14<br>- default 15 if UART3_IRQ15<br>-<br>-# end of UART3<br>-<br>-# Begin of UART4<br>-config UART4_ENABLE<br>- bool "UART4 Enable"<br>- default y<br>-<br>-choice<br>- prompt "UART4 I/O port"<br>- default UART4_IO_PORT_2E8<br>- depends on UART4_ENABLE<br>-<br>-config UART4_IO_PORT_3F8<br>- bool "0x3f8, COM1"<br>-config UART4_IO_PORT_2F8<br>- bool "0x2f8, COM2"<br>-config UART4_IO_PORT_3E8<br>- bool "0x3e8, COM3"<br>-config UART4_IO_PORT_2E8<br>- bool "0x2e8, COM4"<br>-config UART4_IO_PORT_OTHER<br>- bool "Other"<br>-<br>-endchoice<br>-<br>-config UART4_IO_PORT_OTHER_INPUT<br>- hex "UART4 I/O port"<br>- depends on UART4_ENABLE && UART4_IO_PORT_OTHER<br>-<br>-config UART4_IO<br>- hex<br>- depends on UART4_ENABLE<br>- default 0x3f8 if UART4_IO_PORT_3F8<br>- default 0x2f8 if UART4_IO_PORT_2F8<br>- default 0x3e8 if UART4_IO_PORT_3E8<br>- default 0x2e8 if UART4_IO_PORT_2E8<br>- default UART4_IO_PORT_OTHER_INPUT if UART4_IO_PORT_OTHER<br>-<br>-choice<br>- prompt "UART4 IRQ"<br>- default UART4_IRQ11<br>- depends on UART4_ENABLE<br>-<br>-config UART4_IRQ_DISABLE<br>- bool "Disable"<br>-config UART4_IRQ3<br>- bool "IRQ3, COM2"<br>-config UART4_IRQ4<br>- bool "IRQ4, COM1"<br>-config UART4_IRQ5<br>- bool "IRQ5"<br>-config UART4_IRQ6<br>- bool "IRQ6"<br>-config UART4_IRQ7<br>- bool "IRQ7"<br>-config UART4_IRQ9<br>- bool "IRQ9"<br>-config UART4_IRQ10<br>- bool "IRQ10, COM3"<br>-config UART4_IRQ11<br>- bool "IRQ11, COM4"<br>-config UART4_IRQ12<br>- bool "IRQ12"<br>-config UART4_IRQ14<br>- bool "IRQ14"<br>-config UART4_IRQ15<br>- bool "IRQ15"<br>-<br>-endchoice<br>-<br>-config UART4_IRQ<br>- int<br>- depends on UART4_ENABLE<br>- default 0 if UART4_IRQ_DISABLE<br>- default 3 if UART4_IRQ3<br>- default 4 if UART4_IRQ4<br>- default 5 if UART4_IRQ5<br>- default 6 if UART4_IRQ6<br>- default 7 if UART4_IRQ7<br>- default 9 if UART4_IRQ9<br>- default 10 if UART4_IRQ10<br>- default 11 if UART4_IRQ11<br>- default 12 if UART4_IRQ12<br>- default 14 if UART4_IRQ14<br>- default 15 if UART4_IRQ15<br>-<br>-# end of UART4<br>-<br>-# Begin of UART5<br>-config UART5_ENABLE<br>- bool "UART5 Enable"<br>- default n<br>-<br>-choice<br>- prompt "UART5 I/O port"<br>- default UART5_IO_PORT_OTHER<br>- depends on UART5_ENABLE<br>-<br>-config UART5_IO_PORT_3F8<br>- bool "0x3f8, COM1"<br>-config UART5_IO_PORT_2F8<br>- bool "0x2f8, COM2"<br>-config UART5_IO_PORT_3E8<br>- bool "0x3e8, COM3"<br>-config UART5_IO_PORT_2E8<br>- bool "0x2e8, COM4"<br>-config UART5_IO_PORT_OTHER<br>- bool "Other"<br>-<br>-endchoice<br>-<br>-config UART5_IO_PORT_OTHER_INPUT<br>- hex "UART5 I/O port"<br>- depends on UART5_ENABLE && UART5_IO_PORT_OTHER<br>-<br>-config UART5_IO<br>- hex<br>- depends on UART5_ENABLE<br>- default 0x3f8 if UART5_IO_PORT_3F8<br>- default 0x2f8 if UART5_IO_PORT_2F8<br>- default 0x3e8 if UART5_IO_PORT_3E8<br>- default 0x2e8 if UART5_IO_PORT_2E8<br>- default UART5_IO_PORT_OTHER_INPUT if UART5_IO_PORT_OTHER<br>-<br>-choice<br>- prompt "UART5 IRQ"<br>- default UART5_IRQ_DISABLE<br>- depends on UART5_ENABLE<br>-<br>-config UART5_IRQ_DISABLE<br>- bool "Disable"<br>-config UART5_IRQ3<br>- bool "IRQ3, COM2"<br>-config UART5_IRQ4<br>- bool "IRQ4, COM1"<br>-config UART5_IRQ5<br>- bool "IRQ5"<br>-config UART5_IRQ6<br>- bool "IRQ6"<br>-config UART5_IRQ7<br>- bool "IRQ7"<br>-config UART5_IRQ9<br>- bool "IRQ9"<br>-config UART5_IRQ10<br>- bool "IRQ10, COM3"<br>-config UART5_IRQ11<br>- bool "IRQ11, COM4"<br>-config UART5_IRQ12<br>- bool "IRQ12"<br>-config UART5_IRQ14<br>- bool "IRQ14"<br>-config UART5_IRQ15<br>- bool "IRQ15"<br>-<br>-endchoice<br>-<br>-config UART5_IRQ<br>- int<br>- depends on UART5_ENABLE<br>- default 0 if UART5_IRQ_DISABLE<br>- default 3 if UART5_IRQ3<br>- default 4 if UART5_IRQ4<br>- default 5 if UART5_IRQ5<br>- default 6 if UART5_IRQ6<br>- default 7 if UART5_IRQ7<br>- default 9 if UART5_IRQ9<br>- default 10 if UART5_IRQ10<br>- default 11 if UART5_IRQ11<br>- default 12 if UART5_IRQ12<br>- default 14 if UART5_IRQ14<br>- default 15 if UART5_IRQ15<br>-<br>-# end of UART5<br>-<br>-# Begin of UART6<br>-config UART6_ENABLE<br>- bool "UART6 Enable"<br>- default n<br>-<br>-choice<br>- prompt "UART6 I/O port"<br>- default UART6_IO_PORT_OTHER<br>- depends on UART6_ENABLE<br>-<br>-config UART6_IO_PORT_3F8<br>- bool "0x3f8, COM1"<br>-config UART6_IO_PORT_2F8<br>- bool "0x2f8, COM2"<br>-config UART6_IO_PORT_3E8<br>- bool "0x3e8, COM3"<br>-config UART6_IO_PORT_2E8<br>- bool "0x2e8, COM4"<br>-config UART6_IO_PORT_OTHER<br>- bool "Other"<br>-<br>-endchoice<br>-<br>-config UART6_IO_PORT_OTHER_INPUT<br>- hex "UART6 I/O port"<br>- depends on UART6_ENABLE && UART6_IO_PORT_OTHER<br>-<br>-config UART6_IO<br>- hex<br>- depends on UART6_ENABLE<br>- default 0x3f8 if UART6_IO_PORT_3F8<br>- default 0x2f8 if UART6_IO_PORT_2F8<br>- default 0x3e8 if UART6_IO_PORT_3E8<br>- default 0x2e8 if UART6_IO_PORT_2E8<br>- default UART6_IO_PORT_OTHER_INPUT if UART6_IO_PORT_OTHER<br>-<br>-choice<br>- prompt "UART6 IRQ"<br>- default UART6_IRQ_DISABLE<br>- depends on UART6_ENABLE<br>-<br>-config UART6_IRQ_DISABLE<br>- bool "Disable"<br>-config UART6_IRQ3<br>- bool "IRQ3, COM2"<br>-config UART6_IRQ4<br>- bool "IRQ4, COM1"<br>-config UART6_IRQ5<br>- bool "IRQ5"<br>-config UART6_IRQ6<br>- bool "IRQ6"<br>-config UART6_IRQ7<br>- bool "IRQ7"<br>-config UART6_IRQ9<br>- bool "IRQ9"<br>-config UART6_IRQ10<br>- bool "IRQ10, COM3"<br>-config UART6_IRQ11<br>- bool "IRQ11, COM4"<br>-config UART6_IRQ12<br>- bool "IRQ12"<br>-config UART6_IRQ14<br>- bool "IRQ14"<br>-config UART6_IRQ15<br>- bool "IRQ15"<br>-<br>-endchoice<br>-<br>-config UART6_IRQ<br>- int<br>- depends on UART6_ENABLE<br>- default 0 if UART6_IRQ_DISABLE<br>- default 3 if UART6_IRQ3<br>- default 4 if UART6_IRQ4<br>- default 5 if UART6_IRQ5<br>- default 6 if UART6_IRQ6<br>- default 7 if UART6_IRQ7<br>- default 9 if UART6_IRQ9<br>- default 10 if UART6_IRQ10<br>- default 11 if UART6_IRQ11<br>- default 12 if UART6_IRQ12<br>- default 14 if UART6_IRQ14<br>- default 15 if UART6_IRQ15<br>-<br>-# end of UART6<br>-<br>-# Begin of UART7<br>-config UART7_ENABLE<br>- bool "UART7 Enable"<br>- default n<br>-<br>-choice<br>- prompt "UART7 I/O port"<br>- default UART7_IO_PORT_OTHER<br>- depends on UART7_ENABLE<br>-<br>-config UART7_IO_PORT_3F8<br>- bool "0x3f8, COM1"<br>-config UART7_IO_PORT_2F8<br>- bool "0x2f8, COM2"<br>-config UART7_IO_PORT_3E8<br>- bool "0x3e8, COM3"<br>-config UART7_IO_PORT_2E8<br>- bool "0x2e8, COM4"<br>-config UART7_IO_PORT_OTHER<br>- bool "Other"<br>-<br>-endchoice<br>-<br>-config UART7_IO_PORT_OTHER_INPUT<br>- hex "UART7 I/O port"<br>- depends on UART7_ENABLE && UART7_IO_PORT_OTHER<br>-<br>-config UART7_IO<br>- hex<br>- depends on UART7_ENABLE<br>- default 0x3f8 if UART7_IO_PORT_3F8<br>- default 0x2f8 if UART7_IO_PORT_2F8<br>- default 0x3e8 if UART7_IO_PORT_3E8<br>- default 0x2e8 if UART7_IO_PORT_2E8<br>- default UART7_IO_PORT_OTHER_INPUT if UART7_IO_PORT_OTHER<br>-<br>-choice<br>- prompt "UART7 IRQ"<br>- default UART7_IRQ_DISABLE<br>- depends on UART7_ENABLE<br>-<br>-config UART7_IRQ_DISABLE<br>- bool "Disable"<br>-config UART7_IRQ3<br>- bool "IRQ3, COM2"<br>-config UART7_IRQ4<br>- bool "IRQ4, COM1"<br>-config UART7_IRQ5<br>- bool "IRQ5"<br>-config UART7_IRQ6<br>- bool "IRQ6"<br>-config UART7_IRQ7<br>- bool "IRQ7"<br>-config UART7_IRQ9<br>- bool "IRQ9"<br>-config UART7_IRQ10<br>- bool "IRQ10, COM3"<br>-config UART7_IRQ11<br>- bool "IRQ11, COM4"<br>-config UART7_IRQ12<br>- bool "IRQ12"<br>-config UART7_IRQ14<br>- bool "IRQ14"<br>-config UART7_IRQ15<br>- bool "IRQ15"<br>-<br>-endchoice<br>-<br>-config UART7_IRQ<br>- int<br>- depends on UART7_ENABLE<br>- default 0 if UART7_IRQ_DISABLE<br>- default 3 if UART7_IRQ3<br>- default 4 if UART7_IRQ4<br>- default 5 if UART7_IRQ5<br>- default 6 if UART7_IRQ6<br>- default 7 if UART7_IRQ7<br>- default 9 if UART7_IRQ9<br>- default 10 if UART7_IRQ10<br>- default 11 if UART7_IRQ11<br>- default 12 if UART7_IRQ12<br>- default 14 if UART7_IRQ14<br>- default 15 if UART7_IRQ15<br>-<br>-# end of UART7<br>-<br>-# Begin of UART8<br>-config UART8_ENABLE<br>- bool "UART8 Enable"<br>- default n<br>-<br>-choice<br>- prompt "UART8 I/O port"<br>- default UART8_IO_PORT_OTHER<br>- depends on UART8_ENABLE<br>-<br>-config UART8_IO_PORT_3F8<br>- bool "0x3f8, COM1"<br>-config UART8_IO_PORT_2F8<br>- bool "0x2f8, COM2"<br>-config UART8_IO_PORT_3E8<br>- bool "0x3e8, COM3"<br>-config UART8_IO_PORT_2E8<br>- bool "0x2e8, COM4"<br>-config UART8_IO_PORT_OTHER<br>- bool "Other"<br>-<br>-endchoice<br>-<br>-config UART8_IO_PORT_OTHER_INPUT<br>- hex "UART8 I/O port"<br>- depends on UART8_ENABLE && UART8_IO_PORT_OTHER<br>-<br>-config UART8_IO<br>- hex<br>- depends on UART8_ENABLE<br>- default 0x3f8 if UART8_IO_PORT_3F8<br>- default 0x2f8 if UART8_IO_PORT_2F8<br>- default 0x3e8 if UART8_IO_PORT_3E8<br>- default 0x2e8 if UART8_IO_PORT_2E8<br>- default UART8_IO_PORT_OTHER_INPUT if UART8_IO_PORT_OTHER<br>-<br>-choice<br>- prompt "UART8 IRQ"<br>- default UART8_IRQ_DISABLE<br>- depends on UART8_ENABLE<br>-<br>-config UART8_IRQ_DISABLE<br>- bool "Disable"<br>-config UART8_IRQ3<br>- bool "IRQ3, COM2"<br>-config UART8_IRQ4<br>- bool "IRQ4, COM1"<br>-config UART8_IRQ5<br>- bool "IRQ5"<br>-config UART8_IRQ6<br>- bool "IRQ6"<br>-config UART8_IRQ7<br>- bool "IRQ7"<br>-config UART8_IRQ9<br>- bool "IRQ9"<br>-config UART8_IRQ10<br>- bool "IRQ10, COM3"<br>-config UART8_IRQ11<br>- bool "IRQ11, COM4"<br>-config UART8_IRQ12<br>- bool "IRQ12"<br>-config UART8_IRQ14<br>- bool "IRQ14"<br>-config UART8_IRQ15<br>- bool "IRQ15"<br>-<br>-endchoice<br>-<br>-config UART8_IRQ<br>- int<br>- depends on UART8_ENABLE<br>- default 0 if UART8_IRQ_DISABLE<br>- default 3 if UART8_IRQ3<br>- default 4 if UART8_IRQ4<br>- default 5 if UART8_IRQ5<br>- default 6 if UART8_IRQ6<br>- default 7 if UART8_IRQ7<br>- default 9 if UART8_IRQ9<br>- default 10 if UART8_IRQ10<br>- default 11 if UART8_IRQ11<br>- default 12 if UART8_IRQ12<br>- default 14 if UART8_IRQ14<br>- default 15 if UART8_IRQ15<br>-<br>-# end of UART8<br>-<br>-# Begin of UART9<br>-config UART9_ENABLE<br>- bool "UART9 Enable"<br>- default n<br>-<br>-choice<br>- prompt "UART9 I/O port"<br>- default UART9_IO_PORT_OTHER<br>- depends on UART9_ENABLE<br>-<br>-config UART9_IO_PORT_3F8<br>- bool "0x3f8, COM1"<br>-config UART9_IO_PORT_2F8<br>- bool "0x2f8, COM2"<br>-config UART9_IO_PORT_3E8<br>- bool "0x3e8, COM3"<br>-config UART9_IO_PORT_2E8<br>- bool "0x2e8, COM4"<br>-config UART9_IO_PORT_OTHER<br>- bool "Other"<br>-<br>-endchoice<br>-<br>-config UART9_IO_PORT_OTHER_INPUT<br>- hex "UART9 I/O port"<br>- depends on UART9_ENABLE && UART9_IO_PORT_OTHER<br>-<br>-config UART9_IO<br>- hex<br>- depends on UART9_ENABLE<br>- default 0x3f8 if UART9_IO_PORT_3F8<br>- default 0x2f8 if UART9_IO_PORT_2F8<br>- default 0x3e8 if UART9_IO_PORT_3E8<br>- default 0x2e8 if UART9_IO_PORT_2E8<br>- default UART9_IO_PORT_OTHER_INPUT if UART9_IO_PORT_OTHER<br>-<br>-choice<br>- prompt "UART9 IRQ"<br>- default UART9_IRQ_DISABLE<br>- depends on UART9_ENABLE<br>-<br>-config UART9_IRQ_DISABLE<br>- bool "Disable"<br>-config UART9_IRQ3<br>- bool "IRQ3, COM2"<br>-config UART9_IRQ4<br>- bool "IRQ4, COM1"<br>-config UART9_IRQ5<br>- bool "IRQ5"<br>-config UART9_IRQ6<br>- bool "IRQ6"<br>-config UART9_IRQ7<br>- bool "IRQ7"<br>-config UART9_IRQ9<br>- bool "IRQ9"<br>-config UART9_IRQ10<br>- bool "IRQ10, COM3"<br>-config UART9_IRQ11<br>- bool "IRQ11, COM4"<br>-config UART9_IRQ12<br>- bool "IRQ12"<br>-config UART9_IRQ14<br>- bool "IRQ14"<br>-config UART9_IRQ15<br>- bool "IRQ15"<br>-<br>-endchoice<br>-<br>-config UART9_IRQ<br>- int<br>- depends on UART9_ENABLE<br>- default 0 if UART9_IRQ_DISABLE<br>- default 3 if UART9_IRQ3<br>- default 4 if UART9_IRQ4<br>- default 5 if UART9_IRQ5<br>- default 6 if UART9_IRQ6<br>- default 7 if UART9_IRQ7<br>- default 9 if UART9_IRQ9<br>- default 10 if UART9_IRQ10<br>- default 11 if UART9_IRQ11<br>- default 12 if UART9_IRQ12<br>- default 14 if UART9_IRQ14<br>- default 15 if UART9_IRQ15<br>-<br>-# end of UART9<br>-<br>-# Begin of UART10<br>-config UART10_ENABLE<br>- bool "UART10 Enable"<br>- default n<br>-<br>-choice<br>- prompt "UART10 I/O port"<br>- default UART10_IO_PORT_OTHER<br>- depends on UART10_ENABLE<br>-<br>-config UART10_IO_PORT_3F8<br>- bool "0x3f8, COM1"<br>-config UART10_IO_PORT_2F8<br>- bool "0x2f8, COM2"<br>-config UART10_IO_PORT_3E8<br>- bool "0x3e8, COM3"<br>-config UART10_IO_PORT_2E8<br>- bool "0x2e8, COM4"<br>-config UART10_IO_PORT_OTHER<br>- bool "Other"<br>-<br>-endchoice<br>-<br>-config UART10_IO_PORT_OTHER_INPUT<br>- hex "UART10 I/O port"<br>- depends on UART10_ENABLE && UART10_IO_PORT_OTHER<br>-<br>-config UART10_IO<br>- hex<br>- depends on UART10_ENABLE<br>- default 0x3f8 if UART10_IO_PORT_3F8<br>- default 0x2f8 if UART10_IO_PORT_2F8<br>- default 0x3e8 if UART10_IO_PORT_3E8<br>- default 0x2e8 if UART10_IO_PORT_2E8<br>- default UART10_IO_PORT_OTHER_INPUT if UART10_IO_PORT_OTHER<br>-<br>-choice<br>- prompt "UART10 IRQ"<br>- default UART10_IRQ_DISABLE<br>- depends on UART10_ENABLE<br>-<br>-config UART10_IRQ_DISABLE<br>- bool "Disable"<br>-config UART10_IRQ3<br>- bool "IRQ3, COM2"<br>-config UART10_IRQ4<br>- bool "IRQ4, COM1"<br>-config UART10_IRQ5<br>- bool "IRQ5"<br>-config UART10_IRQ6<br>- bool "IRQ6"<br>-config UART10_IRQ7<br>- bool "IRQ7"<br>-config UART10_IRQ9<br>- bool "IRQ9"<br>-config UART10_IRQ10<br>- bool "IRQ10, COM3"<br>-config UART10_IRQ11<br>- bool "IRQ11, COM4"<br>-config UART10_IRQ12<br>- bool "IRQ12"<br>-config UART10_IRQ14<br>- bool "IRQ14"<br>-config UART10_IRQ15<br>- bool "IRQ15"<br>-<br>-endchoice<br>-<br>-config UART10_IRQ<br>- int<br>- depends on UART10_ENABLE<br>- default 0 if UART10_IRQ_DISABLE<br>- default 3 if UART10_IRQ3<br>- default 4 if UART10_IRQ4<br>- default 5 if UART10_IRQ5<br>- default 6 if UART10_IRQ6<br>- default 7 if UART10_IRQ7<br>- default 9 if UART10_IRQ9<br>- default 10 if UART10_IRQ10<br>- default 11 if UART10_IRQ11<br>- default 12 if UART10_IRQ12<br>- default 14 if UART10_IRQ14<br>- default 15 if UART10_IRQ15<br>-<br>-# end of UART10<br>-<br>-endmenu<br>-<br>-# LPT setting :<br>-menu "LPT setting"<br>-<br>-# Begin of LPT<br>-config LPT_ENABLE<br>- bool "LPT Enable"<br>- default n<br>-<br>-choice<br>- prompt "LPT I/O port"<br>- default LPT_IO_PORT_278<br>- depends on LPT_ENABLE<br>-<br>-config LPT_IO_PORT_378<br>- bool "0x378, LPT1"<br>-config LPT_IO_PORT_278<br>- bool "0x278, LPT2"<br>-config LPT_IO_PORT_OTHER<br>- bool "Other"<br>-<br>-endchoice<br>-<br>-config LPT_IO_PORT_OTHER_INPUT<br>- hex "LPT I/O port"<br>- depends on LPT_ENABLE && LPT_IO_PORT_OTHER<br>-<br>-config LPT_IO<br>- hex<br>- depends on LPT_ENABLE<br>- default 0x378 if LPT_IO_PORT_378<br>- default 0x278 if LPT_IO_PORT_278<br>- default LPT_IO_PORT_OTHER_INPUT if LPT_IO_PORT_OTHER<br>-<br>-choice<br>- prompt "LPT IRQ"<br>- default LPT_IRQ_DISABLE<br>- depends on LPT_ENABLE<br>-<br>-config LPT_IRQ_DISABLE<br>- bool "Disable"<br>-config LPT_IRQ3<br>- bool "IRQ3"<br>-config LPT_IRQ4<br>- bool "IRQ4"<br>-config LPT_IRQ5<br>- bool "IRQ5"<br>-config LPT_IRQ6<br>- bool "IRQ6"<br>-config LPT_IRQ7<br>- bool "IRQ7"<br>-config LPT_IRQ9<br>- bool "IRQ9"<br>-config LPT_IRQ10<br>- bool "IRQ10"<br>-config LPT_IRQ11<br>- bool "IRQ11"<br>-config LPT_IRQ12<br>- bool "IRQ12"<br>-config LPT_IRQ14<br>- bool "IRQ14"<br>-config LPT_IRQ15<br>- bool "IRQ15"<br>-<br>-endchoice<br>-<br>-config LPT_IRQ<br>- int<br>- depends on LPT_ENABLE<br>- default 0 if LPT_IRQ_DISABLE<br>- default 3 if LPT_IRQ3<br>- default 4 if LPT_IRQ4<br>- default 5 if LPT_IRQ5<br>- default 6 if LPT_IRQ6<br>- default 7 if LPT_IRQ7<br>- default 9 if LPT_IRQ9<br>- default 10 if LPT_IRQ10<br>- default 11 if LPT_IRQ11<br>- default 12 if LPT_IRQ12<br>- default 14 if LPT_IRQ14<br>- default 15 if LPT_IRQ15<br>-<br>-choice<br>- prompt "LPT Mode Setting"<br>- default LPT_MODE_SPP<br>- depends on LPT_ENABLE<br>-<br>-config LPT_MODE_BPP<br>- bool "BPP mode"<br>-config LPT_MODE_EPP_19_AND_SPP<br>- bool "EPP 1.9 and SPP mode"<br>-config LPT_MODE_ECP<br>- bool "ECP Mode"<br>-config LPT_MODE_ECP_AND_EPP_19<br>- bool "ECP and EPP 1.9 mode"<br>-config LPT_MODE_SPP<br>- bool "SPP Mode"<br>-config LPT_MODE_EPP_17_AND_SPP<br>- bool "EPP 1.7 and SPP mode"<br>-config LPT_MODE_ECP_AND_EPP_17<br>- bool "ECP and EPP 1.7 mode"<br>-<br>-endchoice<br>-<br>-# end of LPT<br>-<br>-endmenu<br>-<br>-endif # BOARD_DMP_EX<br>diff --git a/src/mainboard/dmp/vortex86ex/Kconfig.name b/src/mainboard/dmp/vortex86ex/Kconfig.name<br>deleted file mode 100644<br>index 8e1a564..0000000<br>--- a/src/mainboard/dmp/vortex86ex/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_DMP_EX<br>- bool "Vortex86EX"<br>diff --git a/src/mainboard/dmp/vortex86ex/board_info.txt b/src/mainboard/dmp/vortex86ex/board_info.txt<br>deleted file mode 100644<br>index c67b641..0000000<br>--- a/src/mainboard/dmp/vortex86ex/board_info.txt<br>+++ /dev/null<br>@@ -1 +0,0 @@<br>-Category: sbc<br>diff --git a/src/mainboard/dmp/vortex86ex/devicetree.cb b/src/mainboard/dmp/vortex86ex/devicetree.cb<br>deleted file mode 100644<br>index 4106bed..0000000<br>--- a/src/mainboard/dmp/vortex86ex/devicetree.cb<br>+++ /dev/null<br>@@ -1,28 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2013 DMP Electronics Inc.<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-chip soc/dmp/vortex86ex # North Bridge<br>- device domain 0 on<br>- device pci 0.0 on end # Host Bridge<br>- device pci 7.0 on end # ISA Bridge<br>- device pci 8.0 on end # Ethernet<br>- device pci a.0 on end # USB 1.1<br>- device pci a.1 on end # USB 2.0<br>- device pci b.0 on end # USB 1.1<br>- device pci b.1 on end # USB 2.0<br>- device pci c.0 on end # IDE<br>- end # pci domain 0<br>- chip cpu/dmp/vortex86ex end # CPU<br>-end<br>diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.c b/src/mainboard/dmp/vortex86ex/hda_verb.c<br>deleted file mode 100644<br>index 5c72807..0000000<br>--- a/src/mainboard/dmp/vortex86ex/hda_verb.c<br>+++ /dev/null<br>@@ -1,64 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <device/azalia_device.h><br>-<br>-const u32 cim_verb_data[] = {<br>- /* coreboot specific header */<br>- 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262<br>- 0x10714700, // Subsystem ID<br>- 0x0000000f, // Number of jacks<br>-<br>- /* ===== HDA Codec Subsystem ID Verb-table ===== */<br>- /* HDA Codec Subsystem ID : 0x10EC0000 */<br>- AZALIA_SUBVENDOR(0x0, 0x10ec0000),<br>-<br>- /* ===== Pin Widget Verb-table ===== */<br>- /* Widget node 0x01 : */<br>- 0x0017ff00,<br>- 0x0017ff00,<br>- 0x0017ff00,<br>- 0x0017ff00,<br>- /* Pin widget 0x11 - S/PDIF-OUT2 */<br>- AZALIA_PIN_CFG(0x0, 0x11, 0x40000000),<br>- /* Pin widget 0x12 - DMIC */<br>- AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),<br>- /* Pin widget 0x14 - LINE-OUT (Port-D) */<br>- AZALIA_PIN_CFG(0x0, 0x14, 0x01014110),<br>- /* Pin widget 0x15 - HP-OUT (Port-A) */<br>- AZALIA_PIN_CFG(0x0, 0x15, 0x411111f0),<br>- /* Pin widget 0x16 - MONO-OUT */<br>- AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0),<br>- /* Pin widget 0x18 - MIC1 (Port-B) */<br>- AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),<br>- /* Pin widget 0x19 - MIC2 (Port-F) */<br>- AZALIA_PIN_CFG(0x0, 0x19, 0x02a19130),<br>- /* Pin widget 0x1A - LINE1 (Port-C) */<br>- AZALIA_PIN_CFG(0x0, 0x1a, 0x01813140),<br>- /* Pin widget 0x1B - LINE2 (Port-E) */<br>- AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),<br>- /* Pin widget 0x1C - CD-IN */<br>- AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),<br>- /* Pin widget 0x1D - BEEP-IN */<br>- AZALIA_PIN_CFG(0x0, 0x1d, 0x40354629),<br>- /* Pin widget 0x1E - S/PDIF-OUT */<br>- AZALIA_PIN_CFG(0x0, 0x1e, 0x18561120),<br>- /* Pin widget 0x1F - S/PDIF-IN */<br>- AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0),<br>-};<br>-<br>-const u32 pc_beep_verbs[0] = {};<br>-<br>-AZALIA_ARRAY_SIZES;<br>diff --git a/src/mainboard/dmp/vortex86ex/irq_tables.c b/src/mainboard/dmp/vortex86ex/irq_tables.c<br>deleted file mode 100644<br>index 9e4e77f..0000000<br>--- a/src/mainboard/dmp/vortex86ex/irq_tables.c<br>+++ /dev/null<br>@@ -1,53 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32 + 16 * 12, /* Max. number of devices on the bus */<br>- 0x00, /* Interrupt router bus */<br>- (0x07 << 3) | 0x0, /* Interrupt router dev */<br>- 0, /* IRQs devoted exclusively to PCI usage */<br>- 0x17f3, /* Vendor */<br>- 0x6031, /* Device */<br>- 0, /* Miniport */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0xa, /* Checksum (has to be set to some value that<br>- * would give 0 after the sum of all bytes<br>- * for this structure (including checksum).<br>- */<br>- {<br>- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x1, 0x0},<br>- {0x00, (0x02 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x2, 0x0},<br>- {0x00, (0x03 << 3) | 0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x0, 0x0},<br>- {0x00, (0x04 << 3) | 0x0, {{0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}}, 0x4, 0x0},<br>- {0x00, (0x05 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x5, 0x0},<br>- {0x00, (0x06 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x6, 0x0},<br>- {0x00, (0x08 << 3) | 0x0, {{0x05, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x0a << 3) | 0x0, {{0x07, 0xdef8}, {0x08, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x0b << 3) | 0x0, {{0x09, 0xdef8}, {0x0a, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x0c << 3) | 0x0, {{0x0b, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x0f << 3) | 0x0, {{0x0d, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x0e << 3) | 0x0, {{0x0e, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- }<br>-};<br>-<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c<br>deleted file mode 100644<br>index 108cc1d..0000000<br>--- a/src/mainboard/dmp/vortex86ex/romstage.c<br>+++ /dev/null<br>@@ -1,352 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2012 Andrew Wu <arw@dmp.com.tw><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <arch/io.h><br>-#include <stdlib.h><br>-#include "arch/x86/romcc_console.c"<br>-#include <console/console.h><br>-#include <cpu/x86/cache.h><br>-#include <halt.h><br>-#include "drivers/pc80/pc/i8254.c"<br>-#include <soc/dmp/vortex86ex/northbridge.h><br>-#include <soc/dmp/vortex86ex/southbridge.h><br>-#include "soc/dmp/vortex86ex/raminit.c"<br>-#include <cpu/dmp/dmp_post_code.h><br>-<br>-#define DMP_CPUID_SX 0x31504d44<br>-#define DMP_CPUID_DX 0x32504d44<br>-#define DMP_CPUID_MX 0x33504d44<br>-#define DMP_CPUID_DX2 0x34504d44<br>-#define DMP_CPUID_MX_PLUS 0x35504d44<br>-#define DMP_CPUID_EX 0x37504d44<br>-<br>-static u32 get_dmp_id(void)<br>-{<br>- return pci_read_config32(NB, NB_REG_CID);<br>-}<br>-<br>-/* Indirect access registers for Watch-dog timer, GPIO PORT 0,1<br>- * Index port is for I/O port 22h<br>- * Index port 13h (00: lock register, C5h: unlock register) for lock/unlock function<br>- * Index port 37h, 39h, 3Ah, 3Bh, 3Ch for Watchdog timer<br>- * Index port 46h, 47h, 4Ch, 4Dh, 4Eh, 4Fh for GPIO port 0, 1<br>- */<br>-static void write_indirect_reg(u8 index, u8 data)<br>-{<br>- outb(index, 0x22);<br>- outb(data, 0x23);<br>-}<br>-<br>-static void lock_indirect_reg(void)<br>-{<br>- write_indirect_reg(0x13, 0x00);<br>-}<br>-<br>-static void unlock_indirect_reg(void)<br>-{<br>- write_indirect_reg(0x13, 0xc5);<br>-}<br>-<br>-static void disable_watchdog(void)<br>-{<br>- unlock_indirect_reg();<br>- // disable watchdog timer<br>- write_indirect_reg(0x37, 0x0);<br>-}<br>-<br>-void set_ex_powerdown_control(void)<br>-{<br>- u32 powerdown_ctrl;<br>- powerdown_ctrl = pci_read_config32(SB, 0xbc);<br>-#if IS_ENABLED(CONFIG_TEMP_POWERDOWN)<br>- powerdown_ctrl |= (1 << 31);<br>-#endif<br>-#if IS_ENABLED(CONFIG_SATA_POWERDOWN)<br>- powerdown_ctrl |= (1 << 30);<br>-#endif<br>-#if IS_ENABLED(CONFIG_ADC_POWERDOWN)<br>- powerdown_ctrl |= (1 << 28);<br>-#endif<br>-#if IS_ENABLED(CONFIG_PCIE0_POWERDOWN)<br>- powerdown_ctrl |= (1 << 13);<br>-#endif<br>-#if IS_ENABLED(CONFIG_MAC_POWERDOWN)<br>- powerdown_ctrl |= (1 << 3);<br>-#endif<br>-#if IS_ENABLED(CONFIG_USB1_POWERDOWN)<br>- powerdown_ctrl |= (1 << 1);<br>-#endif<br>-#if IS_ENABLED(CONFIG_IDE_POWERDOWN)<br>- powerdown_ctrl |= (1 << 0);<br>-#endif<br>- pci_write_config32(SB, 0xbc, powerdown_ctrl);<br>-}<br>-<br>-static void set_pci_nb_pmcr(void)<br>-{<br>- u8 pmcr = pci_read_config8(NB, NB_REG_PMCR);<br>- /*<br>- * Set PCI Master Max Cycle Length (MCL) to 32 PCI clocks.<br>- * Set PCI Master Burst Write Length (BL) to Burst length over 3.<br>- */<br>- pmcr |= 0x0f;<br>- pci_write_config8(NB, NB_REG_PMCR, pmcr);<br>-}<br>-<br>-static void set_pci_sb_lpccr(void)<br>-{<br>- u8 lpccr = pci_read_config8(SB, SB_REG_LPCCR);<br>- /* Set PCI Soft Reset Control to 1.<br>- * (When the CPU soft reset is initialized, PCIRST# will be active.)<br>- * Set P92FE to 1. (I/O port 92 Register Write Function Enable.)<br>- * Set P92S to 1. (Internal Port 92h Selected.)<br>- */<br>- lpccr |= 0x16;<br>- pci_write_config8(SB, SB_REG_LPCCR, lpccr);<br>- /* enable fast ga20 */<br>- outb(inb(SYSTEM_CTL_PORT) | 0x02, SYSTEM_CTL_PORT);<br>-}<br>-<br>-static u32 make_uart_config(u16 base, u8 irq)<br>-{<br>- /* Set base IO address only, skip IRQ. IRQ will be setup in<br>- * southbridge stage. */<br>- u32 cfg = 0;<br>- cfg |= 1 << 23; // UE = enabled.<br>- cfg |= base; // UIOA.<br>- return cfg;<br>-}<br>-<br>-#define SETUP_UART(n) \<br>- uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\<br>- outl(uart_cfg, 0xc00 + (n - 1) * 4);<br>-<br>-static void ex_uart_early_init(void)<br>-{<br>-#if CONFIG_TTYS0_BASE<br>- u32 uart_cfg = 0;<br>- /* Set UART Config I/O base address to 0xc00 */<br>- pci_write_config16(SB, 0x60, 0xc01);<br>- /* If serial console base address is defined, find out which<br>- * UART uses this address, and setup this UART first. */<br>-#if CONFIG_TTYS0_BASE == CONFIG_UART1_IO<br>- SETUP_UART(1)<br>-#elif CONFIG_TTYS0_BASE == CONFIG_UART2_IO<br>- SETUP_UART(2)<br>-#elif CONFIG_TTYS0_BASE == CONFIG_UART3_IO<br>- SETUP_UART(3)<br>-#elif CONFIG_TTYS0_BASE == CONFIG_UART4_IO<br>- SETUP_UART(4)<br>-#elif CONFIG_TTYS0_BASE == CONFIG_UART5_IO<br>- SETUP_UART(5)<br>-#elif CONFIG_TTYS0_BASE == CONFIG_UART6_IO<br>- SETUP_UART(6)<br>-#elif CONFIG_TTYS0_BASE == CONFIG_UART7_IO<br>- SETUP_UART(7)<br>-#elif CONFIG_TTYS0_BASE == CONFIG_UART8_IO<br>- SETUP_UART(8)<br>-#elif CONFIG_TTYS0_BASE == CONFIG_UART9_IO<br>- SETUP_UART(9)<br>-#elif CONFIG_TTYS0_BASE == CONFIG_UART10_IO<br>- SETUP_UART(10)<br>-#endif<br>-#endif<br>-}<br>-<br>-static void init_wdt1(void)<br>-{<br>-#if IS_ENABLED(CONFIG_WDT1_INITIALIZE)<br>-#if IS_ENABLED(CONFIG_WDT1_ENABLE)<br>- outb(0x1 << 6, 0xa8);<br>-#endif<br>- u8 wdt1_signal_reg = 0;<br>-#if IS_ENABLED(CONFIG_WDT1_SINGAL_NMI)<br>- wdt1_signal_reg = 0x0c << 4;<br>-#elif IS_ENABLED(CONFIG_WDT1_SIGNAL_RESET)<br>- wdt1_signal_reg = 0x0d << 4;<br>-#elif IS_ENABLED(CONFIG_WDT1_SIGNAL_SMI)<br>- wdt1_signal_reg = 0x0e << 4;<br>-#endif<br>- outb(wdt1_signal_reg, 0xa9);<br>-#endif<br>-}<br>-<br>-/* Fill 32bit pattern into specified DRAM region. */<br>-static void fill_dram(u32 * p, u32 pattern, u32 test_len)<br>-{<br>- if (test_len == 0)<br>- return;<br>-#if 0<br>- // C version, very slow.<br>- for (p = (u32 *) 0; (u32) p < test_len; p++) {<br>- *p = pattern;<br>- }<br>-#endif<br>- // ASM version, much faster.<br>- asm volatile (<br>- "cld\n\t"<br>- "rep\n\t"<br>- "stosl"<br>- : /* no output registers */<br>- : "c" (test_len / 4), "a" (pattern), "D" (p)<br>- );<br>-}<br>-<br>-/* Verify 32bit pattern in specified DRAM region.<br>- * Return -1 if ok, failed memory address if error. */<br>-static int verify_dram(u32 * p, u32 pattern, u32 test_len)<br>-{<br>- if (test_len == 0)<br>- return -1;<br>-#if 0<br>- // C version, very slow.<br>- for (p = (u32 *) 0; (u32) p < test_len; p++) {<br>- if (*p != pattern) {<br>- return (int)p;<br>- }<br>- }<br>- return -1;<br>-#endif<br>- u16 flags;<br>- int addr;<br>- asm volatile (<br>- "cld\n\t"<br>- "rep\n\t"<br>- "scasl\n\t"<br>- "lahf\n\t"<br>- : "=a" (flags), "=D" (addr)<br>- : "c" (test_len / 4), "a" (pattern), "D" (p)<br>- );<br>- if (flags & (1 << (6 + 8))) // x86 zero flag = bit 6.<br>- {<br>- return -1; // verify ok<br>- }<br>- return addr - 4; // verify error, return error address.<br>-}<br>-<br>-static void test_dram_stability(void)<br>-{<br>- u32 test_len = 2048 * 1024;<br>- u32 pat = 0x5aa5a55a;<br>- u32 ext_mem_start = 0xc0000;<br>- u32 base_mem_test_len = test_len > 640 * 1024 ? 640 * 1024 : test_len;<br>- u32 ext_mem_test_len = test_len > ext_mem_start ? test_len - ext_mem_start : 0;<br>- if (ext_mem_test_len > 0) {<br>- /* Enable all shadow RAM region C0000 - FFFFF. */<br>- pci_write_config32(NB, NB_REG_MAR, 0x3ffffff0);<br>- }<br>- int v;<br>- fill_dram((u32 *) 0, pat, base_mem_test_len);<br>- fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);<br>- v = verify_dram((u32 *) 0, pat, base_mem_test_len);<br>- if (v == -1) {<br>- v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);<br>- }<br>- /* Change pattern and test again */<br>- if (v == -1) {<br>- pat = 0xa55a5aa5;<br>- fill_dram((u32 *) 0, pat, base_mem_test_len);<br>- fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);<br>- v = verify_dram((u32 *) 0, pat, base_mem_test_len);<br>- if (v == -1) {<br>- v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);<br>- }<br>- }<br>- if (v != -1) {<br>- post_code(POST_DMP_DRAM_TEST_ERR);<br>- print_emerg("DRAM stablility test error!\nADDR = ");<br>- print_emerg_hex32(v);<br>- print_emerg(", WRITE = ");<br>- print_emerg_hex32(pat);<br>- u32 r = *(u32 *) v;<br>- print_emerg(", READ = ");<br>- print_emerg_hex32(r);<br>- print_emerg(", XOR = ");<br>- print_emerg_hex32(r ^ pat);<br>- print_emerg("\n");<br>- die("System halted.\n");<br>- }<br>- if (ext_mem_test_len > 0) {<br>- /* Disable shadow RAM. */<br>- pci_write_config32(NB, NB_REG_MAR, 0x0);<br>- }<br>-}<br>-<br>-static void enable_l2_cache(void)<br>-{<br>- /*<br>- * Enable L2 cache by setting PCI N/B function 1 L2 cache<br>- * control register (0xe8) bit 0 (L2_EN) and bit 1 (L2_WB_EN).<br>- */<br>- u32 reg_nb_f1_e8;<br>- reg_nb_f1_e8 = pci_read_config8(NB1, 0xe8);<br>- reg_nb_f1_e8 |= 3;<br>- pci_write_config8(NB1, 0xe8, reg_nb_f1_e8);<br>-}<br>-<br>-static void main(unsigned long bist)<br>-{<br>- u32 dmp_id;<br>-<br>- dmp_id = get_dmp_id();<br>- if (dmp_id != DMP_CPUID_EX) {<br>- /* Not DMP Vortex86EX CPU. */<br>- post_code(POST_DMP_ID_ERR);<br>- halt();<br>- }<br>- disable_watchdog();<br>- set_ex_powerdown_control();<br>- set_pci_nb_pmcr();<br>- set_pci_sb_lpccr();<br>- ex_uart_early_init();<br>-<br>- console_init();<br>-<br>- init_wdt1();<br>-<br>- /* Initialize i8254 timers */<br>- post_code(0x42);<br>- setup_i8254();<br>-<br>- /* Initialize DRAM */<br>- u8 reg_nb_f1_cc;<br>- /* Setup DDR3 Timing reg 0-3 / Config reg */<br>- pci_write_config16(NB, 0x6e, 0x0a2f);<br>- pci_write_config32(NB, 0x74, 0x84010200);<br>- pci_write_config32(NB, 0x78, 0x33405544);<br>- pci_write_config32(NB, 0x7c, 0x2e0f0e0b);<br>- /* Disable enhance read push write */<br>- reg_nb_f1_cc = pci_read_config8(NB1, 0xcc);<br>- reg_nb_f1_cc &= ~(1 << 4);<br>- pci_write_config8(NB1, 0xcc, reg_nb_f1_cc);<br>- if (detect_ddr3_dram_size()) {<br>- post_code(POST_DMP_DRAM_SIZING_ERR);<br>- die("DRAM sizing error!\n");<br>- }<br>- /* Reset enhance read push write to default(enable) */<br>- reg_nb_f1_cc |= (1 << 4);<br>- pci_write_config8(NB1, 0xcc, reg_nb_f1_cc);<br>-<br>- print_ddr3_memory_setup();<br>- test_dram_stability();<br>-<br>- /* CPU setup, romcc pukes on invd() */<br>- asm volatile ("invd");<br>- enable_cache();<br>-<br>- enable_l2_cache();<br>-}<br>diff --git a/src/soc/dmp/vortex86ex/Kconfig b/src/soc/dmp/vortex86ex/Kconfig<br>deleted file mode 100644<br>index 7c616d6..0000000<br>--- a/src/soc/dmp/vortex86ex/Kconfig<br>+++ /dev/null<br>@@ -1,20 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2013 DMP Electronics Inc.<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-config SOC_DMP_VORTEX86EX<br>- bool<br>- select LATE_CBMEM_INIT<br>- select AZALIA_PLUGIN_SUPPORT<br>- select HAVE_HARD_RESET<br>diff --git a/src/soc/dmp/vortex86ex/Makefile.inc b/src/soc/dmp/vortex86ex/Makefile.inc<br>deleted file mode 100644<br>index a896fcd..0000000<br>--- a/src/soc/dmp/vortex86ex/Makefile.inc<br>+++ /dev/null<br>@@ -1,26 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2013 DMP Electronics Inc.<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-ifeq ($(CONFIG_SOC_DMP_VORTEX86EX),y)<br>-<br>-ramstage-y += northbridge.c<br>-ramstage-y += xgi_oprom.c<br>-<br>-ramstage-y += southbridge.c<br>-ramstage-y += hard_reset.c<br>-ramstage-y += ide_sd_sata.c<br>-ramstage-y += audio.c<br>-<br>-endif<br>diff --git a/src/soc/dmp/vortex86ex/audio.c b/src/soc/dmp/vortex86ex/audio.c<br>deleted file mode 100644<br>index 05a0d8c..0000000<br>--- a/src/soc/dmp/vortex86ex/audio.c<br>+++ /dev/null<br>@@ -1,25 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <device/azalia_device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-<br>-/* RDC HD audio controller */<br>-static const struct pci_driver rdc_audio __pci_driver = {<br>- .ops = &default_azalia_audio_ops,<br>- .vendor = PCI_VENDOR_ID_RDC,<br>- .device = 0x3010,<br>-};<br>diff --git a/src/soc/dmp/vortex86ex/chip.h b/src/soc/dmp/vortex86ex/chip.h<br>deleted file mode 100644<br>index d67b801..0000000<br>--- a/src/soc/dmp/vortex86ex/chip.h<br>+++ /dev/null<br>@@ -1,34 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef _SOC_DMP_VORTEX86EX<br>-#define _SOC_DMP_VORTEX86EX<br>-<br>-struct soc_dmp_vortex86ex_config {<br>- /* PCI function enables */<br>- /* i.e. so that pci scan bus will find them. */<br>- /* I am putting in IDE as an example but obviously this needs<br>- * to be more complete!<br>- */<br>- int enable_ide;<br>- /* enables of functions of devices */<br>- int enable_usb;<br>- int enable_native_ide;<br>- int enable_com_ports;<br>- int enable_keyboard;<br>- int enable_nvram;<br>-};<br>-<br>-#endif /* _SOC_DMP_VORTEX86EX */<br>diff --git a/src/soc/dmp/vortex86ex/hard_reset.c b/src/soc/dmp/vortex86ex/hard_reset.c<br>deleted file mode 100644<br>index fe127aa..0000000<br>--- a/src/soc/dmp/vortex86ex/hard_reset.c<br>+++ /dev/null<br>@@ -1,21 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <reset.h><br>-<br>-void do_hard_reset(void)<br>-{<br>-}<br>diff --git a/src/soc/dmp/vortex86ex/ide_sd_sata.c b/src/soc/dmp/vortex86ex/ide_sd_sata.c<br>deleted file mode 100644<br>index c60018a..0000000<br>--- a/src/soc/dmp/vortex86ex/ide_sd_sata.c<br>+++ /dev/null<br>@@ -1,167 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <delay.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include <arch/io.h><br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-<br>-/* Vortex86EX IDE to SD/STAT controller need to enable ATA decoder and<br>- * setup timing. */<br>-<br>-/*<br>- * Primary ATA Timing Register (PATR) - Offset 40-41h<br>- * Secondary ATA Timing Register (PATR) - Offset 42-43h<br>- *<br>- * Bit R/W Default Description<br>- * 15 R/W 0h ATA Decode Enable. Decode the I/O addressing ranges assigned to this controller.<br>- * 1: Enabled.<br>- * 0: Disabled.<br>- * 14 R/W 0b Device 1 ATA Timing Register Enable<br>- * 1: Enable the device 1 ATA timing.<br>- * 0: Disable the device 1 ATA timing<br>- * 13-12 R/W 0h IORDY Sample Mode. Sets the setup time before IORDY are sampled.<br>- * 00: PIO-0<br>- * 10: PIO-2, SW-2<br>- * 10: PIO-3, PIO-4, MW-1, MW-2<br>- * 11: Reserved<br>- * 11-10 RO 0h Reserved<br>- * 9-8 R/W 0h Recovery Mode. Sets the hold time after IORDY are sampled.<br>- * 00: PIO-0, PIO-2, SW-2<br>- * 10: PIO-3, MW-1<br>- * 10: Reserved<br>- * 11: PIO-4, MW-2<br>- * 7 R/W 0b DMA Timing Enable Only Select 1<br>- * 1: Enable the device timings for DMA operation for device 1<br>- * 0: Disable the device timings for DMA operation for device 1<br>- * 6 R/W 0b ATA/ATAPI Device Indicator 1<br>- * 1: Indicate presence od an ATA device<br>- * 0: Indicate presence od an ATAPI device<br>- * 5 R/W 0b IORDY Sample Point Enabled Select 1<br>- * 1: Enable IORDY sample for PIO transfers for device 1<br>- * 0: Disable IORDY sample for PIO transfers for device 1<br>- * 4 R/W 0b Fast Drive Timing Select 1<br>- * 1: Enable faster than PIO-0 timing modes for device 1<br>- * 0: Disable faster than PIO-0 timing modes for device 1<br>- * 3 R/W 0b DMA Timing Enable Only Select 0<br>- * 1: Enable the device timings for DMA operation for device 0<br>- * 0: Disable the device timings for DMA operation for device 0<br>- * 2 R/W 0b ATA/ATAPI Device Indicator 0<br>- * 1: Indicate presence od an ATA device<br>- * 0: Indicate presence od an ATAPI device<br>- * 1 R/W 0b IORDY Sample Point Enabled Select 0<br>- * 1: Enable IORDY sample for PIO transfers for device 0<br>- * 0: Disable IORDY sample for PIO transfers for device 0<br>- * 0 R/W 0b Fast Drive Timing Select 0<br>- * 1: Enable faster than PIO-0 timing modes for device 0<br>- * 0: Disable faster than PIO-0 timing modes for device 0<br>- * */<br>-<br>-static void init_ide_ata_timing(struct device *dev)<br>-{<br>- u16 ata_timing_pri, ata_timing_sec;<br>- u32 ata_timing_reg32;<br>- /* Primary channel is SD. */<br>-#if IS_ENABLED(CONFIG_IDE1_ENABLE)<br>- ata_timing_pri = 0x8000;<br>-#else<br>- ata_timing_pri = 0x0000; // Disable this channel.<br>-#endif<br>- /* Secondary channel is SATA. */<br>-#if IS_ENABLED(CONFIG_IDE2_ENABLE)<br>- ata_timing_sec = 0xa30f; // This setting value works well.<br>-#else<br>- ata_timing_sec = 0x0000; // Disable this channel.<br>-#endif<br>- ata_timing_reg32 = (ata_timing_sec << 16) | ata_timing_pri;<br>- pci_write_config32(dev, 0x40, ata_timing_reg32);<br>-#if IS_ENABLED(CONFIG_IDE_NATIVE_MODE)<br>- /* Set both IDE channels to native mode. */<br>- u8 prog_if;<br>- prog_if = pci_read_config8(dev, 0x09);<br>- prog_if |= 5;<br>- pci_write_config8(dev, 0x09, prog_if);<br>-#endif<br>- /* MMC function enable. */<br>- u32 sd_ctrl_reg;<br>- sd_ctrl_reg = pci_read_config32(dev, 0x94);<br>- sd_ctrl_reg |= 0x0200;<br>- pci_write_config32(dev, 0x94, sd_ctrl_reg);<br>- printk(BIOS_INFO, "Vortex86EX IDE controller ATA TIMING reg = %08x\n", ata_timing_reg32);<br>-}<br>-<br>-static void setup_std_ide_compatible(struct device *dev)<br>-{<br>-#if IS_ENABLED(CONFIG_IDE_STANDARD_COMPATIBLE)<br>- // Misc Control Register (MCR) Offset 90h<br>- // bit 0 = Vendor ID Access, bit 1 = Device ID Access.<br>- u8 mcr;<br>- u16 vendor = (u16) (CONFIG_IDE_COMPATIBLE_SELECTION >> 16);<br>- u16 device = (u16) (CONFIG_IDE_COMPATIBLE_SELECTION & 0xffff);<br>- // unlock vendor/device ID access bits.<br>- mcr = pci_read_config8(dev, 0x90);<br>- pci_write_config8(dev, 0x90, mcr | 3);<br>- pci_write_config16(dev, 0x00, vendor);<br>- pci_write_config16(dev, 0x02, device);<br>- // restore lock bits.<br>- pci_write_config8(dev, 0x90, mcr);<br>-#endif<br>-}<br>-<br>-static void vortex_ide_init(struct device *dev)<br>-{<br>- if (dev->device == 0x1010) {<br>- // This is SX/old DX IDE controller.<br>- // Set IOCFG bit 15/13 : IDE Decoder Enable for Primary/Secondary channel.<br>- u16 iocfg = 0xa000;<br>- pci_write_config16(dev, 0x40, iocfg);<br>- } else if (dev->device == 0x1011 || dev->device == 0x1012) {<br>- // This is new DX/MX/MX+/DX2 IDE controller.<br>- init_ide_ata_timing(dev);<br>- setup_std_ide_compatible(dev);<br>- }<br>-}<br>-<br>-static struct device_operations vortex_ide_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = vortex_ide_init,<br>- .scan_bus = 0,<br>-};<br>-<br>-static const struct pci_driver vortex_ide_driver_1010 __pci_driver = {<br>- .ops = &vortex_ide_ops,<br>- .vendor = PCI_VENDOR_ID_RDC,<br>- .device = 0x1010,<br>-};<br>-<br>-static const struct pci_driver vortex_ide_driver_1011 __pci_driver = {<br>- .ops = &vortex_ide_ops,<br>- .vendor = PCI_VENDOR_ID_RDC,<br>- .device = 0x1011,<br>-};<br>-<br>-static const struct pci_driver vortex_ide_driver_1012 __pci_driver = {<br>- .ops = &vortex_ide_ops,<br>- .vendor = PCI_VENDOR_ID_RDC,<br>- .device = 0x1012,<br>-};<br>diff --git a/src/soc/dmp/vortex86ex/northbridge.c b/src/soc/dmp/vortex86ex/northbridge.c<br>deleted file mode 100644<br>index d811ba9..0000000<br>--- a/src/soc/dmp/vortex86ex/northbridge.c<br>+++ /dev/null<br>@@ -1,133 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <cbmem.h><br>-#include <pc80/mc146818rtc.h><br>-#include "chip.h"<br>-#include "northbridge.h"<br>-<br>-#define SPI_BASE 0xfc00<br>-<br>-static void northbridge_init(device_t dev)<br>-{<br>- printk(BIOS_DEBUG, "Vortex86EX northbridge early init ...\n");<br>- // enable F0A/ECA/E8A/E4A/E0A/C4A/C0A shadow read/writable.<br>- pci_write_config32(dev, NB_REG_MAR, 0x3ff000f0);<br>- // enable C0000h - C3FFFh/C4000h - C7FFF can be in L1 cache selection.<br>- pci_write_config32(dev, NB_REG_HOST_CTL, (1 << 18) | (1 << 19));<br>- // Set SPI register base.<br>- pci_write_config16(dev, NB_REG_SPI_BASE, SPI_BASE | 1);<br>-}<br>-<br>-static struct device_operations northbridge_operations = {<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = northbridge_init<br>-};<br>-<br>-static const struct pci_driver northbridge_driver_6025 __pci_driver = {<br>- .ops = &northbridge_operations,<br>- .vendor = PCI_VENDOR_ID_RDC,<br>- .device = 0x6025, /* EX CPU N/B ID */<br>-};<br>-<br>-/* Set CMOS register 15h/16h/17h/18h for base/extended<br>- * memory size. */<br>-static void set_cmos_memory_size(unsigned long sizek)<br>-{<br>- unsigned long ext_mem_size;<br>- u8 ext_mem_size_hb, ext_mem_size_lb;<br>- /* calculate memory size between 1M - 65M. */<br>- ext_mem_size = sizek - 1024;<br>- if (ext_mem_size > 65535)<br>- ext_mem_size = 65535;<br>- ext_mem_size_hb = (u8) (ext_mem_size >> 8);<br>- ext_mem_size_lb = (u8) (ext_mem_size & 0xff);<br>- /* Base memory is always 640K. */<br>- cmos_write(0x80, 0x15);<br>- cmos_write(0x02, 0x16);<br>- /* Write extended memory size. */<br>- cmos_write(ext_mem_size_lb, 0x17);<br>- cmos_write(ext_mem_size_hb, 0x18);<br>- /* register 0x30(48) is RTC_BOOT_BYTE for coreboot,<br>- * don't touch it. */<br>-}<br>-<br>-static void pci_domain_set_resources(device_t dev)<br>-{<br>- device_t mc_dev;<br>- uint32_t pci_tolm;<br>-<br>- printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n");<br>-<br>- pci_tolm = find_pci_tolm(dev->link_list);<br>- mc_dev = dev->link_list->children;<br>- if (mc_dev) {<br>- unsigned long tomk, tolmk;<br>- int idx;<br>- int ss;<br>- /* Get DDRII size setting from northbridge register. */<br>- /* SS = 0 for 2MB, 1 for 4MB, 2 for 8MB, 3 for 16MB ... */<br>- ss = pci_read_config16(mc_dev, 0x6c);<br>- ss = ((ss >> 8) & 0xf);<br>- tomk = (2 * 1024) << ss;<br>- printk(BIOS_DEBUG, "I would set RAM size to %ld Mbytes\n", (tomk >> 10));<br>- /* Compute the top of Low memory */<br>- tolmk = pci_tolm >> 10;<br>- if (tolmk >= tomk)<br>- /* The PCI hole does does not overlap the memory.<br>- */<br>- tolmk = tomk;<br>-<br>- set_late_cbmem_top(tolmk * 1024);<br>-<br>- /* Report the memory regions */<br>- idx = 10;<br>- ram_resource(dev, idx++, 0, 640); /* first 640k */<br>- ram_resource(dev, idx++, 768, tolmk - 768); /* leave a hole for vga */<br>- set_cmos_memory_size(tolmk);<br>- }<br>- assign_resources(dev->link_list);<br>-}<br>-<br>-static struct device_operations pci_domain_ops = {<br>- .read_resources = pci_domain_read_resources,<br>- .set_resources = pci_domain_set_resources,<br>- .enable_resources = NULL,<br>- .init = NULL,<br>- .scan_bus = pci_domain_scan_bus,<br>- .ops_pci_bus = pci_bus_default_ops,<br>-};<br>-<br>-static void enable_dev(struct device *dev)<br>-{<br>- printk(BIOS_SPEW, "In vortex86ex enable_dev for device %s.\n", dev_path(dev));<br>-<br>- /* Set the operations if it is a special bus type */<br>- if (dev->path.type == DEVICE_PATH_DOMAIN) {<br>- dev->ops = &pci_domain_ops;<br>- }<br>-}<br>-<br>-struct chip_operations northbridge_dmp_vortex86ex_ops = {<br>- CHIP_NAME("DMP Vortex86EX Northbridge")<br>- .enable_dev = enable_dev,<br>-};<br>diff --git a/src/soc/dmp/vortex86ex/northbridge.h b/src/soc/dmp/vortex86ex/northbridge.h<br>deleted file mode 100644<br>index d5bb6f1..0000000<br>--- a/src/soc/dmp/vortex86ex/northbridge.h<br>+++ /dev/null<br>@@ -1,65 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef NORTHBRIDGE_H<br>-#define NORTHBRIDGE_H<br>-<br>-#define NB PCI_DEV(0, 0, 0)<br>-#define NB_REG_SPI_BASE 0x40<br>-#define NB_REG_CLK_OUT_CTL 0x48<br>-#define NB_REG_PCI_CLK_CTL 0x4b<br>-#define NB_REG_STRAP 0x60<br>-#define NB_REG_STRAP2 0x64<br>-#define NB_REG_MBR 0x6c<br>-#define NB_REG_DDR3_CFG 0x74<br>-#define NB_REG_DDR3_MTR1 0x78<br>-#define NB_REG_DDR3_MTR2 0x7c<br>-#define NB_REG_SMM 0x83<br>-#define NB_REG_MAR 0x84<br>-#define NB_REG_CID 0x90<br>-#define NB_REG_S1R 0x94<br>-#define NB_REG_S2R 0x98<br>-#define NB_REG_S3R 0x9c<br>-#define NB_REG_HOST_CTL 0xa0<br>-#define NB_REG_CPU_MBCR 0xc4<br>-#define NB_REG_CDR 0xd0<br>-#define NB_REG_PACR 0xf0<br>-#define NB_REG_PMCR 0xf4<br>-#define NB_REG_PCI_TARGET 0xf8<br>-#define NB_REG_PCSCR 0xfc<br>-<br>-/* Additional "virtual" device, just extension of NB */<br>-#define NB1 PCI_DEV(0, 0, 1)<br>-#define NB1_REG_FJZ_PHY_CTL1 0x80<br>-#define NB1_REG_FJZ_PHY_CTL2 0x84<br>-#define NB1_REG_FJZ_PHY_CTL3 0x88<br>-#define NB1_REG_FJZ_DRAM_CTL1 0x90<br>-#define NB1_REG_FJZ_DRAM_CTL2 0x94<br>-#define NB1_REG_FJZ_DRAM_CTL3 0x98<br>-#define NB1_REG_FJZ_DRAM_CTL4 0x9c<br>-#define NB1_REG_PLL_TEST_CTL 0xa8<br>-#define NB1_REG_DDR3_PWR_SAV 0xbc<br>-#define NB1_REG_DDR3_CTL_OPT1 0xc0<br>-#define NB1_REG_DDR3_CTL_OPT3 0xc8<br>-#define NB1_REG_DDR3_CTL_OPT4 0xcc<br>-#define NB1_REG_DDR3_CTL_OPT5 0xce<br>-#define NB1_REG_PLL_TEST_MODE 0xd0<br>-#define NB1_REG_L2_CACHE_CTL 0xe8<br>-#define NB1_REG_SSCR 0xec<br>-#define NB1_REG_NB_CTL_OPT1 0xf4<br>-#define NB1_REG_UPDATE_PHY_IO 0xf8<br>-#define NB1_REG_RESET_DRAMC_PHY 0xfa<br>-<br>-#endif /* NORTHBRIDGE_H */<br>diff --git a/src/soc/dmp/vortex86ex/raminit.c b/src/soc/dmp/vortex86ex/raminit.c<br>deleted file mode 100644<br>index 0d4b5b5..0000000<br>--- a/src/soc/dmp/vortex86ex/raminit.c<br>+++ /dev/null<br>@@ -1,321 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-static u16 get_mask(u16 bit_width, u16 bit_offset)<br>-{<br>- u16 mask = (((1 << bit_width) - 1) << bit_offset);<br>- return mask;<br>-}<br>-<br>-static u16 set_bitfield(u16 val, u16 bits, u16 bit_width, u16 bit_offset)<br>-{<br>- u16 mask = get_mask(bit_width, bit_offset);<br>- val = (val & ~mask) | (bits << bit_offset);<br>- return val;<br>-}<br>-<br>-static u16 get_bitfield(u16 val, u16 bit_width, u16 bit_offset)<br>-{<br>- u16 mask = get_mask(bit_width, bit_offset);<br>- return (val & mask) >> bit_offset;<br>-}<br>-<br>-static u8 check_address_bit(int addr_bit)<br>-{<br>- u16 dummy;<br>- *(volatile u16 *)(0) = 0;<br>- dummy = *(volatile u16 *)(0); // read push write<br>- *(volatile u16 *)(1 << addr_bit) = 0x5a5a;<br>- dummy = *(volatile u16 *)(1 << addr_bit); // read push write<br>- if ((*(volatile u16 *)(0)) != 0)<br>- return 0; // address bit wrapped.<br>- return 1; // address bit not wrapped.<br>-}<br>-<br>-static u8 check_dram_side(int addr_bit)<br>-{<br>- *(volatile u16 *)(1 << addr_bit) = 0x5a5a;<br>- *(volatile u16 *)(0) = 0;<br>- if ((*(volatile u16 *)(1 << addr_bit)) != 0x5a5a)<br>- return 0; // DRAM only one side.<br>- return 1; // two sides.<br>-}<br>-<br>-// DDRIII memory bank register control:<br>-// bit :<br>-// 2 - 0 : DRAMC_COLSIZE : DDRIII Column Address Type : 0 0 0 = 10bit<br>-// : 0 0 1 = 11bit<br>-// 7 - 5 : DRAMC_ROWSIZE : DDRIII Row Address Type : 0 0 0 = 13bit<br>-// : 0 0 1 = 14bit<br>-// : 0 1 0 = 15bit<br>-// : 0 1 1 = 16bit<br>-// 11 - 8 : DRAM_SIZE : DDRIII Size : 0 1 0 1 = 64M<br>-// : 0 1 1 0 = 128M<br>-// : 0 1 1 1 = 256M<br>-// : 1 0 0 0 = 512M<br>-// : 1 0 0 1 = 1GB<br>-// : 1 0 1 0 = 2GB<br>-// 13 : DRAMC_CSMASK : DDRIII CS#[1] Mask : 1 = Mask CS1 enable<br>-<br>-#define DDR3_COL_10BIT 0<br>-#define DDR3_COL_11BIT 1<br>-#define DDR3_ROW_13BIT 0<br>-#define DDR3_ROW_14BIT 1<br>-#define DDR3_ROW_15BIT 2<br>-#define DDR3_ROW_16BIT 3<br>-#define DDR3_SIZE_64M 5<br>-#define DDR3_SIZE_128M 6<br>-#define DDR3_SIZE_256M 7<br>-#define DDR3_SIZE_512M 8<br>-#define DDR3_SIZE_1GB 9<br>-#define DDR3_SIZE_2GB 10<br>-#define DDR3_C1M_ACTIVE 0<br>-#define DDR3_C1M_MASK 1<br>-<br>-static u16 set_ddr3_mem_reg_col(u16 reg, u16 col)<br>-{<br>- return set_bitfield(reg, col, 3, 0);<br>-}<br>-<br>-static u16 get_ddr3_mem_reg_col(u16 reg)<br>-{<br>- return get_bitfield(reg, 3, 0);<br>-}<br>-<br>-static u16 set_ddr3_mem_reg_row(u16 reg, u16 row)<br>-{<br>- return set_bitfield(reg, row, 3, 5);<br>-}<br>-<br>-static u16 get_ddr3_mem_reg_row(u16 reg)<br>-{<br>- return get_bitfield(reg, 3, 5);<br>-}<br>-<br>-static u16 set_ddr3_mem_reg_size(u16 reg, u16 size)<br>-{<br>- return set_bitfield(reg, size, 4, 8);<br>-}<br>-<br>-static u16 get_ddr3_mem_reg_size(u16 reg)<br>-{<br>- return get_bitfield(reg, 4, 8);<br>-}<br>-<br>-static u16 set_ddr3_mem_reg_c1m(u16 reg, u16 c1m)<br>-{<br>- return set_bitfield(reg, c1m, 1, 13);<br>-}<br>-<br>-static u16 get_ddr3_mem_reg_c1m(u16 reg)<br>-{<br>- return get_bitfield(reg, 1, 13);<br>-}<br>-<br>-static u16 auto_set_ddr3_mem_reg_size(u16 reg)<br>-{<br>- u8 ss = 0;<br>- // If reg is the minimum DRAM size,<br>- // SS is also the minimum size 128M.<br>- // If size in reg is bigger, SS is also bigger.<br>- ss += get_ddr3_mem_reg_col(reg);<br>- ss += get_ddr3_mem_reg_row(reg);<br>- ss += (1 - get_ddr3_mem_reg_c1m(reg));<br>- ss += DDR3_SIZE_128M;<br>- return set_ddr3_mem_reg_size(reg, ss);<br>-}<br>-<br>-static u16 get_ddr3_mem_reg(u16 col, u16 row, u16 c1m)<br>-{<br>- u16 reg;<br>- reg = 0;<br>- reg = set_ddr3_mem_reg_col(reg, col);<br>- reg = set_ddr3_mem_reg_row(reg, row);<br>- reg = set_ddr3_mem_reg_c1m(reg, c1m);<br>- reg = auto_set_ddr3_mem_reg_size(reg);<br>- return reg;<br>-}<br>-<br>-static void ddr3_phy_reset(void)<br>-{<br>- // PCI N/B reg FAh bit 6 = RST_DRAM_PHY.<br>- pci_write_config8(NB1, NB1_REG_RESET_DRAMC_PHY, 0x40);<br>- while ((pci_read_config8(NB1, NB1_REG_RESET_DRAMC_PHY) & 0x40) == 0x40) {<br>- }<br>- // reload mode.<br>- u32 ddr3_cfg = pci_read_config32(NB, NB_REG_DDR3_CFG);<br>- pci_write_config32(NB, NB_REG_DDR3_CFG, ddr3_cfg);<br>-}<br>-<br>-static u8 detect_ddr3_dram_cs(u16 reg, u8 base_addr_bit)<br>-{<br>- reg = set_ddr3_mem_reg_c1m(reg, DDR3_C1M_ACTIVE);<br>- reg = auto_set_ddr3_mem_reg_size(reg);<br>- pci_write_config16(NB, NB_REG_MBR, reg);<br>- if (check_dram_side(base_addr_bit + 1)) {<br>- base_addr_bit += 1;<br>- return 0;<br>- }<br>-<br>- reg = set_ddr3_mem_reg_c1m(reg, DDR3_C1M_MASK);<br>- reg = auto_set_ddr3_mem_reg_size(reg);<br>- pci_write_config16(NB, NB_REG_MBR, reg);<br>- // no need to check CS = 0.<br>- // Need to reset DDR3 PHY.<br>- ddr3_phy_reset();<br>- return 0;<br>-}<br>-<br>-static u8 detect_ddr3_dram_row(u16 reg, u8 base_addr_bit)<br>-{<br>- reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_16BIT);<br>- reg = auto_set_ddr3_mem_reg_size(reg);<br>- pci_write_config16(NB, NB_REG_MBR, reg);<br>- if (check_address_bit(base_addr_bit + 16)) {<br>- base_addr_bit += 16;<br>- return detect_ddr3_dram_cs(reg, base_addr_bit);<br>- }<br>-<br>- reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_15BIT);<br>- reg = auto_set_ddr3_mem_reg_size(reg);<br>- pci_write_config16(NB, NB_REG_MBR, reg);<br>- if (check_address_bit(base_addr_bit + 15)) {<br>- base_addr_bit += 15;<br>- return detect_ddr3_dram_cs(reg, base_addr_bit);<br>- }<br>-<br>- reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_14BIT);<br>- reg = auto_set_ddr3_mem_reg_size(reg);<br>- pci_write_config16(NB, NB_REG_MBR, reg);<br>- if (check_address_bit(base_addr_bit + 14)) {<br>- base_addr_bit += 14;<br>- return detect_ddr3_dram_cs(reg, base_addr_bit);<br>- }<br>-<br>- reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_13BIT);<br>- reg = auto_set_ddr3_mem_reg_size(reg);<br>- pci_write_config16(NB, NB_REG_MBR, reg);<br>- if (check_address_bit(base_addr_bit + 13)) {<br>- base_addr_bit += 13;<br>- return detect_ddr3_dram_cs(reg, base_addr_bit);<br>- }<br>- // row test error.<br>- return 1;<br>-}<br>-<br>-static u8 detect_ddr3_dram_bank(u16 reg, u8 base_addr_bit)<br>-{<br>- /* DDR3 is always 3 bank bits */<br>- base_addr_bit += 3;<br>- return detect_ddr3_dram_row(reg, base_addr_bit);<br>-}<br>-<br>-static u8 detect_ddr3_dram_col(u16 reg, u8 base_addr_bit)<br>-{<br>- reg = set_ddr3_mem_reg_col(reg, DDR3_COL_11BIT);<br>- reg = auto_set_ddr3_mem_reg_size(reg);<br>- pci_write_config16(NB, NB_REG_MBR, reg);<br>- if (check_address_bit(base_addr_bit + 11)) {<br>- base_addr_bit += 11;<br>- return detect_ddr3_dram_bank(reg, base_addr_bit);<br>- }<br>-<br>- reg = set_ddr3_mem_reg_col(reg, DDR3_COL_10BIT);<br>- reg = auto_set_ddr3_mem_reg_size(reg);<br>- pci_write_config16(NB, NB_REG_MBR, reg);<br>- if (check_address_bit(base_addr_bit + 10)) {<br>- base_addr_bit += 10;<br>- return detect_ddr3_dram_bank(reg, base_addr_bit);<br>- }<br>- // col test error.<br>- return 1;<br>-}<br>-<br>-static u8 detect_ddr3_dram_size(void)<br>-{<br>- u16 reg;<br>- u8 base_addr_bit = 0;<br>- reg = get_ddr3_mem_reg(DDR3_COL_10BIT, DDR3_ROW_13BIT, DDR3_C1M_MASK);<br>- return detect_ddr3_dram_col(reg, base_addr_bit);<br>-}<br>-<br>-static void print_ddr3_memory_setup(void)<br>-{<br>-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>- printk(BIOS_DEBUG, "DDR3 Timing Reg 0-3:\n");<br>- printk(BIOS_DEBUG, "NB 6e : ");<br>- print_debug_hex16(pci_read_config16(NB, 0x6e));<br>- printk(BIOS_DEBUG, "\nNB 74 : ");<br>- print_debug_hex32(pci_read_config32(NB, 0x74));<br>- printk(BIOS_DEBUG, "\nNB 78 : ");<br>- print_debug_hex32(pci_read_config32(NB, 0x78));<br>- printk(BIOS_DEBUG, "\nNB 7c : ");<br>- print_debug_hex32(pci_read_config32(NB, 0x7c));<br>- u16 mbr = pci_read_config16(NB, 0x6c);<br>- printk(BIOS_DEBUG, "\nNB 6c(MBR) : ");<br>- print_debug_hex16(mbr);<br>- const char *s;<br>- u8 col = get_ddr3_mem_reg_col(mbr);<br>- if (col == DDR3_COL_10BIT)<br>- s = " (COL=10";<br>- else<br>- s = " (COL=11";<br>- print_debug(s);<br>- u8 row = get_ddr3_mem_reg_row(mbr);<br>- switch (row) {<br>- case DDR3_ROW_13BIT:<br>- s = ", ROW = 13";<br>- break;<br>- case DDR3_ROW_14BIT:<br>- s = ", ROW = 14";<br>- break;<br>- case DDR3_ROW_15BIT:<br>- s = ", ROW = 15";<br>- break;<br>- default:<br>- s = ", ROW = 16";<br>- break;<br>- }<br>- print_debug(s);<br>- u8 size = get_ddr3_mem_reg_size(mbr);<br>- switch (size) {<br>- case DDR3_SIZE_64M:<br>- s = ", 64M";<br>- break;<br>- case DDR3_SIZE_128M:<br>- s = ", 128M";<br>- break;<br>- case DDR3_SIZE_256M:<br>- s = ", 256M";<br>- break;<br>- case DDR3_SIZE_512M:<br>- s = ", 512M";<br>- break;<br>- case DDR3_SIZE_1GB:<br>- s = ", 1GB";<br>- break;<br>- case DDR3_SIZE_2GB:<br>- s = ", 2GB";<br>- break;<br>- }<br>- print_debug(s);<br>- u8 mask = get_ddr3_mem_reg_c1m(mbr);<br>- if (mask == DDR3_C1M_ACTIVE)<br>- s = ", CS MASK Enable)\n";<br>- else<br>- s = ", CS Mask Disable)\n";<br>- print_debug(s);<br>-#endif<br>-}<br>diff --git a/src/soc/dmp/vortex86ex/southbridge.c b/src/soc/dmp/vortex86ex/southbridge.c<br>deleted file mode 100644<br>index 1d3c897..0000000<br>--- a/src/soc/dmp/vortex86ex/southbridge.c<br>+++ /dev/null<br>@@ -1,632 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ops.h><br>-#include <device/pci_ids.h><br>-#include <pc80/mc146818rtc.h><br>-#include <pc80/keyboard.h><br>-#include <string.h><br>-#include <delay.h><br>-#include "arch/io.h"<br>-#include "chip.h"<br>-#include "southbridge.h"<br>-#include "cpu/dmp/dmp_post_code.h"<br>-<br>-/* IRQ number to S/B PCI Interrupt routing table reg(0x58/0xb4) mapping table. */<br>-static const unsigned char irq_to_int_routing[16] = {<br>- 0x0, 0x0, 0x0, 0x2, // IRQ0-2 is unmappable, IRQ3 = 2.<br>- 0x4, 0x5, 0x7, 0x6, // IRQ4-7 = 4, 5, 7, 6.<br>- 0x0, 0x1, 0x3, 0x9, // IRQ8 is unmappable, IRQ9-11 = 1, 3, 9.<br>- 0xb, 0x0, 0xd, 0xf // IRQ12 = b, IRQ13 is unmappable, IRQ14-15 = d, f.<br>-};<br>-<br>-/* S/B PCI Interrupt routing table reg(0x58) field bit shift. */<br>-#define EHCIH_IRQ_SHIFT 28<br>-#define OHCII_IRQ_SHIFT 24<br>-#define MAC_IRQ_SHIFT 16<br>-#define RT3_IRQ_SHIFT 12<br>-#define RT2_IRQ_SHIFT 8<br>-#define RT1_IRQ_SHIFT 4<br>-#define RT0_IRQ_SHIFT 0<br>-<br>-/* S/B Extend PCI Interrupt routing table reg(0xb4) field bit shift. */<br>-#define CAN_IRQ_SHIFT 28<br>-#define HDA_IRQ_SHIFT 20<br>-#define USBD_IRQ_SHIFT 16<br>-#define SIDE_IRQ_SHIFT 12<br>-#define PIDE_IRQ_SHIFT 8<br>-<br>-/* S/B function 1 Extend PCI Interrupt routing table reg 2(0xb4)<br>- * field bit shift.<br>- */<br>-#define SPI1_IRQ_SHIFT 8<br>-#define MOTOR_IRQ_SHIFT 0<br>-<br>-/* in-chip PCI device IRQs(0 for disabled). */<br>-#define EHCII_IRQ 5<br>-#define OHCII_IRQ 5<br>-#define MAC_IRQ 6<br>-<br>-#define CAN_IRQ 10<br>-#define HDA_IRQ 7<br>-#define USBD_IRQ 6<br>-#define PIDE_IRQ 5<br>-<br>-#define SPI1_IRQ 10<br>-#define I2C0_IRQ 10<br>-#define MOTOR_IRQ 11<br>-<br>-/* RT0-3 IRQs. */<br>-#define RT3_IRQ 3<br>-#define RT2_IRQ 4<br>-#define RT1_IRQ 5<br>-#define RT0_IRQ 6<br>-<br>-/* IDE legacy mode IRQs. */<br>-#define IDE1_LEGACY_IRQ 14<br>-#define IDE2_LEGACY_IRQ 15<br>-<br>-/* Internal parallel port */<br>-#define LPT_INT_C 0<br>-#define LPT_INT_ACK_SET 0<br>-#define LPT_UE 1<br>-#define LPT_PDMAS 0<br>-#define LPT_DREQS 0<br>-<br>-/* keyboard controller system flag timeout : 400 ms */<br>-#define KBC_TIMEOUT_SYS_FLAG 400<br>-<br>-static u8 get_pci_dev_func(device_t dev)<br>-{<br>- return PCI_FUNC(dev->path.pci.devfn);<br>-}<br>-<br>-static void verify_dmp_keyboard_error(void)<br>-{<br>- post_code(POST_DMP_KBD_FW_VERIFY_ERR);<br>- die("Internal keyboard firmware verify error!\n");<br>-}<br>-<br>-static void upload_dmp_keyboard_firmware(struct device *dev)<br>-{<br>- u32 reg_sb_c0;<br>- u32 fwptr;<br>-<br>- // enable firmware uploading function by set bit 10.<br>- post_code(POST_DMP_KBD_FW_UPLOAD);<br>- reg_sb_c0 = pci_read_config32(dev, SB_REG_IPFCR);<br>- pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 | 0x400);<br>-<br>- outw(0, 0x62); // reset upload address to 0.<br>- // upload 4096 bytes from 0xFFFFE000.<br>- outsb(0x66, (u8 *) 0xffffe000, 4096);<br>- // upload 4096 bytes from 0xFFFFC000.<br>- outsb(0x66, (u8 *) 0xffffc000, 4096);<br>-<br>- outw(0, 0x62); // reset upload address to 0.<br>- // verify 4096 bytes from 0xFFFFE000.<br>- for (fwptr = 0xffffe000; fwptr < 0xfffff000; fwptr++) {<br>- if (inb(0x66) != *(u8 *) fwptr) {<br>- verify_dmp_keyboard_error();<br>- }<br>- }<br>- // verify 4096 bytes from 0xFFFFC000.<br>- for (fwptr = 0xffffc000; fwptr < 0xffffd000; fwptr++) {<br>- if (inb(0x66) != *(u8 *) fwptr) {<br>- verify_dmp_keyboard_error();<br>- }<br>- }<br>-<br>- // disable firmware uploading.<br>- pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 & ~0x400L);<br>-}<br>-<br>-static int kbc_wait_system_flag(void)<br>-{<br>- /* wait keyboard controller ready by checking system flag<br>- * (status port bit 2).<br>- */<br>- post_code(POST_DMP_KBD_CHK_READY);<br>- u32 timeout;<br>- for (timeout = KBC_TIMEOUT_SYS_FLAG;<br>- timeout && ((inb(0x64) & 0x4) == 0); timeout--)<br>- mdelay(1);<br>-<br>- if (!timeout) {<br>- printk(BIOS_WARNING, "Keyboard controller system flag timeout\n");<br>- }<br>- return !!timeout;<br>-}<br>-<br>-static void pci_routing_fixup(struct device *dev)<br>-{<br>- const unsigned slot[3] = { 0 };<br>- const unsigned char slot_irqs[1][4] = {<br>- {RT0_IRQ, RT1_IRQ, RT2_IRQ, RT3_IRQ},<br>- };<br>- const int slot_num = 1;<br>- int i;<br>- u32 int_routing = 0;<br>- u32 ext_int_routing = 0;<br>-<br>- /* assign PCI-e bridge (bus#0, dev#1, fn#0) IRQ to RT0. */<br>- pci_assign_irqs(0, 1, slot_irqs[0]);<br>-<br>- /* RT0 is enabled. */<br>- int_routing |= irq_to_int_routing[RT0_IRQ] << RT0_IRQ_SHIFT;<br>-<br>- /* assign PCI slot IRQs. */<br>- for (i = 0; i < slot_num; i++) {<br>- pci_assign_irqs(1, slot[i], slot_irqs[i]);<br>- }<br>-<br>- /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */<br>- for (i = 0; i < slot_num; i++) {<br>- unsigned int funct;<br>- device_t pdev;<br>- u8 irq;<br>-<br>- /* Each slot may contain up to eight functions. */<br>- for (funct = 0; funct < 8; funct++) {<br>- pdev = dev_find_slot(1, (slot[i] << 3) + funct);<br>- if (!pdev)<br>- continue;<br>- irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);<br>- if (irq == RT1_IRQ) {<br>- int_routing |= irq_to_int_routing[RT1_IRQ] << RT1_IRQ_SHIFT;<br>- } else if (irq == RT2_IRQ) {<br>- int_routing |= irq_to_int_routing[RT2_IRQ] << RT2_IRQ_SHIFT;<br>- } else if (irq == RT3_IRQ) {<br>- int_routing |= irq_to_int_routing[RT3_IRQ] << RT3_IRQ_SHIFT;<br>- }<br>- }<br>- }<br>-<br>- /* Setup S/B PCI Interrupt routing table reg(0x58). */<br>- int_routing |= irq_to_int_routing[EHCII_IRQ] << EHCIH_IRQ_SHIFT;<br>- int_routing |= irq_to_int_routing[OHCII_IRQ] << OHCII_IRQ_SHIFT;<br>- int_routing |= irq_to_int_routing[MAC_IRQ] << MAC_IRQ_SHIFT;<br>- pci_write_config32(dev, SB_REG_PIRQ_ROUTE, int_routing);<br>-<br>- /* Setup S/B PCI Extend Interrupt routing table reg(0xb4). */<br>- ext_int_routing |= irq_to_int_routing[CAN_IRQ] << CAN_IRQ_SHIFT;<br>- ext_int_routing |= irq_to_int_routing[HDA_IRQ] << HDA_IRQ_SHIFT;<br>- ext_int_routing |= irq_to_int_routing[USBD_IRQ] << USBD_IRQ_SHIFT;<br>-#if IS_ENABLED(CONFIG_IDE_NATIVE_MODE)<br>- /* IDE in native mode, only uses one IRQ. */<br>- ext_int_routing |= irq_to_int_routing[0] << SIDE_IRQ_SHIFT;<br>- ext_int_routing |= irq_to_int_routing[PIDE_IRQ] << PIDE_IRQ_SHIFT;<br>-#else<br>- /* IDE in legacy mode, use IRQ 14, 15. */<br>- ext_int_routing |= irq_to_int_routing[IDE2_LEGACY_IRQ] << SIDE_IRQ_SHIFT;<br>- ext_int_routing |= irq_to_int_routing[IDE1_LEGACY_IRQ] << PIDE_IRQ_SHIFT;<br>-#endif<br>- pci_write_config32(dev, SB_REG_EXT_PIRQ_ROUTE, ext_int_routing);<br>-<br>- /* Assign in-chip PCI device IRQs. */<br>- if (MAC_IRQ) {<br>- unsigned char irqs[4] = { MAC_IRQ, 0, 0, 0 };<br>- pci_assign_irqs(0, 0x8, irqs);<br>- }<br>- if ((OHCII_IRQ != 0) && (EHCII_IRQ != 0)) {<br>- unsigned char irqs[4] = { OHCII_IRQ, EHCII_IRQ, 0, 0 };<br>- pci_assign_irqs(0, 0xa, irqs);<br>- }<br>- if ((CONFIG_IDE_NATIVE_MODE != 0) && (PIDE_IRQ != 0)) {<br>- /* IDE in native mode, setup PCI IRQ. */<br>- unsigned char irqs[4] = { PIDE_IRQ, 0, 0, 0 };<br>- pci_assign_irqs(0, 0xc, irqs);<br>- }<br>- if (CAN_IRQ) {<br>- unsigned char irqs[4] = { CAN_IRQ, 0, 0, 0 };<br>- pci_assign_irqs(0, 0x11, irqs);<br>- }<br>- if (HDA_IRQ) {<br>- unsigned char irqs[4] = { HDA_IRQ, 0, 0, 0 };<br>- pci_assign_irqs(0, 0xe, irqs);<br>- }<br>- if (USBD_IRQ) {<br>- unsigned char irqs[4] = { USBD_IRQ, 0, 0, 0 };<br>- pci_assign_irqs(0, 0xf, irqs);<br>- }<br>-}<br>-<br>-static void vortex_sb_init(struct device *dev)<br>-{<br>- u32 lpt_reg = 0;<br>-<br>-#if IS_ENABLED(CONFIG_LPT_ENABLE)<br>- int ppmod = 0;<br>-#if IS_ENABLED(CONFIG_LPT_MODE_BPP)<br>- ppmod = 0;<br>-#elif IS_ENABLED(CONFIG_LPT_MODE_EPP_19_AND_SPP)<br>- ppmod = 1;<br>-#elif IS_ENABLED(CONFIG_LPT_MODE_ECP)<br>- ppmod = 2;<br>-#elif IS_ENABLED(CONFIG_LPT_MODE_ECP_AND_EPP_19)<br>- ppmod = 3;<br>-#elif IS_ENABLED(CONFIG_LPT_MODE_SPP)<br>- ppmod = 4;<br>-#elif IS_ENABLED(CONFIG_LPT_MODE_EPP_17_AND_SPP)<br>- ppmod = 5;<br>-#elif IS_ENABLED(CONFIG_LPT_MODE_ECP_AND_EPP_17)<br>- ppmod = 7;<br>-#else<br>-#error CONFIG_LPT_MODE error.<br>-#endif<br>-<br>- /* Setup internal parallel port */<br>- lpt_reg |= (LPT_INT_C << 28);<br>- lpt_reg |= (LPT_INT_ACK_SET << 27);<br>- lpt_reg |= (ppmod << 24);<br>- lpt_reg |= (LPT_UE << 23);<br>- lpt_reg |= (LPT_PDMAS << 22);<br>- lpt_reg |= (LPT_DREQS << 20);<br>- lpt_reg |= (irq_to_int_routing[CONFIG_LPT_IRQ] << 16);<br>- lpt_reg |= (CONFIG_LPT_IO << 0);<br>-#endif // CONFIG_LPT_ENABLE<br>- pci_write_config32(dev, SB_REG_IPPCR, lpt_reg);<br>-}<br>-<br>-#define SETUP_GPIO_ADDR(n) \<br>- u32 cfg##n = (CONFIG_GPIO_P##n##_DIR_ADDR << 16) | (CONFIG_GPIO_P##n##_DATA_ADDR);\<br>- outl(cfg##n, base + 4 + (n * 4));\<br>- gpio_enable_mask |= (1 << n);<br>-<br>-#define INIT_GPIO(n) \<br>- outb(CONFIG_GPIO_P##n##_INIT_DIR, CONFIG_GPIO_P##n##_DIR_ADDR);\<br>- outb(CONFIG_GPIO_P##n##_INIT_DATA, CONFIG_GPIO_P##n##_DATA_ADDR);<br>-<br>-static void ex_sb_gpio_init(struct device *dev)<br>-{<br>- const int base = 0xb00;<br>- u32 gpio_enable_mask = 0;<br>- /* S/B register 63h - 62h : GPIO Port Config IO Base Address */<br>- pci_write_config16(dev, SB_REG_GPIO_CFG_IO_BASE, base | 1);<br>- /* Set GPIO port 0~9 base address.<br>- * Config Base + 04h, 08h, 0ch... : GPIO port 0~9 data/dir decode addr.<br>- * Bit 31-16 : DBA, GPIO direction base address.<br>- * Bit 15-0 : DPBA, GPIO data port base address.<br>- * */<br>-#if IS_ENABLED(CONFIG_GPIO_P0_ENABLE)<br>- SETUP_GPIO_ADDR(0)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P1_ENABLE)<br>- SETUP_GPIO_ADDR(1)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P2_ENABLE)<br>- SETUP_GPIO_ADDR(2)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P3_ENABLE)<br>- SETUP_GPIO_ADDR(3)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P4_ENABLE)<br>- SETUP_GPIO_ADDR(4)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P5_ENABLE)<br>- SETUP_GPIO_ADDR(5)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P6_ENABLE)<br>- SETUP_GPIO_ADDR(6)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P7_ENABLE)<br>- SETUP_GPIO_ADDR(7)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P8_ENABLE)<br>- SETUP_GPIO_ADDR(8)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P9_ENABLE)<br>- SETUP_GPIO_ADDR(9)<br>-#endif<br>- /* Enable GPIO port 0~9. */<br>- outl(gpio_enable_mask, base);<br>- /* Set GPIO port 0-9 initial dir and data. */<br>-#if IS_ENABLED(CONFIG_GPIO_P0_ENABLE)<br>- INIT_GPIO(0)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P1_ENABLE)<br>- INIT_GPIO(1)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P2_ENABLE)<br>- INIT_GPIO(2)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P3_ENABLE)<br>- INIT_GPIO(3)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P4_ENABLE)<br>- INIT_GPIO(4)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P5_ENABLE)<br>- INIT_GPIO(5)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P6_ENABLE)<br>- INIT_GPIO(6)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P7_ENABLE)<br>- INIT_GPIO(7)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P8_ENABLE)<br>- INIT_GPIO(8)<br>-#endif<br>-#if IS_ENABLED(CONFIG_GPIO_P9_ENABLE)<br>- INIT_GPIO(9)<br>-#endif<br>- /* Disable GPIO Port Config IO Base Address. */<br>- pci_write_config16(dev, SB_REG_GPIO_CFG_IO_BASE, 0x0);<br>-}<br>-<br>-static u32 make_uart_config(u16 base, u8 irq)<br>-{<br>- u8 mapped_irq = irq_to_int_routing[irq];<br>- u32 cfg = 0;<br>- cfg |= 1 << 23; // UE = enabled.<br>- cfg |= (mapped_irq << 16); // UIRT.<br>- cfg |= base; // UIOA.<br>- return cfg;<br>-}<br>-<br>-#define SETUP_UART(n) \<br>- uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\<br>- outl(uart_cfg, base + (n - 1) * 4);<br>-<br>-static void ex_sb_uart_init(struct device *dev)<br>-{<br>- const int base = 0xc00;<br>- u32 uart_cfg = 0;<br>- /* S/B register 61h - 60h : UART Config IO Base Address */<br>- pci_write_config16(dev, SB_REG_UART_CFG_IO_BASE, base | 1);<br>- /* setup UART */<br>-#if IS_ENABLED(CONFIG_UART1_ENABLE)<br>- SETUP_UART(1)<br>-#endif<br>-#if IS_ENABLED(CONFIG_UART2_ENABLE)<br>- SETUP_UART(2)<br>-#endif<br>-#if IS_ENABLED(CONFIG_UART3_ENABLE)<br>- SETUP_UART(3)<br>-#endif<br>-#if IS_ENABLED(CONFIG_UART4_ENABLE)<br>- SETUP_UART(4)<br>-#endif<br>-#if IS_ENABLED(CONFIG_UART5_ENABLE)<br>- SETUP_UART(5)<br>-#endif<br>-#if IS_ENABLED(CONFIG_UART6_ENABLE)<br>- SETUP_UART(6)<br>-#endif<br>-#if IS_ENABLED(CONFIG_UART7_ENABLE)<br>- SETUP_UART(7)<br>-#endif<br>-#if IS_ENABLED(CONFIG_UART8_ENABLE)<br>- SETUP_UART(8)<br>-#endif<br>-#if IS_ENABLED(CONFIG_UART9_ENABLE)<br>- SETUP_UART(9)<br>-#endif<br>-#if IS_ENABLED(CONFIG_UART10_ENABLE)<br>- SETUP_UART(10)<br>-#endif<br>- /* Keep UART Config I/O base address */<br>- //pci_write_config16(SB, SB_REG_UART_CFG_IO_BASE, 0x0);<br>-}<br>-<br>-static void i2c_init(struct device *dev)<br>-{<br>- u8 mapped_irq = irq_to_int_routing[I2C0_IRQ];<br>- u32 cfg = 0;<br>- cfg |= 1 << 31; // UE = enabled.<br>- cfg |= (mapped_irq << 16); // IIRT0.<br>- cfg |= CONFIG_I2C_BASE; // UIOA.<br>- pci_write_config32(dev, SB_REG_II2CCR, cfg);<br>-}<br>-<br>-static int get_rtc_update_in_progress(void)<br>-{<br>- if (cmos_read(RTC_REG_A) & RTC_UIP)<br>- return 1;<br>- return 0;<br>-}<br>-<br>-static void unsafe_read_cmos_rtc(u8 rtc[7])<br>-{<br>- rtc[0] = cmos_read(RTC_CLK_ALTCENTURY);<br>- rtc[1] = cmos_read(RTC_CLK_YEAR);<br>- rtc[2] = cmos_read(RTC_CLK_MONTH);<br>- rtc[3] = cmos_read(RTC_CLK_DAYOFMONTH);<br>- rtc[4] = cmos_read(RTC_CLK_HOUR);<br>- rtc[5] = cmos_read(RTC_CLK_MINUTE);<br>- rtc[6] = cmos_read(RTC_CLK_SECOND);<br>-}<br>-<br>-static void read_cmos_rtc(u8 rtc[7])<br>-{<br>- /* Read RTC twice and check update-in-progress flag, to make<br>- * sure RTC is correct */<br>- u8 rtc_new[7];<br>- while (get_rtc_update_in_progress()) ;<br>- unsafe_read_cmos_rtc(rtc_new);<br>- do {<br>- memcpy(rtc, rtc_new, 7);<br>- while (get_rtc_update_in_progress()) ;<br>- unsafe_read_cmos_rtc(rtc_new);<br>- } while (memcmp(rtc_new, rtc, 7) != 0);<br>-}<br>-<br>-/*<br>- * Convert a number in decimal format into the BCD format.<br>- * Return 255 if not a valid BCD value.<br>- */<br>-static u8 bcd2dec(u8 bcd)<br>-{<br>- u8 h, l;<br>- h = bcd >> 4;<br>- l = bcd & 0xf;<br>- if (h > 9 || l > 9)<br>- return 255;<br>- return h * 10 + l;<br>-}<br>-<br>-static void fix_cmos_rtc_time(void)<br>-{<br>- /* Read RTC data. */<br>- u8 rtc[7];<br>- read_cmos_rtc(rtc);<br>-<br>- /* Convert RTC from BCD format to binary. */<br>- u8 bin_rtc[7];<br>- int i;<br>- for (i = 0; i < 7; i++) {<br>- bin_rtc[i] = bcd2dec(rtc[i]);<br>- }<br>-<br>- /* If RTC date is invalid, fix it. */<br>- if (bin_rtc[0] > 99 || bin_rtc[1] > 99 || bin_rtc[2] > 12 || bin_rtc[3] > 31) {<br>- /* Set PC compatible timing mode. */<br>- cmos_write(0x26, RTC_REG_A);<br>- cmos_write(0x02, RTC_REG_B);<br>- /* Now setup a default date 2008/08/08 08:08:08. */<br>- cmos_write(0x8, RTC_CLK_SECOND);<br>- cmos_write(0x8, RTC_CLK_MINUTE);<br>- cmos_write(0x8, RTC_CLK_HOUR);<br>- cmos_write(0x6, RTC_CLK_DAYOFWEEK); /* Friday */<br>- cmos_write(0x8, RTC_CLK_DAYOFMONTH);<br>- cmos_write(0x8, RTC_CLK_MONTH);<br>- cmos_write(0x8, RTC_CLK_YEAR);<br>- cmos_write(0x20, RTC_CLK_ALTCENTURY);<br>- }<br>-}<br>-<br>-static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size)<br>-{<br>- struct resource *res;<br>- res = new_resource(dev, index);<br>- res->base = base;<br>- res->size = size;<br>- res->limit = 0xffffUL;<br>- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-}<br>-<br>-static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size)<br>-{<br>- /* SPI flash is in topmost of 4G memory space */<br>- struct resource *res;<br>- res = new_resource(dev, index);<br>- res->base = 0x100000000LL - flash_size;<br>- res->size = flash_size;<br>- res->limit = 0xffffffffUL;<br>- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;<br>-}<br>-<br>-static void vortex86_sb_read_resources(device_t dev)<br>-{<br>- u32 flash_size = 8 * 1024 * 1024;<br>-<br>- pci_dev_read_resources(dev);<br>-<br>- if (dev->device == 0x6011) {<br>- /* It is EX CPU southbridge */<br>- if (get_pci_dev_func(dev) != 0) {<br>- /* only for function 0, skip function 1 */<br>- return;<br>- }<br>- /* default SPI flash ROM is 64MB */<br>- flash_size = 64 * 1024 * 1024;<br>- }<br>-<br>- /* Reserve space for legacy I/O */<br>- vortex86_sb_set_io_resv(dev, 1, 0, 0x1000UL);<br>-<br>- /* Reserve space for flash */<br>- vortex86_sb_set_spi_flash_size(dev, 2, flash_size);<br>-<br>- /* Reserve space for I2C */<br>- vortex86_sb_set_io_resv(dev, 3, CONFIG_I2C_BASE, 8);<br>-}<br>-<br>-static void southbridge_init_func1(struct device *dev)<br>-{<br>- /* Handle S/B function 1 PCI IRQ routing. (SPI1/MOTOR) */<br>- u32 ext_int_routing2 = 0;<br>- /* Setup S/B function 1 PCI Extend Interrupt routing table reg 2(0xb4). */<br>- ext_int_routing2 |= irq_to_int_routing[SPI1_IRQ] << SPI1_IRQ_SHIFT;<br>- ext_int_routing2 |= irq_to_int_routing[MOTOR_IRQ] << MOTOR_IRQ_SHIFT;<br>- pci_write_config32(dev, SB1_REG_EXT_PIRQ_ROUTE2, ext_int_routing2);<br>-<br>- /* Assign in-chip PCI device IRQs. */<br>- if ((SPI1_IRQ != 0) || (MOTOR_IRQ != 0)) {<br>- unsigned char irqs[4] = { MOTOR_IRQ, SPI1_IRQ, 0, 0 };<br>- pci_assign_irqs(0, 0x10, irqs);<br>- }<br>-}<br>-<br>-static void southbridge_init(struct device *dev)<br>-{<br>- /* Check it is function 0 or 1. (Same Vendor/Device ID) */<br>- if (get_pci_dev_func(dev) != 0) {<br>- southbridge_init_func1(dev);<br>- return;<br>- }<br>- upload_dmp_keyboard_firmware(dev);<br>- vortex_sb_init(dev);<br>- if (dev->device == 0x6011) {<br>- ex_sb_gpio_init(dev);<br>- ex_sb_uart_init(dev);<br>- i2c_init(dev);<br>- }<br>- pci_routing_fixup(dev);<br>-<br>- fix_cmos_rtc_time();<br>- cmos_init(0);<br>- /* Check keyboard controller ready. If timeout, reload firmware code<br>- * and try again.<br>- */<br>- u32 retries = 10;<br>- while (!kbc_wait_system_flag()) {<br>- if (!retries) {<br>- post_code(POST_DMP_KBD_IS_BAD);<br>- die("The keyboard timeout occurred too often. "<br>- "Your CPU is probably defect. "<br>- "Contact your dealer to replace it\n");<br>- }<br>- upload_dmp_keyboard_firmware(dev);<br>- retries--;<br>- }<br>- post_code(POST_DMP_KBD_IS_READY);<br>- pc_keyboard_init(NO_AUX_DEVICE);<br>-}<br>-<br>-static struct device_operations vortex_sb_ops = {<br>- .read_resources = vortex86_sb_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = &southbridge_init,<br>- .scan_bus = scan_lpc_bus,<br>- .enable = 0,<br>- .ops_pci = 0,<br>-};<br>-<br>-static const struct pci_driver pci_driver_6011 __pci_driver = {<br>- .ops = &vortex_sb_ops,<br>- .vendor = PCI_VENDOR_ID_RDC,<br>- .device = 0x6011, /* EX CPU S/B ID */<br>-};<br>-<br>-struct chip_operations southbridge_dmp_vortex86ex_ops = {<br>- CHIP_NAME("DMP Vortex86EX Southbridge")<br>- .enable_dev = 0<br>-};<br>diff --git a/src/soc/dmp/vortex86ex/southbridge.h b/src/soc/dmp/vortex86ex/southbridge.h<br>deleted file mode 100644<br>index c2b9102..0000000<br>--- a/src/soc/dmp/vortex86ex/southbridge.h<br>+++ /dev/null<br>@@ -1,42 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef SOUTHBRIDGE_H<br>-#define SOUTHBRIDGE_H<br>-<br>-#define SB PCI_DEV(0, 7, 0)<br>-#define SB_REG_LPCCR 0x41<br>-#define SB_REG_FRCSCR 0x42<br>-#define SB_REG_PIRQ_ROUTE 0x58<br>-#define SB_REG_UART_CFG_IO_BASE 0x60<br>-#define SB_REG_GPIO_CFG_IO_BASE 0x62<br>-#define SB_REG_CS_BASE0 0x90<br>-#define SB_REG_CS_BASE_MASK0 0x94<br>-#define SB_REG_CS_BASE1 0x98<br>-#define SB_REG_CS_BASE_MASK1 0x9c<br>-#define SB_REG_IPPCR 0xb0<br>-#define SB_REG_EXT_PIRQ_ROUTE 0xb4<br>-#define SB_REG_OCDCR 0xbc<br>-#define SB_REG_IPFCR 0xc0<br>-#define SB_REG_FRWPR 0xc4<br>-#define SB_REG_STRAP 0xce<br>-#define SB_REG_II2CCR 0xd4<br>-<br>-#define SB1 PCI_DEV(0, 7, 1)<br>-#define SB1_REG_EXT_PIRQ_ROUTE2 0xb4<br>-<br>-#define SYSTEM_CTL_PORT 0x92<br>-<br>-#endif /* SOUTHBRIDGE_H */<br>diff --git a/src/soc/dmp/vortex86ex/xgi_oprom.c b/src/soc/dmp/vortex86ex/xgi_oprom.c<br>deleted file mode 100644<br>index b72157d..0000000<br>--- a/src/soc/dmp/vortex86ex/xgi_oprom.c<br>+++ /dev/null<br>@@ -1,31 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 DMP Electronics Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/********************************************************************<br>- * Change the vendor / device IDs to match the XGI Z9S VBIOS header.<br>- ********************************************************************/<br>-#include <device/pci.h><br>-u32 map_oprom_vendev(u32 vendev)<br>-{<br>- u32 new_vendev = vendev;<br>-<br>- switch (vendev) {<br>- case 0x18ca0020:<br>- new_vendev = 0x18ca0021;<br>- break;<br>- }<br>-<br>- return new_vendev;<br>-}<br></pre><p>To view, visit <a href="https://review.coreboot.org/22026">change 22026</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22026"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iee7b6005cc2964b2346aaf4dbd9b2d2112b7403f </div>
<div style="display:none"> Gerrit-Change-Number: 22026 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>