<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22029">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Intel e7505 board & chips: Remove - using LATE_CBMEM_INIT<br><br>All boards and chips that are still using LATE_CBMEM_INIT are being<br>removed as previously discussed.<br><br>If these boards and chips are updated to not use LATE_CBMEM_INIT, they<br>can be restored to the active codebase from the 4.8 branch.<br><br>chips:<br>/northbridge/intel/i855<br><br>Mainboards:<br>mainboard/lanner/em8510<br><br>Change-Id: Ic9ba0ba7e2b6e602a5749cc531dd705c49e3f08d<br>Signed-off-by: Martin Roth <gaumless@gmail.com><br>---<br>D src/mainboard/lanner/Kconfig<br>D src/mainboard/lanner/Kconfig.name<br>D src/mainboard/lanner/em8510/Kconfig<br>D src/mainboard/lanner/em8510/Kconfig.name<br>D src/mainboard/lanner/em8510/board_info.txt<br>D src/mainboard/lanner/em8510/cmos.layout<br>D src/mainboard/lanner/em8510/devicetree.cb<br>D src/mainboard/lanner/em8510/irq_tables.c<br>D src/mainboard/lanner/em8510/romstage.c<br>D src/northbridge/intel/i855/Kconfig<br>D src/northbridge/intel/i855/Makefile.inc<br>D src/northbridge/intel/i855/debug.c<br>D src/northbridge/intel/i855/i855.h<br>D src/northbridge/intel/i855/northbridge.c<br>D src/northbridge/intel/i855/raminit.c<br>D src/northbridge/intel/i855/raminit.h<br>D src/northbridge/intel/i855/reset_test.c<br>17 files changed, 0 insertions(+), 1,692 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/22029/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/lanner/Kconfig b/src/mainboard/lanner/Kconfig<br>deleted file mode 100644<br>index 3b304ba..0000000<br>--- a/src/mainboard/lanner/Kconfig<br>+++ /dev/null<br>@@ -1,16 +0,0 @@<br>-if VENDOR_LANNER<br>-<br>-choice<br>- prompt "Mainboard model"<br>-<br>-source "src/mainboard/lanner/*/Kconfig.name"<br>-<br>-endchoice<br>-<br>-source "src/mainboard/lanner/*/Kconfig"<br>-<br>-config MAINBOARD_VENDOR<br>- string<br>- default "Lanner"<br>-<br>-endif # VENDOR_LANNER<br>diff --git a/src/mainboard/lanner/Kconfig.name b/src/mainboard/lanner/Kconfig.name<br>deleted file mode 100644<br>index 69026c5..0000000<br>--- a/src/mainboard/lanner/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config VENDOR_LANNER<br>- bool "Lanner"<br>diff --git a/src/mainboard/lanner/em8510/Kconfig b/src/mainboard/lanner/em8510/Kconfig<br>deleted file mode 100644<br>index 2919df9..0000000<br>--- a/src/mainboard/lanner/em8510/Kconfig<br>+++ /dev/null<br>@@ -1,25 +0,0 @@<br>-if BOARD_LANNER_EM8510<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_INTEL_SOCKET_MPGA479M<br>- select NORTHBRIDGE_INTEL_I855<br>- select SOUTHBRIDGE_INTEL_I82801DX<br>- select SUPERIO_WINBOND_W83627THG<br>- select HAVE_OPTION_TABLE<br>- select HAVE_PIRQ_TABLE<br>- select BOARD_ROMSIZE_KB_512<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default lanner/em8510<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "EM-8510"<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 10<br>-<br>-endif # BOARD_LANNER_EM8510<br>diff --git a/src/mainboard/lanner/em8510/Kconfig.name b/src/mainboard/lanner/em8510/Kconfig.name<br>deleted file mode 100644<br>index 1ab59af..0000000<br>--- a/src/mainboard/lanner/em8510/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_LANNER_EM8510<br>- bool "EM-8510"<br>diff --git a/src/mainboard/lanner/em8510/board_info.txt b/src/mainboard/lanner/em8510/board_info.txt<br>deleted file mode 100644<br>index 31cf750..0000000<br>--- a/src/mainboard/lanner/em8510/board_info.txt<br>+++ /dev/null<br>@@ -1 +0,0 @@<br>-Category: desktop<br>diff --git a/src/mainboard/lanner/em8510/cmos.layout b/src/mainboard/lanner/em8510/cmos.layout<br>deleted file mode 100644<br>index b8ea936..0000000<br>--- a/src/mainboard/lanner/em8510/cmos.layout<br>+++ /dev/null<br>@@ -1,28 +0,0 @@<br>-entries<br>-<br>-0 384 r 0 reserved_memory<br>-384 1 e 4 boot_option<br>-388 4 h 0 reboot_counter<br>-#392 3 r 0 unused<br>-400 1 e 1 power_on_after_fail<br>-412 4 e 6 debug_level<br>-456 1 e 1 ECC_memory<br>-1008 16 h 0 check_sum<br>-<br>-enumerations<br>-<br>-#ID value text<br>-1 0 Disable<br>-1 1 Enable<br>-2 0 Enable<br>-2 1 Disable<br>-4 0 Fallback<br>-4 1 Normal<br>-6 6 Notice<br>-6 7 Info<br>-6 8 Debug<br>-6 9 Spew<br>-<br>-checksums<br>-<br>-checksum 392 1007 1008<br>diff --git a/src/mainboard/lanner/em8510/devicetree.cb b/src/mainboard/lanner/em8510/devicetree.cb<br>deleted file mode 100644<br>index 0a91cc9..0000000<br>--- a/src/mainboard/lanner/em8510/devicetree.cb<br>+++ /dev/null<br>@@ -1,56 +0,0 @@<br>-chip northbridge/intel/i855<br>- device domain 0 on<br>- device pci 0.0 on end<br>- chip southbridge/intel/i82801dx<br>-# pci 11.0 on end<br>-# pci 11.1 on end<br>-# pci 11.2 on end<br>-# pci 11.3 on end<br>-# pci 11.4 on end<br>-# pci 11.5 on end<br>-# pci 11.6 on end<br>-# pci 12.0 on end<br>- register "enable_usb" = "0"<br>- register "enable_native_ide" = "0"<br>- device pci 1f.0 on<br>- chip superio/winbond/w83627thg # link 1<br>- device pnp 2e.0 on # Floppy<br>- io 0x60 = 0x3f0<br>- irq 0x70 = 6<br>- drq 0x74 = 2<br>- end<br>- device pnp 2e.1 on # Parallel Port<br>- io 0x60 = 0x378<br>- irq 0x70 = 7<br>- end<br>- device pnp 2e.2 on # Com1<br>- io 0x60 = 0x3f8<br>- irq 0x70 = 4<br>- end<br>- device pnp 2e.3 on # Com2<br>- io 0x60 = 0x2f8<br>- irq 0x70 = 3<br>- end<br>- device pnp 2e.5 on # Keyboard<br>- io 0x60 = 0x60<br>- io 0x62 = 0x64<br>- irq 0x70 = 1<br>- irq 0x72 = 12<br>- end<br>- device pnp 2e.7 off end # GAME_MIDI_GIPO1<br>- device pnp 2e.8 off end # GPIO2<br>- device pnp 2e.9 off end # GPIO3<br>- device pnp 2e.a off end # ACPI<br>- device pnp 2e.b on # HW Monitor<br>- io 0x60 = 0x290<br>- end<br>- end<br>- end<br>- end<br>- end<br>- device cpu_cluster 0 on<br>- chip cpu/intel/socket_mPGA479M<br>- device lapic 0 on end<br>- end<br>- end<br>-end<br>diff --git a/src/mainboard/lanner/em8510/irq_tables.c b/src/mainboard/lanner/em8510/irq_tables.c<br>deleted file mode 100644<br>index 6e769d7..0000000<br>--- a/src/mainboard/lanner/em8510/irq_tables.c<br>+++ /dev/null<br>@@ -1,52 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2010 Travelping GmbH <info@travelping.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32 + 16 * 10, /* Max. number of devices on the bus */<br>- 0x00, /* Interrupt router bus */<br>- (0x1f << 3) | 0x0, /* Interrupt router dev */<br>- 0x1e20, /* IRQs devoted exclusively to PCI usage */<br>- 0x8086, /* Vendor */<br>- 0x24cc, /* Device */<br>- 0, /* Miniport */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0x39, /* Checksum (has to be set to some value that<br>- * would give 0 after the sum of all bytes<br>- * for this structure (including checksum).<br>- */<br>- {<br>- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x01, (0x0f << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x1, 0x0},<br>- {0x01, (0x0a << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x2, 0x0},<br>- {0x01, (0x05 << 3) | 0x0, {{0x68, 0xdeb8}, {0x69, 0xdeb8}, {0x6a, 0xdeb8}, {0x6b, 0xdeb8}}, 0x3, 0x0},<br>- {0x01, (0x06 << 3) | 0x0, {{0x69, 0xdeb8}, {0x6a, 0xdeb8}, {0x6b, 0xdeb8}, {0x68, 0xdeb8}}, 0x4, 0x0},<br>- {0x01, (0x07 << 3) | 0x0, {{0x6a, 0xdeb8}, {0x6b, 0xdeb8}, {0x68, 0xdeb8}, {0x69, 0xdeb8}}, 0x5, 0x0},<br>- {0x01, (0x09 << 3) | 0x0, {{0x6b, 0xdeb8}, {0x68, 0xdeb8}, {0x69, 0xdeb8}, {0x6a, 0xdeb8}}, 0x6, 0x0},<br>- {0x00, (0x1e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},<br>- {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdeb8}, {0x60, 0xdeb8}, {0x60, 0xdeb8}, {0x60, 0xdeb8}}, 0x0, 0x0},<br>- {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdeb8}, {0x61, 0xdeb8}, {0x60, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},<br>- {0x00, (0x1d << 3) | 0x0, {{0x60, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0xdeb8}, {0x6b, 0xdeb8}}, 0x0, 0x0},<br>- }<br>-};<br>-<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c<br>deleted file mode 100644<br>index 126d942..0000000<br>--- a/src/mainboard/lanner/em8510/romstage.c<br>+++ /dev/null<br>@@ -1,75 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Original take from digitallogic/adl855pc<br>- *<br>- * Copyright (C) 2010 Travelping GmbH <info@travelping.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <device/pci_def.h><br>-#include <arch/io.h><br>-#include <device/pnp_def.h><br>-#include <stdlib.h><br>-#include <lib.h><br>-#include <spd.h><br>-#include <pc80/mc146818rtc.h><br>-#include <console/console.h><br>-#include <southbridge/intel/i82801dx/i82801dx.h><br>-#include <northbridge/intel/i855/raminit.h><br>-#include "northbridge/intel/i855/debug.c"<br>-#include <superio/winbond/common/winbond.h><br>-#include <superio/winbond/w83627thg/w83627thg.h><br>-#include <cpu/x86/bist.h><br>-#include <cpu/intel/romstage.h><br>-<br>-#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)<br>-<br>-static inline int spd_read_byte(unsigned device, unsigned address)<br>-{<br>- return smbus_read_byte(device, address);<br>-}<br>-<br>-#include "northbridge/intel/i855/raminit.c"<br>-#include "northbridge/intel/i855/reset_test.c"<br>-<br>-void mainboard_romstage_entry(unsigned long bist)<br>-{<br>- if (bist == 0) {<br>-#if 0<br>- enable_lapic();<br>- init_timer();<br>-#endif<br>- }<br>-<br>- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>- console_init();<br>-<br>- /* Halt if there was a built in self test failure */<br>- report_bist_failure(bist);<br>-<br>-#if 0<br>- print_pci_devices();<br>-#endif<br>-<br>- if (!bios_reset_detected()) {<br>- enable_smbus();<br>-#if 1<br>- dump_spd_registers();<br>- dump_smbus_registers();<br>-#endif<br>- sdram_set_registers();<br>- sdram_set_spd_registers();<br>- sdram_enable();<br>- }<br>-}<br>diff --git a/src/northbridge/intel/i855/Kconfig b/src/northbridge/intel/i855/Kconfig<br>deleted file mode 100644<br>index a9439dc..0000000<br>--- a/src/northbridge/intel/i855/Kconfig<br>+++ /dev/null<br>@@ -1,35 +0,0 @@<br>-config NORTHBRIDGE_INTEL_I855<br>- bool<br>- select NO_MMCONF_SUPPORT<br>- select HAVE_DEBUG_RAM_SETUP<br>- select LATE_CBMEM_INIT<br>-<br>-choice<br>- prompt "Onboard graphics"<br>- default I855_VIDEO_MB_8MB<br>- depends on NORTHBRIDGE_INTEL_I855<br>-<br>-config I855_VIDEO_MB_OFF<br>- bool "Disabled, 0KB"<br>-config I855_VIDEO_MB_1MB<br>- bool "Enabled, 1MB"<br>-config I855_VIDEO_MB_4MB<br>- bool "Enabled, 4MB"<br>-config I855_VIDEO_MB_8MB<br>- bool "Enabled, 8MB"<br>-config I855_VIDEO_MB_16MB<br>- bool "Enabled, 16MB"<br>-config I855_VIDEO_MB_32MB<br>- bool "Enabled, 32MB"<br>-<br>-endchoice<br>-<br>-config VIDEO_MB<br>- int<br>- default 0 if I855_VIDEO_MB_OFF<br>- default 1 if I855_VIDEO_MB_1MB<br>- default 4 if I855_VIDEO_MB_4MB<br>- default 8 if I855_VIDEO_MB_8MB<br>- default 16 if I855_VIDEO_MB_16MB<br>- default 32 if I855_VIDEO_MB_32MB<br>- depends on NORTHBRIDGE_INTEL_I855<br>diff --git a/src/northbridge/intel/i855/Makefile.inc b/src/northbridge/intel/i855/Makefile.inc<br>deleted file mode 100644<br>index 4dfc358..0000000<br>--- a/src/northbridge/intel/i855/Makefile.inc<br>+++ /dev/null<br>@@ -1,5 +0,0 @@<br>-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I855),y)<br>-<br>-ramstage-y += northbridge.c<br>-<br>-endif<br>diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c<br>deleted file mode 100644<br>index bdf2523..0000000<br>--- a/src/northbridge/intel/i855/debug.c<br>+++ /dev/null<br>@@ -1,129 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2003 Ronald G. Minnich<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <spd.h><br>-<br>-static void print_debug_pci_dev(unsigned dev)<br>-{<br>- printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",<br>- (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 0x07);<br>-}<br>-<br>-static inline void print_pci_devices(void)<br>-{<br>- pci_devfn_t dev;<br>- for (dev = PCI_DEV(0, 0, 0);<br>- dev <= PCI_DEV(0, 0x1f, 0x7);<br>- dev += PCI_DEV(0,0,1)) {<br>- uint32_t id;<br>- id = pci_read_config32(dev, PCI_VENDOR_ID);<br>- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||<br>- (((id >> 16) & 0xffff) == 0xffff) ||<br>- (((id >> 16) & 0xffff) == 0x0000)) {<br>- continue;<br>- }<br>- print_debug_pci_dev(dev);<br>- printk(BIOS_DEBUG, "\n");<br>- }<br>-}<br>-<br>-static void dump_pci_device(unsigned dev)<br>-{<br>- int i;<br>- print_debug_pci_dev(dev);<br>- printk(BIOS_DEBUG, "\n");<br>-<br>- for (i = 0; i <= 255; i++) {<br>- unsigned char val;<br>- if ((i & 0x0f) == 0)<br>- printk(BIOS_DEBUG, "%02x:", i);<br>- val = pci_read_config8(dev, i);<br>- printk(BIOS_DEBUG, " %02x", val);<br>- if ((i & 0x0f) == 0x0f)<br>- printk(BIOS_DEBUG, "\n");<br>- }<br>-}<br>-<br>-static inline void dump_pci_devices(void)<br>-{<br>- pci_devfn_t dev;<br>- for (dev = PCI_DEV(0, 0, 0);<br>- dev <= PCI_DEV(0, 0x1f, 0x7);<br>- dev += PCI_DEV(0,0,1)) {<br>- uint32_t id;<br>- id = pci_read_config32(dev, PCI_VENDOR_ID);<br>- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||<br>- (((id >> 16) & 0xffff) == 0xffff) ||<br>- (((id >> 16) & 0xffff) == 0x0000)) {<br>- continue;<br>- }<br>- dump_pci_device(dev);<br>- }<br>-}<br>-<br>-static inline void dump_spd_registers(void)<br>-{<br>- int i;<br>- printk(BIOS_DEBUG, "\n");<br>- for (i = 0; i < 2; i++) {<br>- unsigned device;<br>- device = DIMM0 + i;<br>- if (device) {<br>- int j;<br>- printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);<br>- for (j = 0; j < 256; j++) {<br>- int status;<br>- unsigned char byte;<br>- if ((j & 0xf) == 0)<br>- printk(BIOS_DEBUG, "\n%02x: ", j);<br>- status = smbus_read_byte(device, j);<br>- if (status < 0) {<br>- printk(BIOS_DEBUG, "bad device\n");<br>- break;<br>- }<br>- byte = status & 0xff;<br>- printk(BIOS_DEBUG, "%02x ", byte);<br>- }<br>- printk(BIOS_DEBUG, "\n");<br>- }<br>- }<br>-}<br>-<br>-static inline void dump_smbus_registers(void)<br>-{<br>- int i;<br>- printk(BIOS_DEBUG, "\n");<br>- for (i = 1; i < 0x80; i++) {<br>- unsigned device;<br>- device = i;<br>- int j;<br>- printk(BIOS_DEBUG, "smbus: %02x", device);<br>- for (j = 0; j < 256; j++) {<br>- int status;<br>- unsigned char byte;<br>- if ((j & 0xf) == 0)<br>- printk(BIOS_DEBUG, "\n%02x: ", j);<br>- status = smbus_read_byte(device, j);<br>- if (status < 0) {<br>- printk(BIOS_DEBUG, "bad device\n");<br>- break;<br>- }<br>- byte = status & 0xff;<br>- printk(BIOS_DEBUG, "%02x ", byte);<br>- }<br>- printk(BIOS_DEBUG, "\n");<br>- }<br>-}<br>diff --git a/src/northbridge/intel/i855/i855.h b/src/northbridge/intel/i855/i855.h<br>deleted file mode 100644<br>index 467875f..0000000<br>--- a/src/northbridge/intel/i855/i855.h<br>+++ /dev/null<br>@@ -1,77 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2010 Travelping GmbH <info@travelping.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef NORTHBRIDGE_INTEL_I855_I855_H<br>-#define NORTHBRIDGE_INTEL_I855_I855_H<br>-<br>-/* Host-Hub Interface Bridge */<br>-#define GMC 0x50 /* GMCH Misc. Control (0x0000) */<br>-#define GGC 0x52 /* GMCH Graphics Control (0x0030) */<br>-#define DAFC 0x54 /* Device and Function Control (0x0000) */<br>-#define FDHC 0x58 /* Fixed Dram Hole Control */<br>-#define PAM0 0x59 /* Programmable Attribute Map #0 (0x00) */<br>-#define PAM1 0x5a /* Programmable Attribute Map #1 (0x00) */<br>-#define PAM2 0x5b /* Programmable Attribute Map #2 (0x00) */<br>-#define PAM3 0x5c /* Programmable Attribute Map #3 (0x00) */<br>-#define PAM4 0x5d /* Programmable Attribute Map #4 (0x00) */<br>-#define PAM5 0x5e /* Programmable Attribute Map #5 (0x00) */<br>-#define PAM6 0x5f /* Programmable Attribute Map #6 (0x00) */<br>-#define SMRAM 0x60 /* System Management RAM Control (0x02) */<br>-#define ESMRAMC 0x61 /* Extended System Management RAM Control (0x38) */<br>-#define ERRSTS 0x62 /* Error Status (0x0000) */<br>-#define ERRCMD 0x64 /* Error Command (0x0000) */<br>-#define SMICMD 0x66 /* SMI Command (0x00) */<br>-#define SCICMD 0x67 /* SCI Command (0x00) */<br>-#define SHIC 0x74 /* Secondary Host Interface Control Register (0x00006010) */<br>-#define ACAPID 0xA0 /* AGP Capability Identifier (0x00200002) */<br>-#define AGPSTAT 0xA4 /* AGP Status Register (0x1f000217) */<br>-#define AGPCMD 0xA8 /* AGP Command (0x0000) */<br>-#define AGPCTRL 0xB0 /* AGP Control (0x0000) */<br>-#define AFT 0xB2 /* AGP Functional Test (0xe9f0) */<br>-#define ATTBASE 0xB8 /* Aperture Translation Table Base (0x00000000) */<br>-#define AMTT 0xBC /* AGP Interface Multi Transaction Timer (0x00) */<br>-#define LPTT 0xBD /* Low Priority Transaction Timer (0x00) */<br>-#define HEM 0xF0 /* Host Error Control/Status/Obs (0x00000000) */<br>-<br>-/* Main Memory Control */<br>-#define DRB 0x40 /* DRAM Row 0-3 Boundary (0x00000000) */<br>-#define DRA 0x50 /* DRAM Row 0-3 Attribute (0x7777) */<br>-#define DRT 0x60 /* DRAM Timing (0x18004425) */<br>-#define PWRMG 0x68 /* DRAM Controller Power Management Control (0x00000000) */<br>-#define DRC 0x70 /* DRAM Controller Mode (0x00000081) */<br>-#define DTC 0xA0 /* DRAM Throttling Control (0x00000000) */<br>-<br>-#define DRT_CAS_MASK (3 << 5)<br>-#define DRT_CAS_2_0 (1 << 5)<br>-#define DRT_CAS_2_5 (0 << 5)<br>-<br>-#define DRT_TRP_MASK 3<br>-#define DRT_TRP_4 0<br>-#define DRT_TRP_3 1<br>-#define DRT_TRP_2 2<br>-<br>-#define DRT_RCD_MASK (3 << 2)<br>-#define DRT_RCD_4 (0 << 2)<br>-#define DRT_RCD_3 (1 << 2)<br>-#define DRT_RCD_2 (2 << 2)<br>-<br>-#define DRT_TRAS_MIN_MASK (3 << 9)<br>-#define DRT_TRAS_MIN_8 (0 << 9)<br>-#define DRT_TRAS_MIN_7 (1 << 9)<br>-#define DRT_TRAS_MIN_6 (2 << 9)<br>-#define DRT_TRAS_MIN_5 (3 << 9)<br>-<br>-#endif /* NORTHBRIDGE_INTEL_I855_I855_H */<br>diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c<br>deleted file mode 100644<br>index 3398d66..0000000<br>--- a/src/northbridge/intel/i855/northbridge.c<br>+++ /dev/null<br>@@ -1,145 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2003 Ronald G. Minnich<br>- * Copyright (C) 2003-2004 Eric W. Biederman<br>- * Copyright (C) 2006 Jon Dufresne <jon.dufresne@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include <cbmem.h><br>-#include <cpu/x86/cache.h><br>-#include <cpu/cpu.h><br>-<br>-static void northbridge_init(device_t dev)<br>-{<br>- printk(BIOS_SPEW, "Northbridge init\n");<br>-}<br>-<br>-static struct device_operations northbridge_operations = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = northbridge_init,<br>- .enable = 0,<br>- .ops_pci = 0,<br>-};<br>-<br>-static const struct pci_driver northbridge_driver __pci_driver = {<br>- .ops = &northbridge_operations,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x3580,<br>-};<br>-<br>-static void pci_domain_set_resources(device_t dev)<br>-{<br>- device_t mc_dev;<br>- uint32_t pci_tolm;<br>-<br>- printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor);<br>- printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device);<br>-<br>- pci_tolm = find_pci_tolm(dev->link_list);<br>- mc_dev = dev->link_list->children->sibling;<br>- printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor);<br>- printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device);<br>-<br>- if (mc_dev) {<br>- /* Figure out which areas are/should be occupied by RAM.<br>- * This is all computed in kilobytes and converted to/from<br>- * the memory controller right at the edges.<br>- * Having different variables in different units is<br>- * too confusing to get right. Kilobytes are good up to<br>- * 4 Terabytes of RAM...<br>- */<br>- unsigned long tomk, tolmk;<br>- int idx;<br>-<br>- /* Get the value of the highest DRB. This tells the end of<br>- * the physical memory. The units are ticks of 32MB<br>- * i.e. 1 means 32MB.<br>- */<br>- tomk = (unsigned long)pci_read_config8(mc_dev, 0x43);<br>- tomk = tomk * 32 * 1024;<br>- /* add vga_mem detection */<br>- tomk = tomk - 16 * 1024;<br>- /* Compute the top of Low memory */<br>- tolmk = pci_tolm >> 10;<br>- if (tolmk >= tomk) {<br>- /* The PCI hole does not overlap memory<br>- */<br>- tolmk = tomk;<br>- }<br>- /* Write the RAM configuration registers,<br>- * preserving the reserved bits.<br>- */<br>-<br>- /* Report the memory regions */<br>- printk(BIOS_DEBUG, "tomk = %ld\n", tomk);<br>- printk(BIOS_DEBUG, "tolmk = %ld\n", tolmk);<br>-<br>- idx = 10;<br>- /* avoid pam region */<br>- ram_resource(dev, idx++, 0, 640);<br>- /* ram_resource(dev, idx++, 1024, tolmk - 1024); */<br>- ram_resource(dev, idx++, 768, tolmk - 768);<br>-<br>- set_late_cbmem_top(tomk * 1024);<br>- }<br>- assign_resources(dev->link_list);<br>-}<br>-<br>-static struct device_operations pci_domain_ops = {<br>- .read_resources = pci_domain_read_resources,<br>- .set_resources = pci_domain_set_resources,<br>- .enable_resources = NULL,<br>- .init = NULL,<br>- .scan_bus = pci_domain_scan_bus,<br>- .ops_pci_bus = pci_bus_default_ops,<br>-};<br>-<br>-static void cpu_bus_init(device_t dev)<br>-{<br>- initialize_cpus(dev->link_list);<br>-}<br>-<br>-static struct device_operations cpu_bus_ops = {<br>- .read_resources = DEVICE_NOOP,<br>- .set_resources = DEVICE_NOOP,<br>- .enable_resources = DEVICE_NOOP,<br>- .init = cpu_bus_init,<br>- .scan_bus = 0,<br>-};<br>-<br>-static void enable_dev(struct device *dev)<br>-{<br>- /* Set the operations if it is a special bus type */<br>- if (dev->path.type == DEVICE_PATH_DOMAIN) {<br>- dev->ops = &pci_domain_ops;<br>- }<br>- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {<br>- dev->ops = &cpu_bus_ops;<br>- }<br>-}<br>-<br>-struct chip_operations northbridge_intel_i855_ops = {<br>- CHIP_NAME("Intel 855 Northbridge")<br>- .enable_dev = enable_dev,<br>-};<br>diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c<br>deleted file mode 100644<br>index 8041951..0000000<br>--- a/src/northbridge/intel/i855/raminit.c<br>+++ /dev/null<br>@@ -1,980 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2006 Jon Dufresne <jon.dufresne@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <assert.h><br>-#include <lib.h><br>-#include <spd.h><br>-#include <sdram_mode.h><br>-#include <stdlib.h><br>-#include <delay.h><br>-#include "i855.h"<br>-<br>-/*-----------------------------------------------------------------------------<br>-Macros and definitions:<br>------------------------------------------------------------------------------*/<br>-<br>-#define VALIDATE_DIMM_COMPATIBILITY<br>-<br>-/* Debugging macros. */<br>-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>-#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)<br>-#define DUMPNORTH() dump_pci_device(NORTHBRIDGE_MMC)<br>-#else<br>-#define PRINTK_DEBUG(x...)<br>-#define DUMPNORTH()<br>-#endif<br>-<br>-#define delay() udelay(200)<br>-<br>-#define VG85X_MODE (SDRAM_BURST_4 | SDRAM_BURST_INTERLEAVED | SDRAM_CAS_2_5)<br>-<br>-/* DRC[10:8] - Refresh Mode Select (RMS).<br>- * 0x0 for Refresh Disabled (Self Refresh)<br>- * 0x1 for Refresh interval 15.6 us for 133MHz<br>- * 0x2 for Refresh interval 7.8 us for 133MHz<br>- * 0x7 for Refresh interval 64 Clocks. (Fast Refresh Mode)<br>- */<br>-#define RAM_COMMAND_REFRESH 0x1<br>-<br>-/* DRC[6:4] - SDRAM Mode Select (SMS). */<br>-#define RAM_COMMAND_SELF_REFRESH 0x0<br>-#define RAM_COMMAND_NOP 0x1<br>-#define RAM_COMMAND_PRECHARGE 0x2<br>-#define RAM_COMMAND_MRS 0x3<br>-#define RAM_COMMAND_EMRS 0x4<br>-#define RAM_COMMAND_CBR 0x6<br>-#define RAM_COMMAND_NORMAL 0x7<br>-<br>-/* DRC[29] - Initialization Complete (IC). */<br>-#define RAM_COMMAND_IC 0x1<br>-<br>-struct dimm_size {<br>- unsigned int side1;<br>- unsigned int side2;<br>-};<br>-<br>-static const uint32_t refresh_frequency[] = {<br>- /* Relative frequency (array value) of each E7501 Refresh Mode Select<br>- * (RMS) value (array index)<br>- * 0 == least frequent refresh (longest interval between refreshes)<br>- * [0] disabled -> 0<br>- * [1] 15.6 usec -> 2<br>- * [2] 7.8 usec -> 3<br>- * [3] 64 usec -> 1<br>- * [4] reserved -> 0<br>- * [5] reserved -> 0<br>- * [6] reserved -> 0<br>- * [7] 64 clocks -> 4<br>- */<br>- 0, 2, 3, 1, 0, 0, 0, 4<br>-};<br>-<br>-static const uint32_t refresh_rate_map[] = {<br>- /* Map the JEDEC spd refresh rates (array index) to i855 Refresh Mode<br>- * Select values (array value)<br>- * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0<br>- * The i855 supports only 15.6 us (1), 7.8 us (2) and<br>- * 64 clock (481 ns) (7) refresh.<br>- * [0] == 15.625 us -> 15.6 us<br>- * [1] == 3.9 us -> 481 ns<br>- * [2] == 7.8 us -> 7.8 us<br>- * [3] == 31.3 us -> 15.6 us<br>- * [4] == 62.5 us -> 15.6 us<br>- * [5] == 125 us -> 15.6 us<br>- */<br>- 1, 7, 2, 1, 1, 1<br>-};<br>-<br>-#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)<br>-<br>-/*-----------------------------------------------------------------------------<br>-SPD functions:<br>------------------------------------------------------------------------------*/<br>-<br>-static void die_on_spd_error(int spd_return_value)<br>-{<br>- if (spd_return_value < 0)<br>- PRINTK_DEBUG("Error reading SPD info: got %d\n", spd_return_value);<br>-/*<br>- if (spd_return_value < 0)<br>- die("Error reading SPD info\n");<br>-*/<br>-}<br>-<br>-/**<br>- * Calculate the page size for each physical bank of the DIMM:<br>- *<br>- * log2(page size) = (# columns) + log2(data width)<br>- *<br>- * NOTE: Page size is the total number of data bits in a row.<br>- *<br>- * @param dimm_socket_address SMBus address of DIMM socket to interrogate.<br>- * @return log2(page size) for each side of the DIMM.<br>- */<br>-static struct dimm_size sdram_spd_get_page_size(u8 dimm_socket_address)<br>-{<br>- uint16_t module_data_width;<br>- int value;<br>- struct dimm_size pgsz;<br>-<br>- pgsz.side1 = 0;<br>- pgsz.side2 = 0;<br>-<br>- // Side 1<br>- value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);<br>- die_on_spd_error(value);<br>-<br>- pgsz.side1 = value & 0xf; // # columns in bank 1<br>-<br>- /* Get the module data width and convert it to a power of two */<br>- value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);<br>- die_on_spd_error(value);<br>-<br>- module_data_width = (value & 0xff) << 8;<br>-<br>- value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);<br>- die_on_spd_error(value);<br>-<br>- module_data_width |= (value & 0xff);<br>-<br>- pgsz.side1 += log2(module_data_width);<br>-<br>- /* side two */<br>- value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);<br>- die_on_spd_error(value);<br>-<br>-/*<br>- if (value > 2)<br>- die("Bad SPD value\n");<br>-*/<br>- if (value > 2)<br>- PRINTK_DEBUG("Bad SPD value\n");<br>-<br>- if (value == 2) {<br>- pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently<br>- value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);<br>- die_on_spd_error(value);<br>-<br>- if ((value & 0xf0) != 0) {<br>- // Asymmetric banks<br>- pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */<br>- pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */<br>- }<br>- }<br>-<br>- return pgsz;<br>-}<br>-<br>-/**<br>- * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16).<br>- *<br>- * @param dimm_socket_address SMBus address of DIMM socket to interrogate.<br>- * @return Width in bits of each DIMM side's DRAMs.<br>- */<br>-static struct dimm_size sdram_spd_get_width(u8 dimm_socket_address)<br>-{<br>- int value;<br>- struct dimm_size width;<br>-<br>- width.side1 = 0;<br>- width.side2 = 0;<br>-<br>- value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);<br>- die_on_spd_error(value);<br>-<br>- width.side1 = value & 0x7f; // Mask off bank 2 flag<br>-<br>- if (value & 0x80) {<br>- width.side2 = width.side1 << 1; // Bank 2 exists and is double-width<br>- } else {<br>- // If bank 2 exists, it's the same width as bank 1<br>- value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);<br>- die_on_spd_error(value);<br>-<br>-#ifdef ROMCC_IF_BUG_FIXED<br>- if (value == 2)<br>- width.side2 = width.side1;<br>-#else<br>- switch (value) {<br>- case 2:<br>- width.side2 = width.side1;<br>- break;<br>-<br>- default:<br>- break;<br>- }<br>-#endif<br>- }<br>-<br>- return width;<br>-}<br>-<br>-/**<br>- * Calculate the log base 2 size in bits of both DIMM sides.<br>- *<br>- * log2(# bits) = (# columns) + log2(data width) +<br>- * (# rows) + log2(banks per SDRAM)<br>- *<br>- * Note that it might be easier to use SPD byte 31 here, it has the DIMM size<br>- * as a multiple of 4MB. The way we do it now we can size both sides of an<br>- * asymmetric DIMM.<br>- *<br>- * @param dimm SMBus address of DIMM socket to interrogate.<br>- * @return log2(number of bits) for each side of the DIMM.<br>- */<br>-static struct dimm_size spd_get_dimm_size(unsigned dimm)<br>-{<br>- int value;<br>-<br>- // Start with log2(page size)<br>- struct dimm_size sz = sdram_spd_get_page_size(dimm);<br>-<br>- if (sz.side1 > 0) {<br>- value = spd_read_byte(dimm, SPD_NUM_ROWS);<br>- die_on_spd_error(value);<br>-<br>- sz.side1 += value & 0xf;<br>-<br>- if (sz.side2 > 0) {<br>- // Double-sided DIMM<br>- if (value & 0xF0)<br>- sz.side2 += value >> 4; // Asymmetric<br>- else<br>- sz.side2 += value; // Symmetric<br>- }<br>-<br>- value = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);<br>- die_on_spd_error(value);<br>-<br>- value = log2(value);<br>- sz.side1 += value;<br>- if (sz.side2 > 0)<br>- sz.side2 += value;<br>- }<br>-<br>- return sz;<br>-}<br>-<br>-/**<br>- * Scan for compatible DIMMs.<br>- *<br>- * @return A bitmask indicating which sockets contain a compatible DIMM.<br>- */<br>-static uint8_t spd_get_supported_dimms(void)<br>-{<br>- int i;<br>- uint8_t dimm_mask = 0;<br>-<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- u8 dimm = DIMM0 + i;<br>-<br>-#ifdef VALIDATE_DIMM_COMPATIBILITY<br>- struct dimm_size page_size;<br>- struct dimm_size sdram_width;<br>-#endif<br>- int spd_value;<br>-<br>- if (dimm == 0)<br>- continue; // No such socket on this mainboard<br>-<br>- if (spd_read_byte(dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR)<br>- continue;<br>-<br>-#ifdef VALIDATE_DIMM_COMPATIBILITY<br>- if ((spd_value = spd_read_byte(dimm, SPD_MODULE_VOLTAGE)) != SPD_VOLTAGE_SSTL2) {<br>- PRINTK_DEBUG("Skipping DIMM with unsupported voltage: %02x\n", spd_value);<br>- continue; // Unsupported voltage<br>- }<br>-<br>-/*<br>- // E7501 does not support unregistered DIMMs<br>- spd_value = spd_read_byte(dimm, SPD_MODULE_ATTRIBUTES);<br>- if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {<br>- PRINTK_DEBUG("Skipping unregistered DIMM: %02x\n", spd_value);<br>- continue;<br>- }<br>-*/<br>-<br>- page_size = sdram_spd_get_page_size(dimm);<br>- sdram_width = sdram_spd_get_width(dimm);<br>-<br>- // Validate DIMM page size<br>- // The i855 only supports page sizes of 4, 8, 16 KB per channel<br>- // NOTE: 4 KB = 32 Kb = 2^15<br>- // 16 KB = 128 Kb = 2^17<br>-<br>- if ((page_size.side1 < 15) || (page_size.side1 > 17)) {<br>- PRINTK_DEBUG("Skipping DIMM with unsupported page size: %d\n", page_size.side1);<br>- continue;<br>- }<br>-<br>- // If DIMM is double-sided, verify side2 page size<br>- if (page_size.side2 != 0) {<br>- if ((page_size.side2 < 15) || (page_size.side2 > 17)) {<br>- PRINTK_DEBUG("Skipping DIMM with unsupported page size: %d\n", page_size.side2);<br>- continue;<br>- }<br>- }<br>- // Validate SDRAM width<br>- // The i855 only supports x8 and x16 devices<br>- if ((sdram_width.side1 != 8) && (sdram_width.side1 != 16)) {<br>- PRINTK_DEBUG("Skipping DIMM with unsupported width: %d\n", sdram_width.side2);<br>- continue;<br>- }<br>-<br>- // If DIMM is double-sided, verify side2 width<br>- if (sdram_width.side2 != 0) {<br>- if ((sdram_width.side2 != 8)<br>- && (sdram_width.side2 != 16)) {<br>- PRINTK_DEBUG("Skipping DIMM with unsupported width: %d\n", sdram_width.side2);<br>- continue;<br>- }<br>- }<br>-#endif<br>- // Made it through all the checks, this DIMM is usable<br>- dimm_mask |= (1 << i);<br>- }<br>-<br>- return dimm_mask;<br>-}<br>-<br>-/*-----------------------------------------------------------------------------<br>-SDRAM configuration functions:<br>------------------------------------------------------------------------------*/<br>-<br>-static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)<br>-{<br>- int i;<br>- u32 reg32;<br>- uint8_t dimm_start_32M_multiple = 0;<br>- uint16_t i855_mode_bits = jedec_mode_bits;<br>-<br>- /* Configure the RAM command. */<br>- reg32 = pci_read_config32(NORTHBRIDGE_MMC, DRC);<br>- reg32 &= ~(7 << 4);<br>- reg32 |= (command << 4);<br>- PRINTK_DEBUG(" Sending RAM command 0x%08x\n", reg32);<br>- pci_write_config32(NORTHBRIDGE_MMC, DRC, reg32);<br>-<br>- // RAM_COMMAND_NORMAL is an exception.<br>- // It affects only the memory controller and does not need to be "sent" to the DIMMs.<br>-<br>- if (command != RAM_COMMAND_NORMAL) {<br>-<br>- // Send the command to all DIMMs by accessing a memory location within each<br>- // NOTE: for mode select commands, some of the location address bits<br>- // are part of the command<br>-<br>- // Map JEDEC mode bits to i855<br>- if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) {<br>- /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */<br>- i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (12 - 9));<br>- }<br>-<br>- for (i = 0; i < (DIMM_SOCKETS * 2); ++i) {<br>- uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i);<br>- if (dimm_end_32M_multiple > dimm_start_32M_multiple) {<br>-<br>- uint32_t dimm_start_address = dimm_start_32M_multiple << 25;<br>- PRINTK_DEBUG(" Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits);<br>- read32((void *)(dimm_start_address + i855_mode_bits));<br>-<br>- // Set the start of the next DIMM<br>- dimm_start_32M_multiple = dimm_end_32M_multiple;<br>- }<br>- }<br>- }<br>-}<br>-<br>-static void set_initialize_complete(void)<br>-{<br>- uint32_t drc_reg;<br>-<br>- drc_reg = pci_read_config32(NORTHBRIDGE_MMC, DRC);<br>- drc_reg |= (1 << 29);<br>- pci_write_config32(NORTHBRIDGE_MMC, DRC, drc_reg);<br>-}<br>-<br>-static void sdram_enable(void)<br>-{<br>- int i;<br>-<br>- printk(BIOS_DEBUG, "Ram enable 1\n");<br>- delay();<br>- delay();<br>-<br>- /* NOP command */<br>- PRINTK_DEBUG(" NOP\n");<br>- do_ram_command(RAM_COMMAND_NOP, 0);<br>- delay();<br>- delay();<br>- delay();<br>-<br>- /* Pre-charge all banks (at least 200 us after NOP) */<br>- PRINTK_DEBUG(" Pre-charging all banks\n");<br>- do_ram_command(RAM_COMMAND_PRECHARGE, 0);<br>- delay();<br>- delay();<br>- delay();<br>-<br>- printk(BIOS_DEBUG, "Ram enable 4\n");<br>- do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE);<br>- delay();<br>- delay();<br>- delay();<br>-<br>- printk(BIOS_DEBUG, "Ram enable 5\n");<br>- do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_DLL_RESET);<br>-<br>- printk(BIOS_DEBUG, "Ram enable 6\n");<br>- do_ram_command(RAM_COMMAND_PRECHARGE, 0);<br>- delay();<br>- delay();<br>- delay();<br>-<br>- /* 8 CBR refreshes (Auto Refresh) */<br>- PRINTK_DEBUG(" 8 CBR refreshes\n");<br>- for (i = 0; i < 8; i++) {<br>- do_ram_command(RAM_COMMAND_CBR, 0);<br>- delay();<br>- delay();<br>- delay();<br>- }<br>-<br>- printk(BIOS_DEBUG, "Ram enable 8\n");<br>- do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_NORMAL);<br>-<br>- /* Set GME-M Mode Select bits back to NORMAL operation mode */<br>- PRINTK_DEBUG(" Normal operation mode\n");<br>- do_ram_command(RAM_COMMAND_NORMAL, 0);<br>- delay();<br>- delay();<br>- delay();<br>-<br>- printk(BIOS_DEBUG, "Ram enable 9\n");<br>- set_initialize_complete();<br>-<br>- delay();<br>- delay();<br>- delay();<br>- delay();<br>- delay();<br>-<br>- printk(BIOS_DEBUG, "After configuration:\n");<br>- /* dump_pci_devices(); */<br>-<br>- /*<br>- printk(BIOS_DEBUG, "\n\n***** RAM TEST *****\n");<br>- ram_check(0, 0xa0000);<br>- ram_check(0x100000, 0x40000000);<br>- */<br>-}<br>-<br>-/*-----------------------------------------------------------------------------<br>-DIMM-independent configuration functions:<br>------------------------------------------------------------------------------*/<br>-<br>-/**<br>- * Set only what I need until it works, then make it figure things out on boot<br>- * assumes only one DIMM is populated.<br>- */<br>-static void sdram_set_registers(void)<br>-{<br>- /*<br>- printk(BIOS_DEBUG, "Before configuration:\n");<br>- dump_pci_devices();<br>- */<br>-}<br>-<br>-static void spd_set_row_attributes(uint8_t dimm_mask)<br>-{<br>- int i;<br>- uint16_t row_attributes = 0;<br>-<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- u8 dimm = DIMM0 + i;<br>- struct dimm_size page_size;<br>- struct dimm_size sdram_width;<br>-<br>- if (!(dimm_mask & (1 << i))) {<br>- row_attributes |= 0x77 << (i << 3);<br>- continue; // This DIMM not usable<br>- }<br>-<br>- // Get the relevant parameters via SPD<br>- page_size = sdram_spd_get_page_size(dimm);<br>- sdram_width = sdram_spd_get_width(dimm);<br>-<br>- // Update the DRAM Row Attributes.<br>- // Page size is encoded as log2(page size in bits) - log2(2 KB) or 4 KB == 1, 8 KB == 3, 16KB == 3<br>- // NOTE: 2 KB = 16 Kb = 2^14<br>- row_attributes |= (page_size.side1 - 14) << (i << 3); // Side 1 of each DIMM is an EVEN row<br>-<br>- if (sdram_width.side2 > 0)<br>- row_attributes |= (page_size.side2 - 14) << ((i << 3) + 4); // Side 2 is ODD<br>- else<br>- row_attributes |= 7 << ((i << 3) + 4);<br>- /* go to the next DIMM */<br>- }<br>-<br>- PRINTK_DEBUG("DRA: %04x\n", row_attributes);<br>-<br>- /* Write the new row attributes register */<br>- pci_write_config16(NORTHBRIDGE_MMC, DRA, row_attributes);<br>-}<br>-<br>-static void spd_set_dram_controller_mode(uint8_t dimm_mask)<br>-{<br>- int i;<br>-<br>- // Initial settings<br>- u32 controller_mode = pci_read_config32(NORTHBRIDGE_MMC, DRC);<br>- u32 system_refresh_mode = (controller_mode >> 7) & 7;<br>-<br>- controller_mode |= (1 << 20); // ECC<br>- controller_mode |= (1 << 15); // RAS lockout<br>- controller_mode |= (1 << 12); // Address Tri-state enable (ADRTRIEN), FIXME: how is this detected?????<br>- controller_mode |= (2 << 10); // FIXME: Undocumented, really needed?????<br>-<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- u8 dimm = DIMM0 + i;<br>- uint32_t dimm_refresh_mode;<br>- int value;<br>- u8 tRCD, tRP;<br>-<br>- if (!(dimm_mask & (1 << i))) {<br>- continue; // This DIMM not usable<br>- }<br>-<br>- // Disable ECC mode if any one of the DIMMs does not support ECC<br>- value = spd_read_byte(dimm, SPD_DIMM_CONFIG_TYPE);<br>- die_on_spd_error(value);<br>- if (value != ERROR_SCHEME_ECC)<br>- controller_mode &= ~(3 << 20);<br>-<br>- value = spd_read_byte(dimm, SPD_REFRESH);<br>- die_on_spd_error(value);<br>- value &= 0x7f; // Mask off self-refresh bit<br>- if (value > MAX_SPD_REFRESH_RATE) {<br>- printk(BIOS_ERR, "unsupported refresh rate\n");<br>- continue;<br>- }<br>- // Get the appropriate i855 refresh mode for this DIMM<br>- dimm_refresh_mode = refresh_rate_map[value];<br>- if (dimm_refresh_mode > 7) {<br>- printk(BIOS_ERR, "unsupported refresh rate\n");<br>- continue;<br>- }<br>- // If this DIMM requires more frequent refresh than others,<br>- // update the system setting<br>- if (refresh_frequency[dimm_refresh_mode] ><br>- refresh_frequency[system_refresh_mode])<br>- system_refresh_mode = dimm_refresh_mode;<br>-<br>- /* FIXME: is this correct? */<br>- tRCD = spd_read_byte(dimm, SPD_tRCD);<br>- tRP = spd_read_byte(dimm, SPD_tRP);<br>- if (tRCD != tRP) {<br>- PRINTK_DEBUG(" Disabling RAS lockout due to tRCD (%d) != tRP (%d)\n", tRCD, tRP);<br>- controller_mode &= ~(1 << 15);<br>- }<br>-<br>- /* go to the next DIMM */<br>- }<br>-<br>- controller_mode &= ~(7 << 7);<br>- controller_mode |= (system_refresh_mode << 7);<br>- PRINTK_DEBUG("DRC: %08x\n", controller_mode);<br>-<br>- pci_write_config32(NORTHBRIDGE_MMC, DRC, controller_mode);<br>-}<br>-<br>-static void spd_set_dram_timing(uint8_t dimm_mask)<br>-{<br>- int i;<br>- u32 dram_timing;<br>-<br>- // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format<br>- // NOTE: i82822 supports only 2.0 and 2.5<br>- uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;<br>- uint8_t slowest_row_precharge = 0;<br>- uint8_t slowest_ras_cas_delay = 0;<br>- uint8_t slowest_active_to_precharge_delay = 0;<br>-<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- u8 dimm = DIMM0 + i;<br>- int value;<br>- uint32_t current_cas_latency;<br>- uint32_t dimm_compatible_cas_latencies;<br>- if (!(dimm_mask & (1 << i)))<br>- continue; // This DIMM not usable<br>-<br>- value = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);<br>- PRINTK_DEBUG("SPD_ACCEPTABLE_CAS_LATENCIES: %d\n", value);<br>- die_on_spd_error(value);<br>-<br>- dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM<br>- PRINTK_DEBUG("dimm_compatible_cas_latencies #1: %d\n", dimm_compatible_cas_latencies);<br>-<br>- current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM<br>- PRINTK_DEBUG("current_cas_latency: %d\n", current_cas_latency);<br>-<br>- // Can we support the highest CAS# latency?<br>- value = spd_read_byte(dimm, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);<br>- die_on_spd_error(value);<br>- PRINTK_DEBUG("SPD_MIN_CYCLE_TIME_AT_CAS_MAX: %d.%d\n", value >> 4, value & 0xf);<br>-<br>- // NOTE: At 133 MHz, 1 clock == 7.52 ns<br>- if (value > 0x75) {<br>- // Our bus is too fast for this CAS# latency<br>- // Remove it from the bitmask of those supported by the DIMM that are compatible<br>- dimm_compatible_cas_latencies &= ~current_cas_latency;<br>- PRINTK_DEBUG("dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies);<br>- }<br>- // Can we support the next-highest CAS# latency (max - 0.5)?<br>-<br>- current_cas_latency >>= 1;<br>- if (current_cas_latency != 0) {<br>- value = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);<br>- die_on_spd_error(value);<br>- PRINTK_DEBUG("SPD_SDRAM_CYCLE_TIME_2ND: %d.%d\n", value >> 4, value & 0xf);<br>- if (value > 0x75) {<br>- dimm_compatible_cas_latencies &= ~current_cas_latency;<br>- PRINTK_DEBUG("dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies);<br>- }<br>- }<br>- // Can we support the next-highest CAS# latency (max - 1.0)?<br>- current_cas_latency >>= 1;<br>- if (current_cas_latency != 0) {<br>- value = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);<br>- PRINTK_DEBUG("SPD_SDRAM_CYCLE_TIME_3RD: %d.%d\n", value >> 4, value & 0xf);<br>- die_on_spd_error(value);<br>- if (value > 0x75) {<br>- dimm_compatible_cas_latencies &= ~current_cas_latency;<br>- PRINTK_DEBUG("dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies);<br>- }<br>- }<br>- // Restrict the system to CAS# latencies compatible with this DIMM<br>- system_compatible_cas_latencies &= dimm_compatible_cas_latencies;<br>-<br>- value = spd_read_byte(dimm, SPD_MIN_ROW_PRECHARGE_TIME);<br>- die_on_spd_error(value);<br>- if (value > slowest_row_precharge)<br>- slowest_row_precharge = value;<br>-<br>- value = spd_read_byte(dimm, SPD_MIN_RAS_TO_CAS_DELAY);<br>- die_on_spd_error(value);<br>- if (value > slowest_ras_cas_delay)<br>- slowest_ras_cas_delay = value;<br>-<br>- value = spd_read_byte(dimm, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);<br>- die_on_spd_error(value);<br>- if (value > slowest_active_to_precharge_delay)<br>- slowest_active_to_precharge_delay = value;<br>-<br>- /* go to the next DIMM */<br>- }<br>- PRINTK_DEBUG("CAS latency: %d\n", system_compatible_cas_latencies);<br>-<br>- dram_timing = pci_read_config32(NORTHBRIDGE_MMC, DRT);<br>- dram_timing &= ~(DRT_CAS_MASK | DRT_TRP_MASK | DRT_RCD_MASK);<br>- PRINTK_DEBUG("DRT: %08x\n", dram_timing);<br>-<br>- if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {<br>- dram_timing |= DRT_CAS_2_0;<br>- } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {<br>- dram_timing |= DRT_CAS_2_5;<br>- } else<br>- die("No CAS# latencies compatible with all DIMMs!!\n");<br>-<br>- uint32_t current_cas_latency = dram_timing & DRT_CAS_MASK;<br>-<br>- /* tRP */<br>-<br>- PRINTK_DEBUG("slowest_row_precharge: %d.%d\n", slowest_row_precharge >> 2, slowest_row_precharge & 0x3);<br>- // i855 supports only 2, 3 or 4 clocks for tRP<br>- if (slowest_row_precharge > ((30 << 2)))<br>- die("unsupported DIMM tRP"); // > 30.0 ns: 5 or more clocks<br>- else if (slowest_row_precharge > ((22 << 2) | (2 << 0)))<br>- dram_timing |= DRT_TRP_4; // > 22.5 ns: 4 or more clocks<br>- else if (slowest_row_precharge > (15 << 2))<br>- dram_timing |= DRT_TRP_3; // > 15.0 ns: 3 clocks<br>- else<br>- dram_timing |= DRT_TRP_2; // <= 15.0 ns: 2 clocks<br>-<br>- /* tRCD */<br>-<br>- PRINTK_DEBUG("slowest_ras_cas_delay: %d.%d\n", slowest_ras_cas_delay >> 2, slowest_ras_cas_delay & 0x3);<br>- // i855 supports only 2, 3 or 4 clocks for tRCD<br>- if (slowest_ras_cas_delay > ((30 << 2)))<br>- die("unsupported DIMM tRCD"); // > 30.0 ns: 5 or more clocks<br>- else if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0)))<br>- dram_timing |= DRT_RCD_4; // > 22.5 ns: 4 or more clocks<br>- else if (slowest_ras_cas_delay > (15 << 2))<br>- dram_timing |= DRT_RCD_3; // > 15.0 ns: 3 clocks<br>- else<br>- dram_timing |= DRT_RCD_2; // <= 15.0 ns: 2 clocks<br>-<br>- /* tRAS, min */<br>-<br>- PRINTK_DEBUG("slowest_active_to_precharge_delay: %d\n", slowest_active_to_precharge_delay);<br>- // i855 supports only 5, 6, 7 or 8 clocks for tRAS<br>- // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns, 8 clocks ~= 60.1 ns<br>- if (slowest_active_to_precharge_delay > 60)<br>- die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks<br>- else if (slowest_active_to_precharge_delay > 52)<br>- dram_timing |= DRT_TRAS_MIN_8; // 46-52 ns: 7 clocks<br>- else if (slowest_active_to_precharge_delay > 45)<br>- dram_timing |= DRT_TRAS_MIN_7; // 46-52 ns: 7 clocks<br>- else if (slowest_active_to_precharge_delay > 37)<br>- dram_timing |= DRT_TRAS_MIN_6; // 38-45 ns: 6 clocks<br>- else<br>- dram_timing |= DRT_TRAS_MIN_5; // < 38 ns: 5 clocks<br>-<br>- /* FIXME: guess work starts here...<br>- *<br>- * Intel refers to DQ turn-around values for back to calculate the values,<br>- * but i have no idea what this means<br>- */<br>-<br>- /*<br>- * Back to Back Read-Write command spacing (DDR, different Rows/Bank)<br>- */<br>- /* Set to a 3 clock back to back read to write turn around.<br>- * 2 is a good delay if the CAS latency is 2.0 */<br>- dram_timing &= ~(3 << 28);<br>- if (current_cas_latency == DRT_CAS_2_0)<br>- dram_timing |= (2 << 28); // 2 clocks<br>- else<br>- dram_timing |= (1 << 28); // 3 clocks<br>-<br>- /*<br>- * Back to Back Read-Write command spacing (DDR, same or different Rows/Bank)<br>- */<br>- dram_timing &= ~(3 << 26);<br>- if (current_cas_latency == DRT_CAS_2_0)<br>- dram_timing |= (2 << 26); // 5 clocks<br>- else<br>- dram_timing |= (1 << 26); // 6 clocks<br>-<br>- /*<br>- * Back To Back Read-Read commands spacing (DDR, different Rows):<br>- */<br>- dram_timing &= ~(1 << 25);<br>- dram_timing |= (1 << 25); // 3 clocks<br>-<br>- PRINTK_DEBUG("DRT: %08x\n", dram_timing);<br>- pci_write_config32(NORTHBRIDGE_MMC, DRT, dram_timing);<br>-}<br>-<br>-static void spd_set_dram_size(uint8_t dimm_mask)<br>-{<br>- int i;<br>- int total_dram = 0;<br>- uint32_t drb_reg = 0;<br>-<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- u8 dimm = DIMM0 + i;<br>- struct dimm_size sz;<br>-<br>- if (!(dimm_mask & (1 << i))) {<br>- /* fill values even for not present DIMMs */<br>- drb_reg |= (total_dram << (i * 16));<br>- drb_reg |= (total_dram << ((i * 16) + 8));<br>-<br>- continue; // This DIMM not usable<br>- }<br>- sz = spd_get_dimm_size(dimm);<br>-<br>- total_dram += (1 << (sz.side1 - 28));<br>- drb_reg |= (total_dram << (i * 16));<br>-<br>- total_dram += (1 << (sz.side2 - 28));<br>- drb_reg |= (total_dram << ((i * 16) + 8));<br>- }<br>- PRINTK_DEBUG("DRB: %08x\n", drb_reg);<br>- pci_write_config32(NORTHBRIDGE_MMC, DRB, drb_reg);<br>-}<br>-<br>-<br>-static void spd_set_dram_pwr_management(void)<br>-{<br>- uint32_t pwrmg_reg;<br>-<br>- pwrmg_reg = 0x10f10430;<br>- pci_write_config32(NORTHBRIDGE_MMC, PWRMG, pwrmg_reg);<br>-}<br>-<br>-static void spd_set_dram_throttle_control(void)<br>-{<br>- uint32_t dtc_reg = 0;<br>-<br>- /* DDR SDRAM Throttle Mode (TMODE):<br>- * 0011 = Both Rank and GMCH Thermal Sensor based throttling is enabled. When the external SO-<br>- * DIMM Thermal Sensor is Tripped DDR SDRAM Throttling begins based on the setting in RTT<br>- */<br>- dtc_reg |= (3 << 28);<br>-<br>- /* Read Counter Based Power Throttle Control (RCTC):<br>- * 0 = 85%<br>- */<br>- dtc_reg |= (0 << 24);<br>-<br>- /* Write Counter Based Power Throttle Control (WCTC):<br>- * 0 = 85%<br>- */<br>- dtc_reg |= (0 << 20);<br>-<br>- /* Read Thermal Based Power Throttle Control (RTTC):<br>- * 0xA = 20%<br>- */<br>- dtc_reg |= (0xA << 16);<br>-<br>- /* Write Thermal Based Power Throttle Control (WTTC):<br>- * 0xA = 20%<br>- */<br>- dtc_reg |= (0xA << 12);<br>-<br>- /* Counter Based Throttle Lock (CTLOCK): */<br>- dtc_reg |= (0 << 11);<br>-<br>- /* Thermal Throttle Lock (TTLOCK): */<br>- dtc_reg |= (0 << 10);<br>-<br>- /* Thermal Power Throttle Control fields Enable: */<br>- dtc_reg |= (1 << 9);<br>-<br>- /* High Priority Stream Throttling Enable: */<br>- dtc_reg |= (0 << 8);<br>-<br>- /* Global DDR SDRAM Sampling Window (GDSW): */<br>- dtc_reg |= 0xff;<br>- PRINTK_DEBUG("DTC: %08x\n", dtc_reg);<br>- pci_write_config32(NORTHBRIDGE_MMC, DTC, dtc_reg);<br>-}<br>-<br>-static void spd_update(u8 reg, u32 new_value)<br>-{<br>-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>- u32 value1 = pci_read_config32(NORTHBRIDGE_MMC, reg);<br>-#endif<br>- pci_write_config32(NORTHBRIDGE_MMC, reg, new_value);<br>-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>- u32 value2 = pci_read_config32(NORTHBRIDGE_MMC, reg);<br>- PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2);<br>-#endif<br>-}<br>-<br>-/* if RAM still doesn't work do this function */<br>-static void spd_set_undocumented_registers(void)<br>-{<br>- spd_update(0x74, 0x00000001);<br>- spd_update(0x78, 0x001fe974);<br>- spd_update(0x80, 0x00af0039);<br>- spd_update(0x84, 0x0000033c);<br>- spd_update(0x88, 0x00000010);<br>-<br>- spd_update(0xc0, 0x00000003);<br>-}<br>-<br>-static void northbridge_set_registers(void)<br>-{<br>- u16 value;<br>- int video_memory = 0;<br>-<br>- printk(BIOS_DEBUG, "Setting initial Northbridge registers....\n");<br>-<br>- /* Set the value for Fixed DRAM Hole Control Register */<br>- pci_write_config8(NORTHBRIDGE, FDHC, 0x00);<br>-<br>- /* Set the value for Programmable Attribute Map Registers<br>- * Ideally, this should be R/W for as many ranges as possible.<br>- */<br>- pci_write_config8(NORTHBRIDGE, PAM0, 0x30);<br>- pci_write_config8(NORTHBRIDGE, PAM1, 0x33);<br>- pci_write_config8(NORTHBRIDGE, PAM2, 0x33);<br>- pci_write_config8(NORTHBRIDGE, PAM3, 0x33);<br>- pci_write_config8(NORTHBRIDGE, PAM4, 0x33);<br>- pci_write_config8(NORTHBRIDGE, PAM5, 0x33);<br>- pci_write_config8(NORTHBRIDGE, PAM6, 0x33);<br>-<br>- /* Set the value for System Management RAM Control Register */<br>- pci_write_config8(NORTHBRIDGE, SMRAM, 0x02);<br>-<br>- /* Set the value for GMCH Control Register #1 */<br>- switch (CONFIG_VIDEO_MB) {<br>- case 1: /* 1M of memory */<br>- video_memory = 0x1;<br>- break;<br>- case 4: /* 4M of memory */<br>- video_memory = 0x2;<br>- break;<br>- case 8: /* 8M of memory */<br>- video_memory = 0x3;<br>- break;<br>- case 16: /* 16M of memory */<br>- video_memory = 0x4;<br>- break;<br>- case 32: /* 32M of memory */<br>- video_memory = 0x5;<br>- break;<br>- default: /* No memory */<br>- pci_write_config16(NORTHBRIDGE, GMC, pci_read_config16(NORTHBRIDGE, GMC) | 1);<br>- video_memory = 0x0;<br>- }<br>-<br>- value = pci_read_config16(NORTHBRIDGE, GGC);<br>- value |= video_memory << 4;<br>- if (video_memory == 0) {<br>- value &= ~(1 < 1);<br>- } else<br>- value |= (1 < 1);<br>- pci_write_config16(NORTHBRIDGE, GGC, value);<br>-<br>- /* AGPCMD: disable AGP, Data-Rate: 1x */<br>- pci_write_config32(NORTHBRIDGE, AGPCMD, 0x00000001);<br>-<br>- pci_write_config8(NORTHBRIDGE, AMTT, 0x20);<br>- pci_write_config8(NORTHBRIDGE, LPTT, 0x10);<br>-<br>- printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n");<br>-}<br>-<br>-static void sdram_set_spd_registers(void)<br>-{<br>- uint8_t dimm_mask;<br>-<br>- PRINTK_DEBUG("Reading SPD data...\n");<br>-<br>- dimm_mask = spd_get_supported_dimms();<br>-<br>- if (dimm_mask == 0) {<br>- printk(BIOS_DEBUG, "No usable memory for this controller\n");<br>- } else {<br>- PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);<br>-<br>- spd_set_row_attributes(dimm_mask);<br>- spd_set_dram_controller_mode(dimm_mask);<br>- spd_set_dram_timing(dimm_mask);<br>- spd_set_dram_size(dimm_mask);<br>- spd_set_dram_pwr_management();<br>- spd_set_dram_throttle_control();<br>- spd_set_undocumented_registers();<br>- }<br>-<br>- /* Setup Initial Northbridge Registers */<br>- northbridge_set_registers();<br>-}<br>diff --git a/src/northbridge/intel/i855/raminit.h b/src/northbridge/intel/i855/raminit.h<br>deleted file mode 100644<br>index 31f57a1..0000000<br>--- a/src/northbridge/intel/i855/raminit.h<br>+++ /dev/null<br>@@ -1,29 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2006 Jon Dufresne <jon.dufresne@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef NORTHBRIDGE_INTEL_I855_RAMINIT_H<br>-#define NORTHBRIDGE_INTEL_I855_RAMINIT_H<br>-<br>-/* i855 Northbridge PCI devices */<br>-#define NORTHBRIDGE PCI_DEV(0, 0, 0)<br>-#define NORTHBRIDGE_MMC PCI_DEV(0, 0, 1)<br>-<br>-/* The i855 supports max. 2 dual-sided SO-DIMMs. */<br>-#define DIMM_SOCKETS 2<br>-<br>-void sdram_initialize(void);<br>-<br>-#endif /* NORTHBRIDGE_INTEL_I855_RAMINIT_H */<br>diff --git a/src/northbridge/intel/i855/reset_test.c b/src/northbridge/intel/i855/reset_test.c<br>deleted file mode 100644<br>index 9ca7854..0000000<br>--- a/src/northbridge/intel/i855/reset_test.c<br>+++ /dev/null<br>@@ -1,35 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2006 Jon Dufresne <jon.dufresne@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#define MCH_DRC 0x70<br>-#define DRC_DONE (1 << 29)<br>-<br>- /* If I have already booted once skip a bunch of initialization */<br>- /* To see if I have already booted I check to see if memory<br>- * has been enabled.<br>- */<br>-static int bios_reset_detected(void)<br>-{<br>- uint32_t dword;<br>-<br>- dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);<br>-<br>- if ( (dword & DRC_DONE) != 0 ) {<br>- return 1;<br>- }<br>-<br>- return 0;<br>-}<br></pre><p>To view, visit <a href="https://review.coreboot.org/22029">change 22029</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22029"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic9ba0ba7e2b6e602a5749cc531dd705c49e3f08d </div>
<div style="display:none"> Gerrit-Change-Number: 22029 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>