<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22027">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Intel sch board & chip: Remove - using LATE_CBMEM_INIT<br><br>All boards and chips that are still using LATE_CBMEM_INIT are being<br>removed as previously discussed.<br><br>If these boards and chips are updated to not use LATE_CBMEM_INIT, they<br>can be restored to the active codebase from the 4.8 branch.<br><br>chips:<br>soc/intel/sch<br><br>Mainboards:<br>mainboard/iwave/iWRainbowG6<br><br>Change-Id: Ida0570988a23fd0d13c6fcbe54f94ab0668c9eae<br>Signed-off-by: Martin Roth <gaumless@gmail.com><br>---<br>M src/cpu/x86/smm/smmrelocate.S<br>D src/mainboard/iwave/Kconfig<br>D src/mainboard/iwave/Kconfig.name<br>D src/mainboard/iwave/iWRainbowG6/Kconfig<br>D src/mainboard/iwave/iWRainbowG6/Kconfig.name<br>D src/mainboard/iwave/iWRainbowG6/Makefile.inc<br>D src/mainboard/iwave/iWRainbowG6/acpi/cpu.asl<br>D src/mainboard/iwave/iWRainbowG6/acpi/ec.asl<br>D src/mainboard/iwave/iWRainbowG6/acpi/northbridge_pci_irqs.asl<br>D src/mainboard/iwave/iWRainbowG6/acpi/platform.asl<br>D src/mainboard/iwave/iWRainbowG6/acpi/sleepstates.asl<br>D src/mainboard/iwave/iWRainbowG6/acpi/southbridge_pci_irqs.asl<br>D src/mainboard/iwave/iWRainbowG6/acpi/superio.asl<br>D src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl<br>D src/mainboard/iwave/iWRainbowG6/acpi_tables.c<br>D src/mainboard/iwave/iWRainbowG6/board_info.txt<br>D src/mainboard/iwave/iWRainbowG6/cmos.layout<br>D src/mainboard/iwave/iWRainbowG6/cstates.c<br>D src/mainboard/iwave/iWRainbowG6/devicetree.cb<br>D src/mainboard/iwave/iWRainbowG6/dsdt.asl<br>D src/mainboard/iwave/iWRainbowG6/fadt.c<br>D src/mainboard/iwave/iWRainbowG6/hda_verb.c<br>D src/mainboard/iwave/iWRainbowG6/irq_tables.c<br>D src/mainboard/iwave/iWRainbowG6/mptable.c<br>D src/mainboard/iwave/iWRainbowG6/romstage.c<br>D src/soc/intel/sch/Kconfig<br>D src/soc/intel/sch/Makefile.inc<br>D src/soc/intel/sch/acpi.c<br>D src/soc/intel/sch/acpi/ac97.asl<br>D src/soc/intel/sch/acpi/audio.asl<br>D src/soc/intel/sch/acpi/globalnvs.asl<br>D src/soc/intel/sch/acpi/hostbridge.asl<br>D src/soc/intel/sch/acpi/igd.asl<br>D src/soc/intel/sch/acpi/irqlinks.asl<br>D src/soc/intel/sch/acpi/lpc.asl<br>D src/soc/intel/sch/acpi/pata.asl<br>D src/soc/intel/sch/acpi/pci.asl<br>D src/soc/intel/sch/acpi/pcie.asl<br>D src/soc/intel/sch/acpi/peg.asl<br>D src/soc/intel/sch/acpi/sch.asl<br>D src/soc/intel/sch/acpi/sleepstates.asl<br>D src/soc/intel/sch/acpi/smbus.asl<br>D src/soc/intel/sch/acpi/usb.asl<br>D src/soc/intel/sch/audio.c<br>D src/soc/intel/sch/bootblock.c<br>D src/soc/intel/sch/chip.h<br>D src/soc/intel/sch/early_init.c<br>D src/soc/intel/sch/early_smbus.c<br>D src/soc/intel/sch/gma.c<br>D src/soc/intel/sch/ide.c<br>D src/soc/intel/sch/lpc.c<br>D src/soc/intel/sch/mmc.c<br>D src/soc/intel/sch/northbridge.c<br>D src/soc/intel/sch/nvs.h<br>D src/soc/intel/sch/pcie.c<br>D src/soc/intel/sch/port_access.c<br>D src/soc/intel/sch/raminit.c<br>D src/soc/intel/sch/raminit.h<br>D src/soc/intel/sch/reset.c<br>D src/soc/intel/sch/sch.h<br>D src/soc/intel/sch/smbus.c<br>D src/soc/intel/sch/smbus.h<br>D src/soc/intel/sch/smi.c<br>D src/soc/intel/sch/smihandler.c<br>D src/soc/intel/sch/south.c<br>D src/soc/intel/sch/usb.c<br>D src/soc/intel/sch/usb_client.c<br>D src/soc/intel/sch/usb_ehci.c<br>68 files changed, 0 insertions(+), 7,640 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/22027/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S<br>index 230c78d..ed556db 100644<br>--- a/src/cpu/x86/smm/smmrelocate.S<br>+++ b/src/cpu/x86/smm/smmrelocate.S<br>@@ -25,8 +25,6 @@<br> #include "../../../southbridge/intel/i82801gx/i82801gx.h"<br> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)<br> #include "../../../southbridge/intel/i82801dx/i82801dx.h"<br>-#elif IS_ENABLED(CONFIG_SOC_INTEL_SCH)<br>-#include "../../../soc/intel/sch/sch.h"<br> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX)<br> #include "../../../southbridge/intel/i82801ix/i82801ix.h"<br> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX)<br>diff --git a/src/mainboard/iwave/Kconfig b/src/mainboard/iwave/Kconfig<br>deleted file mode 100644<br>index 2af87f9..0000000<br>--- a/src/mainboard/iwave/Kconfig<br>+++ /dev/null<br>@@ -1,17 +0,0 @@<br>-if VENDOR_IWAVE<br>-<br>-choice<br>- prompt "Mainboard model"<br>- depends on VENDOR_IWAVE<br>-<br>-source "src/mainboard/iwave/*/Kconfig.name"<br>-<br>-endchoice<br>-<br>-source "src/mainboard/iwave/*/Kconfig"<br>-<br>-config MAINBOARD_VENDOR<br>- string<br>- default "iWave"<br>-<br>-endif # VENDOR_IWAVE<br>diff --git a/src/mainboard/iwave/Kconfig.name b/src/mainboard/iwave/Kconfig.name<br>deleted file mode 100644<br>index 2babae3..0000000<br>--- a/src/mainboard/iwave/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config VENDOR_IWAVE<br>- bool "iWave"<br>diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig<br>deleted file mode 100644<br>index c441063d..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/Kconfig<br>+++ /dev/null<br>@@ -1,33 +0,0 @@<br>-if BOARD_IWAVE_RAINBOW_G6<br>-<br>-# TODO: move options to chipset components as appropriate<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_INTEL_SOCKET_441<br>- select SOC_INTEL_SCH<br>- select HAVE_PIRQ_TABLE<br>-# select HAVE_MP_TABLE<br>- select UDELAY_LAPIC<br>- select HAVE_ACPI_TABLES<br>- select BOARD_ROMSIZE_KB_1024<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default iwave/iWRainbowG6<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "iWRainbowG6"<br>-<br>-config MMCONF_BASE_ADDRESS<br>- hex<br>- default 0xe0000000<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 10<br>-<br>-# This mainboard might have a higher clocked UART or might not be able to run<br>-# serial output at 115200 baud<br>-<br>-endif<br>diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig.name b/src/mainboard/iwave/iWRainbowG6/Kconfig.name<br>deleted file mode 100644<br>index d2be662..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_IWAVE_RAINBOW_G6<br>- bool "iWRainbowG6"<br>diff --git a/src/mainboard/iwave/iWRainbowG6/Makefile.inc b/src/mainboard/iwave/iWRainbowG6/Makefile.inc<br>deleted file mode 100644<br>index f9621db..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/Makefile.inc<br>+++ /dev/null<br>@@ -1 +0,0 @@<br>-ramstage-y += cstates.c<br>diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/cpu.asl b/src/mainboard/iwave/iWRainbowG6/acpi/cpu.asl<br>deleted file mode 100644<br>index 7535b51..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/acpi/cpu.asl<br>+++ /dev/null<br>@@ -1,45 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* Intel Core (2) Duo CPU node support<br>- *<br>- * Note: The ACPI P_BLK on the ICH7 (and probably others) lives at<br>- * PMBASE + 0x10, and it's 0x06 bytes long. On ICH8 it's 8 bytes.<br>- *<br>- * The second CPU core does not need its own P_BLK.<br>- */<br>-<br>-Scope(\_PR)<br>-{<br>- Processor(<br>- CPU1, // name of cpu/core 0<br>- 1, // numeric id of cpu/core<br>- 0x510, // ACPI P_BLK base address<br>- 6 // ACPI P_BLK size<br>- )<br>- {<br>- // TODO: _PDT<br>- }<br>-<br>- Processor(<br>- CPU2, // name of cpu/core 1<br>- 2, // numeric id of cpu/core 1<br>- 0, // ACPI P_BLK base address<br>- 0) // ACPI P_BLK size<br>- {<br>- // TODO: _PDT<br>- }<br>-} // End _PR<br>diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl b/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl<br>deleted file mode 100644<br>index 63abc00..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl<br>+++ /dev/null<br>@@ -1,52 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-Device(EC0)<br>-{<br>- Name (_HID, EISAID("PNP0C09"))<br>- Name (_UID, 1)<br>-<br>- // _REG method requires that an operation region be defined.<br>- OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)<br>- Field (ERAM, ByteAcc, Lock, Preserve)<br>- {<br>- }<br>-<br>- Method (_CRS, 0, Serialized)<br>- {<br>- Name (ECMD, ResourceTemplate()<br>- {<br>- IO (Decode16, 0x62, 0x62, 0, 1)<br>- IO (Decode16, 0x66, 0x66, 0, 1)<br>- })<br>-<br>- Return (ECMD)<br>- }<br>-<br>- Method (_REG, 2)<br>- {<br>- // This method is needed by Windows XP/2000<br>- // for EC initialization before a driver<br>- // is loaded<br>- }<br>-<br>- Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI<br>-<br>- // TODO EC Query methods<br>-<br>- // TODO Scope _SB devices for AC power, LID, Power button<br>-<br>-}<br>diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/northbridge_pci_irqs.asl b/src/mainboard/iwave/iWRainbowG6/acpi/northbridge_pci_irqs.asl<br>deleted file mode 100644<br>index efb94c6..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/acpi/northbridge_pci_irqs.asl<br>+++ /dev/null<br>@@ -1,81 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* This is board specific information: IRQ routing for the<br>- * i945<br>- */<br>-<br>-<br>-// PCI Interrupt Routing<br>-Method(_PRT)<br>-{<br>- If (PICM) {<br>- Return (Package() {<br>- // PCIe Graphics 0:1.0<br>- Package() { 0x0001ffff, 0, 0, 16 },<br>- Package() { 0x0001ffff, 1, 0, 17 },<br>- Package() { 0x0001ffff, 2, 0, 18 },<br>- Package() { 0x0001ffff, 3, 0, 19 },<br>- // Onboard graphics (IGD) 0:2.0<br>- Package() { 0x0002ffff, 0, 0, 16 },<br>- // High Definition Audio 0:1b.0<br>- Package() { 0x001bffff, 0, 0, 16 },<br>- // PCIe Root Ports 0:1c.x<br>- Package() { 0x001cffff, 0, 0, 16 },<br>- Package() { 0x001cffff, 1, 0, 17 },<br>- Package() { 0x001cffff, 2, 0, 18 },<br>- Package() { 0x001cffff, 3, 0, 19 },<br>- // USB and EHCI 0:1d.x<br>- Package() { 0x001dffff, 0, 0, 23 },<br>- Package() { 0x001dffff, 1, 0, 19 },<br>- Package() { 0x001dffff, 2, 0, 18 },<br>- Package() { 0x001dffff, 3, 0, 16 },<br>- // AC97/IDE 0:1e.2, 0:1e.3<br>- Package() { 0x001effff, 0, 0, 17 },<br>- Package() { 0x001effff, 1, 0, 20 },<br>- // LPC device 0:1f.0<br>- Package() { 0x001fffff, 0, 0, 18 },<br>- Package() { 0x001fffff, 1, 0, 19},<br>- })<br>- } Else {<br>- Return (Package() {<br>- // PCIe Graphics 0:1.0<br>- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },<br>- // Onboard graphics (IGD) 0:2.0<br>- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // High Definition Audio 0:1b.0<br>- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // PCIe Root Ports 0:1c.x<br>- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },<br>- // USB and EHCI 0:1d.x<br>- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },<br>- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },<br>- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // AC97/IDE 0:1e.2, 0:1e.3<br>- Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },<br>- // LPC device 0:1f.0<br>- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },<br>- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },<br>- })<br>- }<br>-}<br>diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/platform.asl b/src/mainboard/iwave/iWRainbowG6/acpi/platform.asl<br>deleted file mode 100644<br>index 8e6d794..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/acpi/platform.asl<br>+++ /dev/null<br>@@ -1,87 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* The APM port can be used for generating software SMIs */<br>-<br>-OperationRegion (APMP, SystemIO, 0xb2, 2)<br>-Field (APMP, ByteAcc, NoLock, Preserve)<br>-{<br>- APMC, 8, // APM command<br>- APMS, 8 // APM status<br>-}<br>-<br>-/* Port 80 POST */<br>-<br>-OperationRegion (POST, SystemIO, 0x80, 1)<br>-Field (POST, ByteAcc, Lock, Preserve)<br>-{<br>- DBG0, 8<br>-}<br>-<br>-/* SMI I/O Trap */<br>-Method(TRAP, 1, Serialized)<br>-{<br>- Store (Arg0, SMIF) // SMI Function<br>- //Store (0, TRP0) // Generate trap<br>- Return (SMIF) // Return value of SMI handler<br>-}<br>-<br>-/* The _PIC method is called by the OS to choose between interrupt<br>- * routing via the i8259 interrupt controller or the APIC.<br>- *<br>- * _PIC is called with a parameter of 0 for i8259 configuration and<br>- * with a parameter of 1 for Local Apic/IOAPIC configuration.<br>- */<br>-<br>-Method(_PIC, 1)<br>-{<br>- // Remember the OS' IRQ routing choice.<br>- Store(Arg0, PICM)<br>-}<br>-<br>-/* The _PTS method (Prepare To Sleep) is called before the OS is<br>- * entering a sleep state. The sleep state number is passed in Arg0<br>- */<br>-<br>-Method(_PTS,1)<br>-{<br>- // Call a trap so SMI can prepare for Sleep as well.<br>- // TRAP(0x55)<br>-}<br>-<br>-/* The _WAK method is called on system wakeup */<br>-<br>-Method(_WAK,1)<br>-{<br>- // CPU specific part<br>-<br>- // Notify PCI Express slots in case a card<br>- // was inserted while a sleep state was active.<br>-<br>- // Are we going to S3?<br>- If (LEqual(Arg0, 3)) {<br>- // ..<br>- }<br>-<br>- // Are we going to S4?<br>- If (LEqual(Arg0, 4)) {<br>- // ..<br>- }<br>-<br>- // TODO: Windows XP SP2 P-State restore<br>-<br>- Return(Package(){0,0})<br>-}<br>diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/sleepstates.asl b/src/mainboard/iwave/iWRainbowG6/acpi/sleepstates.asl<br>deleted file mode 100644<br>index c05835a..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/acpi/sleepstates.asl<br>+++ /dev/null<br>@@ -1,21 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-Name(\_S0, Package(4){0x0,0x0,0,0})<br>-Name(\_S1, Package(4){0x1,0x0,0,0})<br>-Name(\_S3, Package(4){0x5,0x0,0,0})<br>-Name(\_S4, Package(4){0x6,0x0,0,0})<br>-Name(\_S5, Package(4){0x7,0x0,0,0})<br>diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/southbridge_pci_irqs.asl b/src/mainboard/iwave/iWRainbowG6/acpi/southbridge_pci_irqs.asl<br>deleted file mode 100644<br>index 67915f2..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/acpi/southbridge_pci_irqs.asl<br>+++ /dev/null<br>@@ -1,98 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* This is board specific information: IRQ routing for the<br>- * 0:1e.0 PCI bridge of the ICH7<br>- */<br>-<br>-If (PICM) {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, 0, 16},<br>-<br>- Package() { 0x0001ffff, 0, 0, 20},<br>- Package() { 0x0001ffff, 1, 0, 21},<br>- Package() { 0x0001ffff, 2, 0, 22},<br>- Package() { 0x0001ffff, 3, 0, 23},<br>-<br>- Package() { 0x0002ffff, 0, 0, 21},<br>- Package() { 0x0002ffff, 1, 0, 22},<br>- Package() { 0x0002ffff, 2, 0, 23},<br>- Package() { 0x0002ffff, 3, 0, 20},<br>-<br>- Package() { 0x0003ffff, 0, 0, 22},<br>- Package() { 0x0003ffff, 1, 0, 23},<br>- Package() { 0x0003ffff, 2, 0, 20},<br>- Package() { 0x0003ffff, 3, 0, 21},<br>-<br>- Package() { 0x0004ffff, 0, 0, 23},<br>- Package() { 0x0004ffff, 1, 0, 20},<br>- Package() { 0x0004ffff, 2, 0, 21},<br>- Package() { 0x0004ffff, 3, 0, 22},<br>-<br>- Package() { 0x0005ffff, 0, 0, 19},<br>- Package() { 0x0005ffff, 1, 0, 18},<br>- Package() { 0x0005ffff, 2, 0, 17},<br>- Package() { 0x0005ffff, 3, 0, 16},<br>-<br>- Package() { 0x0006ffff, 0, 0, 18},<br>- Package() { 0x0006ffff, 1, 0, 17},<br>- Package() { 0x0006ffff, 2, 0, 16},<br>- Package() { 0x0006ffff, 3, 0, 19},<br>-<br>- Package() { 0x0009ffff, 0, 0, 21},<br>- Package() { 0x0009ffff, 1, 0, 22},<br>- Package() { 0x0009ffff, 2, 0, 23},<br>- Package() { 0x0009ffff, 3, 0, 20},<br>- })<br>-} Else {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},<br>-<br>- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},<br>- Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},<br>- Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},<br>- Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},<br>-<br>- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},<br>- Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},<br>- Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},<br>- Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},<br>-<br>- Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},<br>- Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},<br>- Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},<br>- Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},<br>-<br>- Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},<br>- Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},<br>- Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},<br>- Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},<br>-<br>- Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},<br>- Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},<br>- Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},<br>- Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},<br>-<br>- Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},<br>- Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},<br>- Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},<br>- Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},<br>-<br>- Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},<br>- Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},<br>- Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},<br>- Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},<br>- })<br>-}<br>diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/superio.asl b/src/mainboard/iwave/iWRainbowG6/acpi/superio.asl<br>deleted file mode 100644<br>index 38343a5..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/acpi/superio.asl<br>+++ /dev/null<br>@@ -1,42 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-<br>-Device (SIO1)<br>-{<br>- Name (_HID, EISAID("PNP0A05"))<br>- Name (_UID, 1)<br>-<br>- Device (UAR1)<br>- {<br>- Name(_HID, EISAID("PNP0501"))<br>- Name(_UID, 1)<br>-<br>- // Some methods need an implementation here:<br>- // missing: _STA, _DIS, _CRS, _PRS,<br>- // missing: _SRS, _PS0, _PS3<br>- }<br>-<br>- Device (UAR2)<br>- {<br>- Name(_HID, EISAID("PNP0501"))<br>- Name(_UID, 2)<br>-<br>- // Some methods need an implementation here:<br>- // missing: _STA, _DIS, _CRS, _PRS,<br>- // missing: _SRS, _PS0, _PS3<br>- }<br>-}<br>diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl b/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl<br>deleted file mode 100644<br>index de8fcdd..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl<br>+++ /dev/null<br>@@ -1,90 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-// Thermal Zone<br>-<br>-Scope (\_TZ)<br>-{<br>- ThermalZone (THRM)<br>- {<br>-<br>- // FIXME these could/should be read from the<br>- // GNVS area, so they can be controlled by<br>- // coreboot<br>- Name(TC1V, 0x04)<br>- Name(TC2V, 0x03)<br>- Name(TSPV, 0x64)<br>-<br>- // At which temperature should the OS start<br>- // active cooling?<br>- Method (_AC0, 0, Serialized)<br>- {<br>- Return (0xf5c) // Value for Rocky<br>- }<br>-<br>- // Method (_AC1, 0, Serialized)<br>- // {<br>- // Return (0xf5c)<br>- // }<br>-<br>- // Critical shutdown temperature<br>- Method (_CRT, 0, Serialized)<br>- {<br>- Return (Add (0x0aac, 0x50)) // FIXME<br>- }<br>-<br>- // CPU throttling start temperature<br>- Method (_PSV, 0, Serialized)<br>- {<br>- Return (0xaaf) // FIXME<br>- }<br>-<br>- // Get DTS Temperature<br>- Method (_TMP, 0, Serialized)<br>- {<br>- Return (0xaac) // FIXME<br>- }<br>-<br>- // Processors used for active cooling<br>- Method (_PSL, 0, Serialized)<br>- {<br>- If (MPEN) {<br>- Return (Package() {\_PR.CP01, \_PR.CP02})<br>- }<br>- Return (Package() {\_PR.CP01})<br>- }<br>-<br>- // TC1 value for passive cooling<br>- Method (_TC1, 0, Serialized)<br>- {<br>- Return (TC1V)<br>- }<br>-<br>- // TC2 value for passive cooling<br>- Method (_TC2, 0, Serialized)<br>- {<br>- Return (TC2V)<br>- }<br>-<br>- // Sampling period for passive cooling<br>- Method (_TSP, 0, Serialized)<br>- {<br>- Return (TSPV)<br>- }<br>-<br>-<br>- }<br>-}<br>diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c<br>deleted file mode 100644<br>index 45b9da2..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c<br>+++ /dev/null<br>@@ -1,58 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <types.h><br>-#include <string.h><br>-#include <console/console.h><br>-#include <arch/acpi.h><br>-#include <arch/ioapic.h><br>-#include <arch/acpigen.h><br>-#include <arch/smp/mpspec.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-<br>-#include "soc/intel/sch/nvs.h"<br>-<br>-void acpi_create_gnvs(global_nvs_t * gnvs)<br>-{<br>- memset((void *)gnvs, 0, sizeof(*gnvs));<br>- gnvs->apic = 1;<br>- gnvs->mpen = 1; /* Enable Multi Processing. */<br>-<br>- /* Enable both COM ports. */<br>- gnvs->cmap = 0x01;<br>- gnvs->cmbp = 0x01;<br>-}<br>-<br>-unsigned long acpi_fill_madt(unsigned long current)<br>-{<br>- /* Local APICs */<br>- current = acpi_create_madt_lapics(current);<br>-<br>- /* IOAPIC */<br>- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,<br>- 2, IO_APIC_ADDR, 0);<br>-<br>- /* INT_SRC_OVR */<br>- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)<br>- current, 0, 0, 2, 0);<br>- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)<br>- current, 0, 9, 9,<br>- MP_IRQ_TRIGGER_LEVEL |<br>- MP_IRQ_POLARITY_HIGH);<br>-<br>- return current;<br>-}<br>diff --git a/src/mainboard/iwave/iWRainbowG6/board_info.txt b/src/mainboard/iwave/iWRainbowG6/board_info.txt<br>deleted file mode 100644<br>index ad25a93..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/board_info.txt<br>+++ /dev/null<br>@@ -1,3 +0,0 @@<br>-Board name: iW-RainboW-G6<br>-Category: half<br>-Board URL: http://www.iwavesystems.com/iW-RainbowG6.htm<br>diff --git a/src/mainboard/iwave/iWRainbowG6/cmos.layout b/src/mainboard/iwave/iWRainbowG6/cmos.layout<br>deleted file mode 100644<br>index 1081a15..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/cmos.layout<br>+++ /dev/null<br>@@ -1,111 +0,0 @@<br>-#<br>-# This file is part of the coreboot project.<br>-#<br>-# Copyright (C) 2007-2009 coresystems GmbH<br>-#<br>-# This program is free software; you can redistribute it and/or<br>-# modify it under the terms of the GNU General Public License as<br>-# published by the Free Software Foundation; version 2 of<br>-# the License.<br>-#<br>-# This program is distributed in the hope that it will be useful,<br>-# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-# GNU General Public License for more details.<br>-#<br>-<br>-# -----------------------------------------------------------------<br>-entries<br>-<br>-# -----------------------------------------------------------------<br>-# Status Register A<br>-# -----------------------------------------------------------------<br>-# Status Register B<br>-# -----------------------------------------------------------------<br>-# Status Register C<br>-#96 4 r 0 status_c_rsvd<br>-#100 1 r 0 uf_flag<br>-#101 1 r 0 af_flag<br>-#102 1 r 0 pf_flag<br>-#103 1 r 0 irqf_flag<br>-# -----------------------------------------------------------------<br>-# Status Register D<br>-#104 7 r 0 status_d_rsvd<br>-#111 1 r 0 valid_cmos_ram<br>-# -----------------------------------------------------------------<br>-# Diagnostic Status Register<br>-#112 8 r 0 diag_rsvd1<br>-<br>-# -----------------------------------------------------------------<br>-0 120 r 0 reserved_memory<br>-#120 264 r 0 unused<br>-<br>-# -----------------------------------------------------------------<br>-# RTC_BOOT_BYTE (coreboot hardcoded)<br>-384 1 e 4 boot_option<br>-388 4 h 0 reboot_counter<br>-#390 2 r 0 unused?<br>-<br>-# -----------------------------------------------------------------<br>-# coreboot config options: console<br>-#392 3 r 0 unused<br>-395 4 e 6 debug_level<br>-#399 1 r 0 unused<br>-<br>-# coreboot config options: cpu<br>-400 1 e 2 hyper_threading<br>-#401 7 r 0 unused<br>-<br>-# coreboot config options: southbridge<br>-408 1 e 1 nmi<br>-409 2 e 7 power_on_after_fail<br>-#411 5 r 0 unused<br>-<br>-# coreboot config options: bootloader<br>-416 512 s 0 boot_devices<br>-#928 40 r 0 unused<br>-<br>-968 1 e 2 ethernet1<br>-969 1 e 2 ethernet2<br>-970 1 e 2 ethernet3<br>-<br>-#971 13 r 0 unused<br>-<br>-# coreboot config options: check sums<br>-984 16 h 0 check_sum<br>-#1000 24 r 0 amd_reserved<br>-<br>-# RAM initialization internal data<br>-1024 8 r 0 C0WL0REOST<br>-1032 8 r 0 C1WL0REOST<br>-1040 8 r 0 RCVENMT<br>-1048 4 r 0 C0DRT1<br>-1052 4 r 0 C1DRT1<br>-<br>-# -----------------------------------------------------------------<br>-<br>-enumerations<br>-<br>-#ID value text<br>-1 0 Disable<br>-1 1 Enable<br>-2 0 Enable<br>-2 1 Disable<br>-4 0 Fallback<br>-4 1 Normal<br>-6 1 Emergency<br>-6 2 Alert<br>-6 3 Critical<br>-6 4 Error<br>-6 5 Warning<br>-6 6 Notice<br>-6 7 Info<br>-6 8 Debug<br>-6 9 Spew<br>-7 0 Disable<br>-7 1 Enable<br>-7 2 Keep<br>-# -----------------------------------------------------------------<br>-checksums<br>-<br>-checksum 392 983 984<br>diff --git a/src/mainboard/iwave/iWRainbowG6/cstates.c b/src/mainboard/iwave/iWRainbowG6/cstates.c<br>deleted file mode 100644<br>index 2d543ff..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/cstates.c<br>+++ /dev/null<br>@@ -1,7 +0,0 @@<br>-#include <device/device.h><br>-#include <arch/x86/include/arch/acpigen.h><br>-<br>-int get_cst_entries(acpi_cstate_t **entries)<br>-{<br>- return 0;<br>-}<br>diff --git a/src/mainboard/iwave/iWRainbowG6/devicetree.cb b/src/mainboard/iwave/iWRainbowG6/devicetree.cb<br>deleted file mode 100644<br>index b13d873..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/devicetree.cb<br>+++ /dev/null<br>@@ -1,40 +0,0 @@<br>-chip soc/intel/sch<br>- # IGD Displays<br>- register "gfx.ndid" = "3"<br>- register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"<br>-<br>- # PIRQ routing<br>- register "pirqa_routing" = "0xa"<br>- register "pirqb_routing" = "0xb"<br>- register "pirqc_routing" = "0x5"<br>- register "pirqd_routing" = "0xf"<br>- register "pirqe_routing" = "0x80"<br>- register "pirqf_routing" = "0x80"<br>- register "pirqg_routing" = "0x80"<br>- register "pirqh_routing" = "0x80"<br>-<br>- device cpu_cluster 0 on<br>- chip cpu/intel/socket_441<br>- device lapic 0 on end<br>- end<br>- end<br>-<br>- device domain 0 on<br>- device pci 00.0 on end # host bridge<br>- device pci 02.0 on end # Integrated Graphics and Video Device<br>-<br>- device pci 1a.0 on end # 26 0 USB Client<br>- device pci 1b.0 on end # 27 0 HD Audio Controller<br>- device pci 1c.0 on end # 28 0 PCI Express Port 1<br>- device pci 1c.1 on end # 28 1 PCI Express Port 2<br>- device pci 1d.0 on end # USB Classic UHCI Controller 1<br>- device pci 1d.1 on end # USB Classic UHCI Controller 2<br>- device pci 1d.2 on end # USB Classic UHCI Controller 3<br>- device pci 1d.7 on end # USB2 EHCI Controller<br>- device pci 1e.0 on end # SDIO/MMC Port 0<br>- device pci 1e.1 on end # SDIO/MMC Port 1<br>- device pci 1e.2 on end # SDIO/MMC Port 2<br>- device pci 1f.0 on end # LPC bridge<br>- device pci 1f.1 on end # PATA Controller<br>- end<br>-end<br>diff --git a/src/mainboard/iwave/iWRainbowG6/dsdt.asl b/src/mainboard/iwave/iWRainbowG6/dsdt.asl<br>deleted file mode 100644<br>index 0dc46f2..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/dsdt.asl<br>+++ /dev/null<br>@@ -1,45 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-DefinitionBlock(<br>- "dsdt.aml",<br>- "DSDT",<br>- 0x02, // DSDT revision: ACPI v2.0<br>- "COREv4", // OEM id<br>- "COREBOOT", // OEM table id<br>- 0x20090419 // OEM revision<br>-)<br>-{<br>- // Some generic macros<br>- #include "acpi/platform.asl"<br>-<br>- // global NVS and variables<br>- #include <soc/intel/sch/acpi/globalnvs.asl><br>-<br>- // General Purpose Events<br>- //#include "acpi/gpe.asl"<br>-<br>- //#include "acpi/thermal.asl"<br>-<br>- Scope (\_SB) {<br>- Device (PCI0)<br>- {<br>- #include <soc/intel/sch/acpi/sch.asl><br>- }<br>- }<br>-<br>- /* Chipset specific sleep states */<br>- #include <soc/intel/sch/acpi/sleepstates.asl><br>-}<br>diff --git a/src/mainboard/iwave/iWRainbowG6/fadt.c b/src/mainboard/iwave/iWRainbowG6/fadt.c<br>deleted file mode 100644<br>index 86aa606..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/fadt.c<br>+++ /dev/null<br>@@ -1,151 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <string.h><br>-#include <device/pci.h><br>-#include <arch/acpi.h><br>-#include <cpu/x86/smm.h><br>-<br>-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)<br>-{<br>- acpi_header_t *header = &(fadt->header);<br>- u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),<br>- 0x40) & 0xfffe;<br>-<br>- memset((void *)fadt, 0, sizeof(acpi_fadt_t));<br>- memcpy(header->signature, "FACP", 4);<br>- header->length = sizeof(acpi_fadt_t);<br>- header->revision = 3;<br>- memcpy(header->oem_id, OEM_ID, 6);<br>- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);<br>- memcpy(header->asl_compiler_id, ASLC, 4);<br>- header->asl_compiler_revision = 1;<br>-<br>- fadt->firmware_ctrl = (unsigned long)facs;<br>- fadt->dsdt = (unsigned long)dsdt;<br>- fadt->model = 1;<br>- fadt->preferred_pm_profile = PM_MOBILE;<br>-<br>- fadt->sci_int = 0x9;<br>- fadt->smi_cmd = APM_CNT;<br>- fadt->acpi_enable = APM_CNT_ACPI_ENABLE;<br>- fadt->acpi_disable = APM_CNT_ACPI_DISABLE;<br>- fadt->s4bios_req = 0x0;<br>- fadt->pstate_cnt = APM_CNT_PST_CONTROL;<br>-<br>- fadt->pm1a_evt_blk = pmbase;<br>- fadt->pm1b_evt_blk = 0x0;<br>- fadt->pm1a_cnt_blk = pmbase + 0x4;<br>- fadt->pm1b_cnt_blk = 0x0;<br>- fadt->pm2_cnt_blk = pmbase + 0x20;<br>- fadt->pm_tmr_blk = pmbase + 0x8;<br>- fadt->gpe0_blk = pmbase + 0x28;<br>- fadt->gpe1_blk = 0;<br>-<br>- fadt->pm1_evt_len = 4;<br>- fadt->pm1_cnt_len = 2;<br>- // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)<br>- fadt->pm2_cnt_len = 2;<br>- fadt->pm_tmr_len = 4;<br>- fadt->gpe0_blk_len = 8;<br>- fadt->gpe1_blk_len = 0;<br>- fadt->gpe1_base = 0;<br>- fadt->cst_cnt = APM_CNT_CST_CONTROL;<br>- fadt->p_lvl2_lat = 1;<br>- fadt->p_lvl3_lat = 85;<br>- fadt->flush_size = 1024;<br>- fadt->flush_stride = 16;<br>- fadt->duty_offset = 1;<br>- fadt->duty_width = 0;<br>- fadt->day_alrm = 0xd;<br>- fadt->mon_alrm = 0x00;<br>- fadt->century = 0x00;<br>- fadt->iapc_boot_arch = 0x03;<br>-<br>- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |<br>- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |<br>- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;<br>-<br>- fadt->reset_reg.space_id = 0;<br>- fadt->reset_reg.bit_width = 0;<br>- fadt->reset_reg.bit_offset = 0;<br>- fadt->reset_reg.resv = 0;<br>- fadt->reset_reg.addrl = 0x0;<br>- fadt->reset_reg.addrh = 0x0;<br>-<br>- fadt->reset_value = 0;<br>- fadt->x_firmware_ctl_l = (unsigned long)facs;<br>- fadt->x_firmware_ctl_h = 0;<br>- fadt->x_dsdt_l = (unsigned long)dsdt;<br>- fadt->x_dsdt_h = 0;<br>-<br>- fadt->x_pm1a_evt_blk.space_id = 1;<br>- fadt->x_pm1a_evt_blk.bit_width = 32;<br>- fadt->x_pm1a_evt_blk.bit_offset = 0;<br>- fadt->x_pm1a_evt_blk.resv = 0;<br>- fadt->x_pm1a_evt_blk.addrl = pmbase;<br>- fadt->x_pm1a_evt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm1b_evt_blk.space_id = 1;<br>- fadt->x_pm1b_evt_blk.bit_width = 0;<br>- fadt->x_pm1b_evt_blk.bit_offset = 0;<br>- fadt->x_pm1b_evt_blk.resv = 0;<br>- fadt->x_pm1b_evt_blk.addrl = 0x0;<br>- fadt->x_pm1b_evt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm1a_cnt_blk.space_id = 1;<br>- fadt->x_pm1a_cnt_blk.bit_width = 16;<br>- fadt->x_pm1a_cnt_blk.bit_offset = 0;<br>- fadt->x_pm1a_cnt_blk.resv = 0;<br>- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;<br>- fadt->x_pm1a_cnt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm1b_cnt_blk.space_id = 1;<br>- fadt->x_pm1b_cnt_blk.bit_width = 0;<br>- fadt->x_pm1b_cnt_blk.bit_offset = 0;<br>- fadt->x_pm1b_cnt_blk.resv = 0;<br>- fadt->x_pm1b_cnt_blk.addrl = 0x0;<br>- fadt->x_pm1b_cnt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm2_cnt_blk.space_id = 1;<br>- fadt->x_pm2_cnt_blk.bit_width = 8;<br>- fadt->x_pm2_cnt_blk.bit_offset = 0;<br>- fadt->x_pm2_cnt_blk.resv = 0;<br>- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;<br>- fadt->x_pm2_cnt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm_tmr_blk.space_id = 1;<br>- fadt->x_pm_tmr_blk.bit_width = 32;<br>- fadt->x_pm_tmr_blk.bit_offset = 0;<br>- fadt->x_pm_tmr_blk.resv = 0;<br>- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;<br>- fadt->x_pm_tmr_blk.addrh = 0x0;<br>-<br>- fadt->x_gpe0_blk.space_id = 1;<br>- fadt->x_gpe0_blk.bit_width = 64;<br>- fadt->x_gpe0_blk.bit_offset = 0;<br>- fadt->x_gpe0_blk.resv = 0;<br>- fadt->x_gpe0_blk.addrl = pmbase + 0x28;<br>- fadt->x_gpe0_blk.addrh = 0x0;<br>-<br>- fadt->x_gpe1_blk.space_id = 1;<br>- fadt->x_gpe1_blk.bit_width = 0;<br>- fadt->x_gpe1_blk.bit_offset = 0;<br>- fadt->x_gpe1_blk.resv = 0;<br>- fadt->x_gpe1_blk.addrl = 0x0;<br>- fadt->x_gpe1_blk.addrh = 0x0;<br>-<br>- header->checksum = acpi_checksum((void *)fadt, header->length);<br>-}<br>diff --git a/src/mainboard/iwave/iWRainbowG6/hda_verb.c b/src/mainboard/iwave/iWRainbowG6/hda_verb.c<br>deleted file mode 100644<br>index 5e6f595..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/hda_verb.c<br>+++ /dev/null<br>@@ -1,93 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <device/azalia_device.h><br>-<br>-const u32 cim_verb_data[] = {<br>- /* coreboot specific header */<br>- 0x111d76d5, // Codec Vendor / Device ID: IDT 92HD81<br>- 0x00000000, // Subsystem ID<br>- 0x0000000a, // Number of jacks<br>-<br>- /* NID 0x0a, Port A (capless headphone) */<br>- 0x0A71C40,<br>- 0x0A71D10,<br>- 0x0A71EA1,<br>- 0x0A71F02,<br>-<br>- /* NID 0x0b, Port B (capless headphone) */<br>- 0x0B71C1F,<br>- 0x0B71D10,<br>- 0x0B71E21,<br>- 0x0B71F02,<br>-<br>- /*<br>- * NID 0x0c, Port C (Line IN/OUT+MIC for YD/UA revisions, and<br>- * Line IN+MIC for TA revision)<br>- */<br>- 0x0C71CF0,<br>- 0x0C71D00,<br>- 0x0C71E00,<br>- 0x0C71F40,<br>-<br>- /* NID 0x0d, Port D (BTL output - EAPD control) */<br>- 0x0D71C10,<br>- 0x0D71D41,<br>- 0x0D71E10,<br>- 0x0D71F10,<br>-<br>- /* NID 0x0e, Port E (Line IN/OUT) */<br>- 0x0E71CF0,<br>- 0x0E71D00,<br>- 0x0E71E00,<br>- 0x0E71F40,<br>-<br>- /* NID 0x0f, Port F (Line IN/OUT, MIC) */<br>- 0x0F71CF0,<br>- 0x0F71D00,<br>- 0x0F71E00,<br>- 0x0F71F40,<br>-<br>- /* NID 0x10, MonoOut (output-only) */<br>- 0x1071CF0,<br>- 0x1071D00,<br>- 0x1071EF0,<br>- 0x1071F40,<br>-<br>- /* NID 0x10, DigMic0 (Digital Microphone 0) */<br>- 0x1171CF0,<br>- 0x1171D00,<br>- 0x1171E00,<br>- 0x1171F40,<br>-<br>- /* NID 0x1f, Dig0Pin (First Digital Output Pin) */<br>- 0x1F71C50,<br>- 0x1F71D21,<br>- 0x1F71E40,<br>- 0x1F71F10,<br>-<br>- /* NID 0x20, Dig1Pin (Second Digital Output Pin / DMIC Input Pin) */<br>- 0x2071CF0,<br>- 0x2071D00,<br>- 0x2071E00,<br>- 0x2071F40,<br>-<br>- /* BTL Gain */<br>- 0x017F417, /* Gain = 16.79dB */<br>-};<br>-<br>-const u32 pc_beep_verbs[0] = {};<br>-<br>-AZALIA_ARRAY_SIZES;<br>diff --git a/src/mainboard/iwave/iWRainbowG6/irq_tables.c b/src/mainboard/iwave/iWRainbowG6/irq_tables.c<br>deleted file mode 100644<br>index 8ad7e25..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/irq_tables.c<br>+++ /dev/null<br>@@ -1,51 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2008 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */<br>- 0x00, /* Interrupt router bus */<br>- (0x1f << 3) | 0x0, /* Interrupt router dev */<br>- 0, /* IRQs devoted exclusively to PCI usage */<br>- 0x8086, /* Vendor */<br>- 0x8119, /* Device*/<br>- 0, /* Miniport */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0xdf, /* Checksum (has to be set to some value that<br>- * would give 0 after the sum of all bytes<br>- * for this structure (including checksum).<br>- */<br>- {<br>- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x00, (0x02 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x1e << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x1f << 3) | 0x0, {{0x62, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x1a << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x1d << 3) | 0x0, {{0x64, 0x8200}, {0x65, 0x8200}, {0x66, 0x8200}, {0x67, 0x8200}}, 0x0, 0x0},<br>- {0x00, (0x1b << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x1c << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x01, (0x00 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x02, (0x00 << 3) | 0x0, {{0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x63, 0x5cb8}, {0x60, 0x5cb8}}, 0x2, 0x0},<br>- {0x00, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- }<br>-};<br>-<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c<br>deleted file mode 100644<br>index 5ba63bc..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/mptable.c<br>+++ /dev/null<br>@@ -1,101 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2008 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <arch/smp/mpspec.h><br>-#include <device/pci.h><br>-#include <string.h><br>-#include <stdint.h><br>-<br>-void *smp_write_config_table(void *v)<br>-{<br>- struct mp_config_table *mc;<br>- int isa_bus;<br>-<br>- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);<br>- mptable_init(mc, LOCAL_APIC_ADDR);<br>-<br>- smp_write_processors(mc);<br>- mptable_write_buses(mc, NULL, &isa_bus);<br>-<br>- smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);<br>- {<br>- device_t dev;<br>- struct resource *res;<br>- dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));<br>- if (dev) {<br>- res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>- if (res) {<br>- smp_write_ioapic(mc, 3, 0x20, res->base);<br>- }<br>- }<br>- dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));<br>- if (dev) {<br>- res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>- if (res) {<br>- smp_write_ioapic(mc, 4, 0x20, res->base);<br>- }<br>- }<br>- dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));<br>- if (dev) {<br>- res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>- if (res) {<br>- smp_write_ioapic(mc, 5, 0x20, res->base);<br>- }<br>- }<br>- dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));<br>- if (dev) {<br>- res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>- if (res) {<br>- smp_write_ioapic(mc, 8, 0x20, res->base);<br>- }<br>- }<br>- }<br>-/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#<br>-*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x0, 0x1, 0x0);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x1, 0x1, 0x1);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x0, 0x1, 0x2);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x3, 0x1, 0x3);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x4, 0x1, 0x4);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x6, 0x1, 0x6);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x7, 0x1, 0x7);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x1, 0x8, 0x1, 0x8);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x9, 0x1, 0x9);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0xc, 0x1, 0xc);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0xd, 0x1, 0xd);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0xe, 0x1, 0xe);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x1, 0x10);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x1, 0x10);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x1, 0x11);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x1, 0x12);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x1, 0x13);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x1, 0x10);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x78, 0x1, 0x10);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x79, 0x1, 0x11);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7a, 0x1, 0x12);<br>-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/<br>- mptable_lintsrc(mc, isa_bus);<br>- /* There is no extension information... */<br>-<br>- /* Compute the checksums */<br>- return mptable_finalize(mc);<br>-}<br>-<br>-unsigned long write_smp_table(unsigned long addr)<br>-{<br>- void *v;<br>- v = smp_write_floating_table(addr, 0);<br>- return (unsigned long)smp_write_config_table(v);<br>-}<br>diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c<br>deleted file mode 100644<br>index a5c0c9c..0000000<br>--- a/src/mainboard/iwave/iWRainbowG6/romstage.c<br>+++ /dev/null<br>@@ -1,379 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <string.h><br>-#include <arch/io.h><br>-#include <device/pci_def.h><br>-#include <device/pnp_def.h><br>-#include <cpu/x86/lapic.h><br>-#include <cpu/x86/cache.h><br>-#include <cpu/intel/romstage.h><br>-#include <arch/cpu.h><br>-#include <console/console.h><br>-#if 0<br>-#include "ram/ramtest.c"<br>-#include "soc/intel/sch/early_smbus.c"<br>-#endif<br>-<br>-#define RFID_TEST 0<br>-<br>-#if RFID_TEST<br>-#define RFID_ADDR 0xA0<br>-#define RFID_SELECT_CARD_COMMAND 0x01<br>-#define SELECT_COMMAND_LENGTH 0x01<br>-<br>-#define SMBUS_BASE_ADDRESS 0x400<br>-<br>-static u32 sch_SMbase_read(void)<br>-{<br>- u32 SMBusBase;<br>-<br>- /* SMBus address */<br>- SMBusBase = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0x40);<br>- SMBusBase &= 0xFFFF;<br>- printk(BIOS_DEBUG, "SMBus base = %x\r\n", SMBusBase);<br>- return SMBusBase;<br>-}<br>-<br>-static void sch_SMbase_init(void)<br>-{<br>- u32 SMBusBase;<br>-<br>- SMBusBase = sch_SMbase_read();<br>- outb(0x3F, SMBusBase + SMBCLKDIV);<br>-}<br>-<br>-static void sch_SMbus_regs(void)<br>-{<br>- u32 SMBusBase;<br>-<br>- SMBusBase = sch_SMbase_read();<br>- printk(BIOS_DEBUG, "SMBHSTCNT. =%x\r\n", inb(SMBusBase + SMBHSTCNT));<br>- printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n", inb(SMBusBase + SMBHSTSTS));<br>- printk(BIOS_DEBUG, "SMBCLKDIV. =%x\r\n", inb(SMBusBase + SMBCLKDIV));<br>-<br>- printk(BIOS_DEBUG, "SMBHSTADD. =%x\r\n", inb(SMBusBase + SMBHSTADD));<br>- printk(BIOS_DEBUG, "SMBHSTCMD. =%x\r\n", inb(SMBusBase + SMBHSTCMD));<br>-}<br>-<br>-void smb_clear(void)<br>-{<br>- u32 SMBusBase;<br>-<br>- SMBusBase = sch_SMbase_read();<br>- outb(0x00, SMBusBase + SMBHSTCNT);<br>- outb(0x07, SMBusBase + SMBHSTSTS);<br>-}<br>-<br>-void data_clear(void)<br>-{<br>- u32 SMBusBase;<br>-<br>- SMBusBase = sch_SMbase_read();<br>- outb(0x00, SMBusBase + SMBHSTDAT0);<br>- outb(0x00, SMBusBase + SMBHSTCMD);<br>- outb(0x00, SMBusBase + SMBHSTDAT1);<br>- outb(0x00, SMBusBase + SMBHSTDATB);<br>- outb(0x00, SMBusBase + (SMBHSTDATB + 0x1));<br>- outb(0x00, SMBusBase + (SMBHSTDATB + 0x2));<br>- outb(0x00, SMBusBase + (SMBHSTDATB + 0x3));<br>- outb(0x00, SMBusBase + (SMBHSTDATB + 0x4));<br>- outb(0x00, SMBusBase + (SMBHSTDATB + 0x5));<br>- outb(0x00, SMBusBase + (SMBHSTDATB + 0x6));<br>-}<br>-<br>-void transaction1(unsigned char dev_addr)<br>-{<br>- int temp, a;<br>- u32 SMBusBase;<br>-<br>- SMBusBase = sch_SMbase_read();<br>- printk(BIOS_DEBUG, "Transaction 1");<br>- //clear the control and status registers<br>- smb_clear();<br>- //clear the data register<br>- data_clear();<br>- //program TSA register<br>- outb(dev_addr, SMBusBase + SMBHSTADD);<br>- //program command register<br>- outb(0x04, SMBusBase + SMBHSTCMD);<br>- //write data register<br>- outb(0x04, SMBusBase + SMBHSTDAT0);<br>- outb(0x04, SMBusBase + SMBHSTDATB);<br>-<br>- outb(0x09, SMBusBase + (SMBHSTDATB + 0x1));<br>- outb(0x11, SMBusBase + (SMBHSTDATB + 0x2));<br>- outb(0x22, SMBusBase + (SMBHSTDATB + 0x3));<br>-<br>- //set the control register<br>- outb(0x15, SMBusBase + SMBHSTCNT);<br>- //check the status register for busy state<br>- //sch_SMbus_regs ();<br>- temp = inb(SMBusBase + SMBHSTSTS);<br>- //printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);<br>- //printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));<br>- do {<br>- temp = inb(SMBusBase + SMBHSTSTS);<br>- printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n", temp);<br>- //sch_SMbus_regs ();<br>- printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",<br>- inb(SMBusBase + SMBHSTSTS));<br>- if (temp > 0)<br>- break;<br>- } while (1);<br>-<br>- switch (temp) {<br>- case 1:<br>- printk(BIOS_DEBUG, "SMBus Success");<br>- break;<br>- default:<br>- printk(BIOS_DEBUG, "SMBus error %d", temp);<br>- break;<br>-<br>- }<br>- sch_SMbus_regs();<br>- printk(BIOS_DEBUG, "Command in TRansaction 1=%x\r\n\n",<br>- inb(SMBusBase + SMBHSTCMD));<br>-}<br>-<br>-void transaction2(unsigned char dev_addr)<br>-{<br>- int temp, a;<br>- u32 SMBusBase;<br>-<br>- SMBusBase = sch_SMbase_read();<br>- printk(BIOS_DEBUG, "Transaction 2");<br>- //clear the control and status registers<br>- smb_clear();<br>- //clear the data register<br>- data_clear();<br>- //program TSA register<br>- outb(dev_addr, SMBusBase + SMBHSTADD);<br>- //program command register<br>- outb(0x03, SMBusBase + SMBHSTCMD);<br>- //write data register<br>- outb(0x02, SMBusBase + SMBHSTDAT0);<br>- outb(0x03, SMBusBase + SMBHSTDATB);<br>- outb(0x09, SMBusBase + (SMBHSTDATB + 0x1));<br>- outb(0x15, SMBusBase + SMBHSTCNT);<br>- //check the status register for busy state<br>- //sch_SMbus_regs ();<br>- temp = inb(SMBusBase + SMBHSTSTS);<br>- //printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);<br>- //printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));<br>- do {<br>- temp = inb(SMBusBase + SMBHSTSTS);<br>- printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n", temp);<br>- //sch_SMbus_regs ();<br>- printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",<br>- inb(SMBusBase + SMBHSTSTS));<br>- if (temp > 0)<br>- break;<br>- } while (1);<br>-<br>- switch (temp) {<br>- case 1:<br>- printk(BIOS_DEBUG, "SMBus Success");<br>- break;<br>- default:<br>- printk(BIOS_DEBUG, "SMBus error %d", temp);<br>- break;<br>-<br>- }<br>- sch_SMbus_regs();<br>-<br>- printk(BIOS_DEBUG, "Command in TRansaction 2=%x\r\n\n",<br>- inb(SMBusBase + SMBHSTCMD));<br>-}<br>-<br>-void transaction3(unsigned char dev_addr)<br>-{<br>- int temp, index, length;<br>- u32 SMBusBase;<br>-<br>- SMBusBase = sch_SMbase_read();<br>- printk(BIOS_DEBUG, "smb_read_multiple_bytes");<br>- smb_clear();<br>- data_clear();<br>- outb(dev_addr, SMBusBase + SMBHSTADD);<br>- outb(0x03, SMBusBase + SMBHSTCMD);<br>- outb(0x11, SMBusBase + SMBHSTCNT);<br>-<br>- //data_clear();<br>- outb(dev_addr + 1, SMBusBase + SMBHSTADD);<br>-<br>- outb(0x15, SMBusBase + SMBHSTCNT);<br>-<br>- // sch_SMbus_regs ();<br>- //check the status register for busy state<br>- //temp = inb(SMBusBase+SMBHSTSTS);<br>- //printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);<br>- //sch_SMbus_regs ();<br>- //printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));<br>- do {<br>- temp = inb(SMBusBase + SMBHSTSTS);<br>- printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",<br>- inb(SMBusBase + SMBHSTSTS));<br>- //sch_SMbus_regs ();<br>- if (temp > 0)<br>- break;<br>- } while (1);<br>-<br>- switch (temp) {<br>- case 1:<br>- printk(BIOS_DEBUG, "SMBus Success\n");<br>- break;<br>- default:<br>- printk(BIOS_DEBUG, "SMBus error %d", temp);<br>- break;<br>-<br>- }<br>-<br>- sch_SMbus_regs();<br>- printk(BIOS_DEBUG, "ADDRESS is.. %x\r\n", inb(SMBusBase + SMBHSTADD));<br>- length = inb(SMBusBase + SMBHSTDAT0);<br>-<br>- printk(BIOS_DEBUG, "Length is.. %x\r\n", inb(SMBusBase + SMBHSTDAT0));<br>-<br>- printk(BIOS_DEBUG, "Command is... %x\r\n", inb(SMBusBase + SMBHSTDATB));<br>- printk(BIOS_DEBUG, "Status .. %x\r\n", inb(SMBusBase + SMBHSTDATB + 1));<br>- for (index = 0; index < length; index++)<br>- printk(BIOS_DEBUG, "Serial Byte[%x]..%x\r\n", index,<br>- inb(SMBusBase + SMBHSTDATB + index));<br>-}<br>-<br>-int selectcard(void)<br>-{<br>- int i;<br>-<br>- printk(BIOS_DEBUG, "%s", "\r\nCase 9.......\r\n");<br>- // send the length byte and command code through RFID interface<br>-<br>- transaction1(RFID_ADDR);<br>- transaction2(RFID_ADDR);<br>- transaction3(RFID_ADDR);<br>- return (1);<br>-}<br>-#endif<br>-<br>-#include "soc/intel/sch/early_init.c"<br>-#include <soc/intel/sch/raminit.h><br>-#include "soc/intel/sch/raminit.c"<br>-<br>-static void sch_enable_lpc(void)<br>-{<br>- /* Initialize the FWH decode/Enable registers according to platform design */<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xD0, 0x00112233);<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xD4, 0xC0000000);<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x60, 0x808A8B8B);<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x64, 0x8F898F89);<br>-}<br>-<br>-static void sch_shadow_CMC(void)<br>-{<br>- u32 reg32;<br>-<br>- /* FIXME: proper dest, proper src, and wbinvd, too */<br>- memcpy((void *)CMC_SHADOW, (void *)0xfffd0000, 64 * 1024);<br>- // __asm__ volatile ("wbinvd\n"<br>- //);<br>- printk(BIOS_DEBUG, "copy done ");<br>- memcpy((void *)0x3f5f0000, (void *)0x3faf0000, 64 * 1024);<br>- printk(BIOS_DEBUG, "copy 2 done ");<br>- reg32 = cpuid_eax(0x00000001);<br>- printk(BIOS_INFO, "CPU ID: %d.\n", reg32);<br>-<br>- reg32 = cpuid_eax(0x80000008);<br>- printk(BIOS_INFO, "Physical Address size: %d.\n", (reg32 & 0xFF));<br>- printk(BIOS_INFO, "Virtual Address size: %d.\n",<br>- ((reg32 & 0xFF00) >> 8));<br>- sch_port_access_write_ram_cmd(0xB8, 4, 0, 0x3faf0000);<br>- printk(BIOS_DEBUG, "1 ");<br>- sch_port_access_write_ram_cmd(0xBA, 4, 0, reg32);<br>- printk(BIOS_DEBUG, "2 ");<br>-}<br>-<br>-static void poulsbo_setup_Stage1Regs(void)<br>-{<br>- u32 reg32;<br>-<br>- printk(BIOS_DEBUG, "E000/F000 Routing ");<br>- reg32 = sch_port_access_read(2, 3, 4);<br>- sch_port_access_write(2, 3, 4, (reg32 | 0x6));<br>-}<br>-<br>-static void poulsbo_setup_Stage2Regs(void)<br>-{<br>- u16 reg16;<br>-<br>- printk(BIOS_DEBUG, "Reserved");<br>- reg16 = pci_read_config16(PCI_DEV(0, 0x2, 0), 0x62);<br>- pci_write_config16(PCI_DEV(0, 0x2, 0), 0x62, (reg16 | 0x3));<br>- /* Slot capabilities */<br>- pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500);<br>- pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500);<br>- /* FIXME: CPU ID identification */<br>- printk(BIOS_DEBUG, " done.\n");<br>-}<br>-<br>-void mainboard_romstage_entry(unsigned long bist)<br>-{<br>- int boot_mode = 0;<br>-<br>- if (bist == 0)<br>- enable_lapic();<br>-<br>- sch_enable_lpc();<br>- console_init();<br>-<br>- /* Halt if there was a built in self test failure */<br>- // report_bist_failure(bist);<br>- // outl (0x00, 0x1088);<br>-<br>- /*<br>- * Perform some early chipset initialization required<br>- * before RAM initialization can work.<br>- */<br>- sch_early_initialization();<br>- sdram_initialize(boot_mode);<br>-<br>- sch_shadow_CMC();<br>- poulsbo_setup_Stage1Regs();<br>- poulsbo_setup_Stage2Regs();<br>-#if 0<br>- sch_SMbase_init();<br>-<br>- /* Perform some initialization that must run before stage2. */<br>-#endif<br>-<br>- /*<br>- * This should probably go away. Until now it is required<br>- * and mainboard specific.<br>- */<br>-<br>- /* Chipset Errata! */<br>- pci_write_config16(PCI_DEV(0, 0x2, 0), GGC, 0x20);<br>- pci_write_config32(PCI_DEV(0, 0x2, 0), 0xc4, 0x00000002);<br>- pci_write_config32(PCI_DEV(0, 0x2, 0), 0xe0, 0x00008000);<br>- pci_write_config32(PCI_DEV(0, 0x2, 0), 0xf0, 0x00000005);<br>- pci_write_config16(PCI_DEV(0, 0x2, 0), 0xf7, 0x80);<br>- pci_write_config16(PCI_DEV(0, 0x2, 0), 0x4, 0x7);<br>-<br>-#if RFID_TEST<br>- sch_SMbase_init();<br>- selectcard();<br>-#endif<br>-}<br>diff --git a/src/soc/intel/sch/Kconfig b/src/soc/intel/sch/Kconfig<br>deleted file mode 100644<br>index 2456df7..0000000<br>--- a/src/soc/intel/sch/Kconfig<br>+++ /dev/null<br>@@ -1,59 +0,0 @@<br>-#<br>-# This file is part of the coreboot project.<br>-#<br>-# Copyright (C) 2007-2010 coresystems GmbH<br>-#<br>-# This program is free software; you can redistribute it and/or modify<br>-# it under the terms of the GNU General Public License as published by<br>-# the Free Software Foundation; version 2 of the License.<br>-#<br>-# This program is distributed in the hope that it will be useful,<br>-# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-# GNU General Public License for more details.<br>-#<br>-<br>-config SOC_INTEL_SCH<br>- bool<br>- select LATE_CBMEM_INIT<br>- select INTEL_GMA_ACPI<br>- select SOUTHBRIDGE_INTEL_COMMON<br>- select HAVE_USBDEBUG<br>- select HAVE_HARD_RESET<br>- select HAVE_SMI_HANDLER<br>-<br>-if SOC_INTEL_SCH<br>-<br>-config BOOTBLOCK_NORTHBRIDGE_INIT<br>- string<br>- default "soc/intel/sch/bootblock.c"<br>-<br>-config VGA_BIOS_ID<br>- string<br>- default "8086,8108"<br>-<br>-config EHCI_BAR<br>- hex<br>- default 0xfef00000<br>-<br>-config HAVE_CMC<br>- bool "Add a CMC state machine binary"<br>- help<br>- Select this option to add a CMC state machine binary to<br>- the resulting coreboot image.<br>-<br>- Note: Without this binary coreboot will not work<br>-<br>-config CMC_FILE<br>- string "Intel CMC path and filename"<br>- depends on HAVE_CMC<br>- default "cmc.bin"<br>- help<br>- The path and filename of the file to use as CMC state machine<br>- binary.<br>-<br>-config HPET_MIN_TICKS<br>- hex<br>- default 0x80<br>-<br>-endif<br>diff --git a/src/soc/intel/sch/Makefile.inc b/src/soc/intel/sch/Makefile.inc<br>deleted file mode 100644<br>index 0a3cfd6..0000000<br>--- a/src/soc/intel/sch/Makefile.inc<br>+++ /dev/null<br>@@ -1,48 +0,0 @@<br>-#<br>-# This file is part of the coreboot project.<br>-#<br>-# Copyright (C) 2007-2010 coresystems GmbH<br>-#<br>-# This program is free software; you can redistribute it and/or modify<br>-# it under the terms of the GNU General Public License as published by<br>-# the Free Software Foundation; version 2 of the License.<br>-#<br>-# This program is distributed in the hope that it will be useful,<br>-# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-# GNU General Public License for more details.<br>-#<br>-<br>-ifeq ($(CONFIG_SOC_INTEL_SCH),y)<br>-<br>-ramstage-y += northbridge.c<br>-ramstage-y += gma.c<br>-ramstage-y += port_access.c<br>-ramstage-y += acpi.c<br>-<br>-ramstage-y += south.c<br>-ramstage-y += audio.c<br>-ramstage-y += lpc.c<br>-ramstage-y += ide.c<br>-ramstage-y += pcie.c<br>-ramstage-y += usb.c<br>-ramstage-y += usb_ehci.c<br>-ramstage-y += usb_client.c<br>-ramstage-y += mmc.c<br>-ramstage-y += smbus.c<br>-<br>-ramstage-y += reset.c<br>-<br>-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c<br>-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S<br>-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c<br>-<br>-ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c<br>-<br>-# We don't ship that, but booting without it is bound to fail<br>-cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin<br>-cmc.bin-file := $(call strip_quotes,$(CONFIG_CMC_FILE))<br>-cmc.bin-type := raw<br>-cmc.bin-position := 0xfffd0000<br>-<br>-endif<br>diff --git a/src/soc/intel/sch/acpi.c b/src/soc/intel/sch/acpi.c<br>deleted file mode 100644<br>index 2c941d8..0000000<br>--- a/src/soc/intel/sch/acpi.c<br>+++ /dev/null<br>@@ -1,72 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <types.h><br>-#include <string.h><br>-#include <console/console.h><br>-#include <arch/acpi.h><br>-#include <arch/acpigen.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <cbmem.h><br>-#include <arch/acpigen.h><br>-#include <cpu/cpu.h><br>-#include "sch.h"<br>-<br>-unsigned long acpi_fill_mcfg(unsigned long current)<br>-{<br>- device_t dev;<br>- u32 pciexbar = 0;<br>- u32 pciexbar_reg;<br>- int max_buses;<br>-<br>- dev = dev_find_device(0x8086, 0x27a0, 0);<br>- if (!dev)<br>- return current;<br>-<br>- pciexbar_reg = pci_read_config32(dev, 0x48);<br>-<br>- /* MMCFG not supported or not enabled. */<br>- if (!(pciexbar_reg & (1 << 0)))<br>- return current;<br>-<br>- switch ((pciexbar_reg >> 1) & 3) {<br>- case 0: /* 256MB */<br>- pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |<br>- (1 << 28));<br>- max_buses = 256;<br>- break;<br>- case 1: /* 128M */<br>- pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |<br>- (1 << 28) | (1 << 27));<br>- max_buses = 128;<br>- break;<br>- case 2: /* 64M */<br>- pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |<br>- (1 << 28) | (1 << 27) | (1 << 26));<br>- max_buses = 64;<br>- break;<br>- default: /* RSVD */<br>- return current;<br>- }<br>-<br>- if (!pciexbar)<br>- return current;<br>-<br>- current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,<br>- pciexbar, 0x0, 0x0, max_buses - 1);<br>- return current;<br>-}<br>diff --git a/src/soc/intel/sch/acpi/ac97.asl b/src/soc/intel/sch/acpi/ac97.asl<br>deleted file mode 100644<br>index e1db234..0000000<br>--- a/src/soc/intel/sch/acpi/ac97.asl<br>+++ /dev/null<br>@@ -1,33 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* Intel i82801G AC'97 Audio and Modem */<br>-<br>-// Intel AC'97 Audio 0:1e.2<br>-<br>-Device (AUD0)<br>-{<br>- Name (_ADR, 0x001e0002)<br>-}<br>-<br>-// Intel AC'97 Modem 0:1e.3<br>-<br>-Device (MODM)<br>-{<br>- Name (_ADR, 0x001e0003)<br>-<br>- Name (_PRW, Package(){ 5, 4 })<br>-}<br>diff --git a/src/soc/intel/sch/acpi/audio.asl b/src/soc/intel/sch/acpi/audio.asl<br>deleted file mode 100644<br>index 9e0d997..0000000<br>--- a/src/soc/intel/sch/acpi/audio.asl<br>+++ /dev/null<br>@@ -1,30 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* Intel i82801G HDA */<br>-<br>-// Intel High Definition Audio (Azalia) 0:1b.0<br>-<br>-Device (HDEF)<br>-{<br>- Name (_ADR, 0x001b0000)<br>-<br>- // Power Resources for Wake<br>- Name (_PRW, Package(){<br>- 5, // Bit 5 of GPE<br>- 4 // Can wake from S4 state.<br>- })<br>-}<br>diff --git a/src/soc/intel/sch/acpi/globalnvs.asl b/src/soc/intel/sch/acpi/globalnvs.asl<br>deleted file mode 100644<br>index ea53953..0000000<br>--- a/src/soc/intel/sch/acpi/globalnvs.asl<br>+++ /dev/null<br>@@ -1,156 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* Global Variables */<br>-<br>-Name(\PICM, 0) // IOAPIC/8259<br>-Name(\DSEN, 1) // Display Output Switching Enable<br>-<br>-/* Global ACPI memory region. This region is used for passing information<br>- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.<br>- * Since we don't know where this will end up in memory at ACPI compile time,<br>- * we have to fix it up in coreboot's ACPI creation phase.<br>- */<br>-<br>-External(NVSA)<br>-OperationRegion (GNVS, SystemMemory, NVSA, 0x100)<br>-Field (GNVS, ByteAcc, NoLock, Preserve)<br>-{<br>- /* Miscellaneous */<br>- Offset (0x00),<br>- OSYS, 16, // 0x00 - Operating System<br>- SMIF, 8, // 0x02 - SMI function<br>- PRM0, 8, // 0x03 - SMI function parameter<br>- PRM1, 8, // 0x04 - SMI function parameter<br>- SCIF, 8, // 0x05 - SCI function<br>- PRM2, 8, // 0x06 - SCI function parameter<br>- PRM3, 8, // 0x07 - SCI function parameter<br>- LCKF, 8, // 0x08 - Global Lock function for EC<br>- PRM4, 8, // 0x09 - Lock function parameter<br>- PRM5, 8, // 0x0a - Lock function parameter<br>- P80D, 32, // 0x0b - Debug port (IO 0x80) value<br>- LIDS, 8, // 0x0f - LID state (open = 1)<br>- PWRS, 8, // 0x10 - Power State (AC = 1)<br>- DBGS, 8, // 0x11 - Debug State<br>- LINX, 8, // 0x12 - Linux OS<br>- DCKN, 8, // 0x13 - PCIe docking state<br>- /* Thermal policy */<br>- Offset (0x14),<br>- ACTT, 8, // 0x14 - active trip point<br>- PSVT, 8, // 0x15 - passive trip point<br>- TC1V, 8, // 0x16 - passive trip point TC1<br>- TC2V, 8, // 0x17 - passive trip point TC2<br>- TSPV, 8, // 0x18 - passive trip point TSP<br>- CRTT, 8, // 0x19 - critical trip point<br>- DTSE, 8, // 0x1a - Digital Thermal Sensor enable<br>- DTS1, 8, // 0x1b - DT sensor 1<br>- DTS2, 8, // 0x1c - DT sensor 2<br>- /* Battery Support */<br>- Offset (0x1e),<br>- BNUM, 8, // 0x1e - number of batteries<br>- B0SC, 8, // 0x1f - BAT0 stored capacity<br>- B1SC, 8, // 0x20 - BAT1 stored capacity<br>- B2SC, 8, // 0x21 - BAT2 stored capacity<br>- B0SS, 8, // 0x22 - BAT0 stored status<br>- B1SS, 8, // 0x23 - BAT1 stored status<br>- B2SS, 8, // 0x24 - BAT2 stored status<br>- /* Processor Identification */<br>- Offset (0x28),<br>- APIC, 8, // 0x28 - APIC Enabled by coreboot<br>- MPEN, 8, // 0x29 - Multi Processor Enable<br>- PCP0, 8, // 0x2a - PDC CPU/CORE 0<br>- PCP1, 8, // 0x2b - PDC CPU/CORE 1<br>- PPCM, 8, // 0x2c - Max. PPC state<br>- /* Super I/O & CMOS config */<br>- Offset (0x32),<br>- NATP, 8, // 0x32 - ...<br>- /* Integrated Graphics Device */<br>- Offset (0x3c),<br>- IGDS, 8, // 0x3c - IGD state (primary = 1)<br>- TLST, 8, // 0x3d - Display Toggle List pointer<br>- CADL, 8, // 0x3e - Currently Attached Devices List<br>- PADL, 8, // 0x3f - Previously Attached Devices List<br>- CSTE, 16, // 0x40 - Current display state<br>- NSTE, 16, // 0x42 - Next display state<br>- SSTE, 16, // 0x44 - Set display state<br>- Offset (0x46),<br>- NDID, 8, // 0x46 - Number of Device IDs<br>- DID1, 32, // 0x47 - Device ID 1<br>- DID2, 32, // 0x4b - Device ID 2<br>- DID3, 32, // 0x4f - Device ID 3<br>- DID4, 32, // 0x53 - Device ID 4<br>- DID5, 32, // 0x57 - Device ID 5<br>- /* Backlight Control */<br>- Offset (0x64),<br>- BLCS, 8, // 0x64 - Backlight control possible?<br>- BRTL, 8, // 0x65 - Brightness Level<br>- ODDS, 8, // 0x66<br>- /* Ambient Light Sensors */<br>- Offset (0x6e),<br>- ALSE, 8, // 0x6e - ALS enable<br>- ALAF, 8, // 0x6f - Ambient light adjustment factor<br>- LLOW, 8, // 0x70 - LUX Low<br>- LHIH, 8, // 0x71 - LUX High<br>- /* EMA */<br>- Offset (0x78),<br>- EMAE, 8, // 0x78 - EMA enable<br>- EMAP, 16, // 0x79 - EMA pointer<br>- EMAL, 16, // 0x7b - EMA length<br>- /* MEF */<br>- Offset (0x82),<br>- MEFE, 8, // 0x82 - MEF enable<br>- /* TPM support */<br>- Offset (0x8c),<br>- TPMP, 8, // 0x8c - TPM<br>- TPME, 8, // 0x8d - TPM enable<br>- /* SATA */<br>- Offset (0x96),<br>- GTF0, 56, // 0x96 - GTF task file buffer for port 0<br>- GTF1, 56, // 0x9d - GTF task file buffer for port 1<br>- GTF2, 56, // 0xa4 - GTF task file buffer for port 2<br>- IDEM, 8, // 0xab - IDE mode (compatible / enhanced)<br>- IDET, 8, // 0xac - IDE<br>- /* IGD OpRegion */<br>- Offset (0xb4),<br>- ASLB, 32, // 0xb4 - IGD OpRegion Base Address<br>- IBTT, 8, // 0xb8 - IGD boot panel device<br>- IPAT, 8, // 0xb9 - IGD panel type cmos option<br>- ITVF, 8, // 0xba - IGD TV format cmos option<br>- ITVM, 8, // 0xbb - IGD TV minor format option<br>- IPSC, 8, // 0xbc - IGD panel scaling<br>- IBLC, 8, // 0xbd - IGD BLC config<br>- IBIA, 8, // 0xbe - IGD BIA config<br>- ISSC, 8, // 0xbf - IGD SSC config<br>- I409, 8, // 0xc0 - IGD 0409 modified settings<br>- I509, 8, // 0xc1 - IGD 0509 modified settings<br>- I609, 8, // 0xc2 - IGD 0609 modified settings<br>- I709, 8, // 0xc3 - IGD 0709 modified settings<br>- IDMM, 8, // 0xc4 - IGD DVMT Mode<br>- IDMS, 8, // 0xc5 - IGD DVMT memory size<br>- IF1E, 8, // 0xc6 - IGD function 1 enable<br>- HVCO, 8, // 0xc7 - IGD HPLL VCO<br>- NXD1, 32, // 0xc8 - IGD _DGS next DID1<br>- NXD2, 32, // 0xcc - IGD _DGS next DID2<br>- NXD3, 32, // 0xd0 - IGD _DGS next DID3<br>- NXD4, 32, // 0xd4 - IGD _DGS next DID4<br>- NXD5, 32, // 0xd8 - IGD _DGS next DID5<br>- NXD6, 32, // 0xdc - IGD _DGS next DID6<br>- NXD7, 32, // 0xe0 - IGD _DGS next DID7<br>- NXD8, 32, // 0xe4 - IGD _DGS next DID8<br>- /* Mainboard Specific (TODO move elsewhere) */<br>- Offset (0xf0),<br>- DOCK, 8, // 0xf0 - Docking Status<br>-}<br>diff --git a/src/soc/intel/sch/acpi/hostbridge.asl b/src/soc/intel/sch/acpi/hostbridge.asl<br>deleted file mode 100644<br>index 67bee8c..0000000<br>--- a/src/soc/intel/sch/acpi/hostbridge.asl<br>+++ /dev/null<br>@@ -1,233 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/ioapic.h><br>-<br>-Name(_HID,EISAID("PNP0A08")) // PCIe<br>-Name(_CID,EISAID("PNP0A03")) // PCI<br>-<br>-Name(_ADR, 0)<br>-Name(_BBN, 0)<br>-<br>-Device (MCHC)<br>-{<br>- Name(_ADR, 0x00000000) // 0:0.0<br>-<br>- OperationRegion(MCHP, PCI_Config, 0x00, 0x100)<br>- Field (MCHP, DWordAcc, NoLock, Preserve)<br>- {<br>- Offset (0x40), // EPBAR<br>- EPEN, 1, // Enable<br>- , 11, //<br>- EPBR, 20, // EPBAR<br>-<br>- Offset (0x44), // MCHBAR<br>- MHEN, 1, // Enable<br>- , 13, //<br>- MHBR, 18, // MCHBAR<br>-<br>- Offset (0x48), // PCIe BAR<br>- PXEN, 1, // Enable<br>- PXSZ, 2, // BAR size<br>- , 23, //<br>- PXBR, 6, // PCIe BAR<br>-<br>- Offset (0x4c), // DMIBAR<br>- DMEN, 1, // Enable<br>- , 11, //<br>- DMBR, 20, // DMIBAR<br>-<br>- // ...<br>-<br>- Offset (0x90), // PAM0<br>- , 4,<br>- PM0H, 2,<br>- , 2,<br>- Offset (0x91), // PAM1<br>- PM1L, 2,<br>- , 2,<br>- PM1H, 2,<br>- , 2,<br>- Offset (0x92), // PAM2<br>- PM2L, 2,<br>- , 2,<br>- PM2H, 2,<br>- , 2,<br>- Offset (0x93), // PAM3<br>- PM3L, 2,<br>- , 2,<br>- PM3H, 2,<br>- , 2,<br>- Offset (0x94), // PAM4<br>- PM4L, 2,<br>- , 2,<br>- PM4H, 2,<br>- , 2,<br>- Offset (0x95), // PAM5<br>- PM5L, 2,<br>- , 2,<br>- PM5H, 2,<br>- , 2,<br>- Offset (0x96), // PAM6<br>- PM6L, 2,<br>- , 2,<br>- PM6H, 2,<br>- , 2,<br>-<br>- Offset (0x9c), // Top of Low Used Memory<br>- , 3,<br>- TLUD, 5,<br>-<br>- Offset (0xa0), // Top of Used Memory<br>- TOM, 16,<br>- }<br>-<br>-}<br>-<br>-<br>-// Current Resource Settings<br>-Name (MCRS, ResourceTemplate()<br>-{<br>- // Bus Numbers<br>- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,<br>- 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)<br>-<br>- // IO Region 0<br>- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,<br>- 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)<br>-<br>- // PCI Config Space<br>- Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)<br>-<br>- // IO Region 1<br>- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,<br>- 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)<br>-<br>- // VGA memory (0xa0000-0xbffff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,<br>- 0x00020000,,, ASEG)<br>-<br>- // OPROM reserved (0xc0000-0xc3fff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,<br>- 0x00004000,,, OPR0)<br>-<br>- // OPROM reserved (0xc4000-0xc7fff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,<br>- 0x00004000,,, OPR1)<br>-<br>- // OPROM reserved (0xc8000-0xcbfff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,<br>- 0x00004000,,, OPR2)<br>-<br>- // OPROM reserved (0xcc000-0xcffff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,<br>- 0x00004000,,, OPR3)<br>-<br>- // OPROM reserved (0xd0000-0xd3fff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,<br>- 0x00004000,,, OPR4)<br>-<br>- // OPROM reserved (0xd4000-0xd7fff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,<br>- 0x00004000,,, OPR5)<br>-<br>- // OPROM reserved (0xd8000-0xdbfff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,<br>- 0x00004000,,, OPR6)<br>-<br>- // OPROM reserved (0xdc000-0xdffff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,<br>- 0x00004000,,, OPR7)<br>-<br>- // BIOS Extension (0xe0000-0xe3fff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,<br>- 0x00004000,,, ESG0)<br>-<br>- // BIOS Extension (0xe4000-0xe7fff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,<br>- 0x00004000,,, ESG1)<br>-<br>- // BIOS Extension (0xe8000-0xebfff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,<br>- 0x00004000,,, ESG2)<br>-<br>- // BIOS Extension (0xec000-0xeffff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000ec000, 0x000effff, 0x00000000,<br>- 0x00004000,,, ESG3)<br>-<br>- // System BIOS (0xf0000-0xfffff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,<br>- 0x00010000,,, FSEG)<br>-<br>- // PCI Memory Region (Top of memory-0xfebfffff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,<br>- IO_APIC_ADDR,,, PM01)<br>-<br>- // TPM Area (0xfed40000-0xfed44fff)<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,<br>- Cacheable, ReadWrite,<br>- 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,<br>- 0x00005000,,, TPMR)<br>-})<br>-<br>-Method (_CRS, 0, Serialized)<br>-{<br>- // Find PCI resource area in MCRS<br>- CreateDwordField(MCRS, ^PM01._MIN, PMIN)<br>- CreateDwordField(MCRS, ^PM01._MAX, PMAX)<br>- CreateDwordField(MCRS, ^PM01._LEN, PLEN)<br>-<br>- // Fix up PCI memory region:<br>- // Enter actual TOLUD. The TOLUD register contains bits 27-31 of<br>- // the top of memory address.<br>- ShiftLeft (^MCHC.TLUD, 27, PMIN)<br>- Add(Subtract(PMAX, PMIN), 1, PLEN)<br>-<br>- Return (MCRS)<br>-}<br>-<br>-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */<br>-#include "acpi/northbridge_pci_irqs.asl"<br>diff --git a/src/soc/intel/sch/acpi/igd.asl b/src/soc/intel/sch/acpi/igd.asl<br>deleted file mode 100644<br>index dcc782f..0000000<br>--- a/src/soc/intel/sch/acpi/igd.asl<br>+++ /dev/null<br>@@ -1,73 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-Device (GFX0)<br>-{<br>- Name (_ADR, 0x00020000)<br>-<br>- OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)<br>- Field (GFXC, DWordAcc, NoLock, Preserve)<br>- {<br>- Offset (0x10),<br>- BAR0, 64<br>- }<br>-<br>- OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)<br>- Field (GFRG, DWordAcc, NoLock, Preserve)<br>- {<br>- Offset (0x61250),<br>- CR1, 32,<br>- BCLV, 16,<br>- BCLM, 16,<br>- }<br>-<br>- Name (BRIG, Package (0x12)<br>- {<br>- 0x61,<br>- 0x61,<br>- 0x2,<br>- 0x4,<br>- 0x5,<br>- 0x7,<br>- 0x9,<br>- 0xb,<br>- 0xd,<br>- 0x11,<br>- 0x14,<br>- 0x17,<br>- 0x1c,<br>- 0x20,<br>- 0x27,<br>- 0x31,<br>- 0x41,<br>- 0x61,<br>- })<br>-<br>- Method (XBCM, 1, NotSerialized)<br>- {<br>- Store (ShiftLeft (Arg0, 4), BCLV)<br>- Store (0x80000000, CR1)<br>- Store (0x0610, BCLM)<br>- }<br>-<br>- Method (XBQC, 0, NotSerialized)<br>- {<br>- Store (BCLV, Local0)<br>- ShiftRight (Local0, 4, Local0)<br>- Return (Local0)<br>- }<br>-#include <drivers/intel/gma/acpi/common.asl><br>-}<br>diff --git a/src/soc/intel/sch/acpi/irqlinks.asl b/src/soc/intel/sch/acpi/irqlinks.asl<br>deleted file mode 100644<br>index 2d02924..0000000<br>--- a/src/soc/intel/sch/acpi/irqlinks.asl<br>+++ /dev/null<br>@@ -1,487 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-Device (LNKA)<br>-{<br>- Name (_HID, EISAID("PNP0C0F"))<br>- Name (_UID, 1)<br>-<br>- // Disable method<br>- Method (_DIS, 0, Serialized)<br>- {<br>- Store (0x80, PRTA)<br>- }<br>-<br>- // Possible Resource Settings for this Link<br>- Name (_PRS, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared)<br>- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }<br>- })<br>-<br>- // Current Resource Settings for this link<br>- Method (_CRS, 0, Serialized)<br>- {<br>- Name (RTLA, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared) {}<br>- })<br>- CreateWordField(RTLA, 1, IRQ0)<br>-<br>- // Clear the WordField<br>- Store (Zero, IRQ0)<br>-<br>- // Set the bit from PRTA<br>- ShiftLeft(1, And(PRTA, 0x0f), IRQ0)<br>-<br>- Return (RTLA)<br>- }<br>-<br>- // Set Resource Setting for this IRQ link<br>- Method (_SRS, 1, Serialized)<br>- {<br>- CreateWordField(Arg0, 1, IRQ0)<br>-<br>- // Which bit is set?<br>- FindSetRightBit(IRQ0, Local0)<br>-<br>- Decrement(Local0)<br>- Store(Local0, PRTA)<br>- }<br>-<br>- // Status<br>- Method (_STA, 0, Serialized)<br>- {<br>- If(And(PRTA, 0x80)) {<br>- Return (0x9)<br>- } Else {<br>- Return (0xb)<br>- }<br>- }<br>-}<br>-<br>-Device (LNKB)<br>-{<br>- Name (_HID, EISAID("PNP0C0F"))<br>- Name (_UID, 2)<br>-<br>- // Disable method<br>- Method (_DIS, 0, Serialized)<br>- {<br>- Store (0x80, PRTB)<br>- }<br>-<br>- // Possible Resource Settings for this Link<br>- Name (_PRS, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared)<br>- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }<br>- })<br>-<br>- // Current Resource Settings for this link<br>- Method (_CRS, 0, Serialized)<br>- {<br>- Name (RTLB, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared) {}<br>- })<br>- CreateWordField(RTLB, 1, IRQ0)<br>-<br>- // Clear the WordField<br>- Store (Zero, IRQ0)<br>-<br>- // Set the bit from PRTB<br>- ShiftLeft(1, And(PRTB, 0x0f), IRQ0)<br>-<br>- Return (RTLB)<br>- }<br>-<br>- // Set Resource Setting for this IRQ link<br>- Method (_SRS, 1, Serialized)<br>- {<br>- CreateWordField(Arg0, 1, IRQ0)<br>-<br>- // Which bit is set?<br>- FindSetRightBit(IRQ0, Local0)<br>-<br>- Decrement(Local0)<br>- Store(Local0, PRTB)<br>- }<br>-<br>- // Status<br>- Method (_STA, 0, Serialized)<br>- {<br>- If(And(PRTB, 0x80)) {<br>- Return (0x9)<br>- } Else {<br>- Return (0xb)<br>- }<br>- }<br>-}<br>-<br>-Device (LNKC)<br>-{<br>- Name (_HID, EISAID("PNP0C0F"))<br>- Name (_UID, 3)<br>-<br>- // Disable method<br>- Method (_DIS, 0, Serialized)<br>- {<br>- Store (0x80, PRTC)<br>- }<br>-<br>- // Possible Resource Settings for this Link<br>- Name (_PRS, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared)<br>- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }<br>- })<br>-<br>- // Current Resource Settings for this link<br>- Method (_CRS, 0, Serialized)<br>- {<br>- Name (RTLC, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared) {}<br>- })<br>- CreateWordField(RTLC, 1, IRQ0)<br>-<br>- // Clear the WordField<br>- Store (Zero, IRQ0)<br>-<br>- // Set the bit from PRTC<br>- ShiftLeft(1, And(PRTC, 0x0f), IRQ0)<br>-<br>- Return (RTLC)<br>- }<br>-<br>- // Set Resource Setting for this IRQ link<br>- Method (_SRS, 1, Serialized)<br>- {<br>- CreateWordField(Arg0, 1, IRQ0)<br>-<br>- // Which bit is set?<br>- FindSetRightBit(IRQ0, Local0)<br>-<br>- Decrement(Local0)<br>- Store(Local0, PRTC)<br>- }<br>-<br>- // Status<br>- Method (_STA, 0, Serialized)<br>- {<br>- If(And(PRTC, 0x80)) {<br>- Return (0x9)<br>- } Else {<br>- Return (0xb)<br>- }<br>- }<br>-}<br>-<br>-Device (LNKD)<br>-{<br>- Name (_HID, EISAID("PNP0C0F"))<br>- Name (_UID, 4)<br>-<br>- // Disable method<br>- Method (_DIS, 0, Serialized)<br>- {<br>- Store (0x80, PRTD)<br>- }<br>-<br>- // Possible Resource Settings for this Link<br>- Name (_PRS, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared)<br>- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }<br>- })<br>-<br>- // Current Resource Settings for this link<br>- Method (_CRS, 0, Serialized)<br>- {<br>- Name (RTLD, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared) {}<br>- })<br>- CreateWordField(RTLD, 1, IRQ0)<br>-<br>- // Clear the WordField<br>- Store (Zero, IRQ0)<br>-<br>- // Set the bit from PRTD<br>- ShiftLeft(1, And(PRTD, 0x0f), IRQ0)<br>-<br>- Return (RTLD)<br>- }<br>-<br>- // Set Resource Setting for this IRQ link<br>- Method (_SRS, 1, Serialized)<br>- {<br>- CreateWordField(Arg0, 1, IRQ0)<br>-<br>- // Which bit is set?<br>- FindSetRightBit(IRQ0, Local0)<br>-<br>- Decrement(Local0)<br>- Store(Local0, PRTD)<br>- }<br>-<br>- // Status<br>- Method (_STA, 0, Serialized)<br>- {<br>- If(And(PRTD, 0x80)) {<br>- Return (0x9)<br>- } Else {<br>- Return (0xb)<br>- }<br>- }<br>-}<br>-<br>-Device (LNKE)<br>-{<br>- Name (_HID, EISAID("PNP0C0F"))<br>- Name (_UID, 5)<br>-<br>- // Disable method<br>- Method (_DIS, 0, Serialized)<br>- {<br>- Store (0x80, PRTE)<br>- }<br>-<br>- // Possible Resource Settings for this Link<br>- Name (_PRS, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared)<br>- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }<br>- })<br>-<br>- // Current Resource Settings for this link<br>- Method (_CRS, 0, Serialized)<br>- {<br>- Name (RTLE, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared) {}<br>- })<br>- CreateWordField(RTLE, 1, IRQ0)<br>-<br>- // Clear the WordField<br>- Store (Zero, IRQ0)<br>-<br>- // Set the bit from PRTE<br>- ShiftLeft(1, And(PRTE, 0x0f), IRQ0)<br>-<br>- Return (RTLE)<br>- }<br>-<br>- // Set Resource Setting for this IRQ link<br>- Method (_SRS, 1, Serialized)<br>- {<br>- CreateWordField(Arg0, 1, IRQ0)<br>-<br>- // Which bit is set?<br>- FindSetRightBit(IRQ0, Local0)<br>-<br>- Decrement(Local0)<br>- Store(Local0, PRTE)<br>- }<br>-<br>- // Status<br>- Method (_STA, 0, Serialized)<br>- {<br>- If(And(PRTE, 0x80)) {<br>- Return (0x9)<br>- } Else {<br>- Return (0xb)<br>- }<br>- }<br>-}<br>-<br>-Device (LNKF)<br>-{<br>- Name (_HID, EISAID("PNP0C0F"))<br>- Name (_UID, 6)<br>-<br>- // Disable method<br>- Method (_DIS, 0, Serialized)<br>- {<br>- Store (0x80, PRTF)<br>- }<br>-<br>- // Possible Resource Settings for this Link<br>- Name (_PRS, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared)<br>- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }<br>- })<br>-<br>- // Current Resource Settings for this link<br>- Method (_CRS, 0, Serialized)<br>- {<br>- Name (RTLF, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared) {}<br>- })<br>- CreateWordField(RTLF, 1, IRQ0)<br>-<br>- // Clear the WordField<br>- Store (Zero, IRQ0)<br>-<br>- // Set the bit from PRTF<br>- ShiftLeft(1, And(PRTF, 0x0f), IRQ0)<br>-<br>- Return (RTLF)<br>- }<br>-<br>- // Set Resource Setting for this IRQ link<br>- Method (_SRS, 1, Serialized)<br>- {<br>- CreateWordField(Arg0, 1, IRQ0)<br>-<br>- // Which bit is set?<br>- FindSetRightBit(IRQ0, Local0)<br>-<br>- Decrement(Local0)<br>- Store(Local0, PRTF)<br>- }<br>-<br>- // Status<br>- Method (_STA, 0, Serialized)<br>- {<br>- If(And(PRTF, 0x80)) {<br>- Return (0x9)<br>- } Else {<br>- Return (0xb)<br>- }<br>- }<br>-}<br>-<br>-Device (LNKG)<br>-{<br>- Name (_HID, EISAID("PNP0C0F"))<br>- Name (_UID, 7)<br>-<br>- // Disable method<br>- Method (_DIS, 0, Serialized)<br>- {<br>- Store (0x80, PRTG)<br>- }<br>-<br>- // Possible Resource Settings for this Link<br>- Name (_PRS, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared)<br>- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }<br>- })<br>-<br>- // Current Resource Settings for this link<br>- Method (_CRS, 0, Serialized)<br>- {<br>- Name (RTLG, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared) {}<br>- })<br>- CreateWordField(RTLG, 1, IRQ0)<br>-<br>- // Clear the WordField<br>- Store (Zero, IRQ0)<br>-<br>- // Set the bit from PRTG<br>- ShiftLeft(1, And(PRTG, 0x0f), IRQ0)<br>-<br>- Return (RTLG)<br>- }<br>-<br>- // Set Resource Setting for this IRQ link<br>- Method (_SRS, 1, Serialized)<br>- {<br>- CreateWordField(Arg0, 1, IRQ0)<br>-<br>- // Which bit is set?<br>- FindSetRightBit(IRQ0, Local0)<br>-<br>- Decrement(Local0)<br>- Store(Local0, PRTG)<br>- }<br>-<br>- // Status<br>- Method (_STA, 0, Serialized)<br>- {<br>- If(And(PRTG, 0x80)) {<br>- Return (0x9)<br>- } Else {<br>- Return (0xb)<br>- }<br>- }<br>-}<br>-<br>-Device (LNKH)<br>-{<br>- Name (_HID, EISAID("PNP0C0F"))<br>- Name (_UID, 8)<br>-<br>- // Disable method<br>- Method (_DIS, 0, Serialized)<br>- {<br>- Store (0x80, PRTH)<br>- }<br>-<br>- // Possible Resource Settings for this Link<br>- Name (_PRS, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared)<br>- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }<br>- })<br>-<br>- // Current Resource Settings for this link<br>- Method (_CRS, 0, Serialized)<br>- {<br>- Name (RTLH, ResourceTemplate()<br>- {<br>- IRQ(Level, ActiveLow, Shared) {}<br>- })<br>- CreateWordField(RTLH, 1, IRQ0)<br>-<br>- // Clear the WordField<br>- Store (Zero, IRQ0)<br>-<br>- // Set the bit from PRTH<br>- ShiftLeft(1, And(PRTH, 0x0f), IRQ0)<br>-<br>- Return (RTLH)<br>- }<br>-<br>- // Set Resource Setting for this IRQ link<br>- Method (_SRS, 1, Serialized)<br>- {<br>- CreateWordField(Arg0, 1, IRQ0)<br>-<br>- // Which bit is set?<br>- FindSetRightBit(IRQ0, Local0)<br>-<br>- Decrement(Local0)<br>- Store(Local0, PRTH)<br>- }<br>-<br>- // Status<br>- Method (_STA, 0, Serialized)<br>- {<br>- If(And(PRTH, 0x80)) {<br>- Return (0x9)<br>- } Else {<br>- Return (0xb)<br>- }<br>- }<br>-}<br>diff --git a/src/soc/intel/sch/acpi/lpc.asl b/src/soc/intel/sch/acpi/lpc.asl<br>deleted file mode 100644<br>index 518bdae..0000000<br>--- a/src/soc/intel/sch/acpi/lpc.asl<br>+++ /dev/null<br>@@ -1,261 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-// Intel LPC Bus Device - 0:1f.0<br>-<br>-Device (LPCB)<br>-{<br>- Name(_ADR, 0x001f0000)<br>-<br>- OperationRegion(LPC0, PCI_Config, 0x00, 0x100)<br>- Field (LPC0, AnyAcc, NoLock, Preserve)<br>- {<br>- Offset (0x40),<br>- PMBS, 16, // PMBASE<br>- Offset (0x60), // Interrupt Routing Registers<br>- PRTA, 8,<br>- PRTB, 8,<br>- PRTC, 8,<br>- PRTD, 8,<br>- Offset (0x68),<br>- PRTE, 8,<br>- PRTF, 8,<br>- PRTG, 8,<br>- PRTH, 8,<br>-<br>- Offset (0x80), // IO Decode Ranges<br>- IOD0, 8,<br>- IOD1, 8,<br>-<br>- Offset (0xf0), // RCBA<br>- RCEN, 1,<br>- , 13,<br>- RCBA, 18,<br>- }<br>-<br>-// #include "irqlinks.asl"<br>- #include "irqlinks.asl"<br>-<br>- #include "acpi/ec.asl"<br>-<br>- Device (DMAC) // DMA Controller<br>- {<br>- Name(_HID, EISAID("PNP0200"))<br>- Name(_CRS, ResourceTemplate()<br>- {<br>- IO (Decode16, 0x00, 0x00, 0x01, 0x20)<br>- IO (Decode16, 0x81, 0x81, 0x01, 0x11)<br>- IO (Decode16, 0x93, 0x93, 0x01, 0x0d)<br>- IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)<br>- DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }<br>- })<br>- }<br>-<br>- Device (FWH) // Firmware Hub<br>- {<br>- Name (_HID, EISAID("INT0800"))<br>- Name (_CRS, ResourceTemplate()<br>- {<br>- Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)<br>- })<br>- }<br>-<br>- Device (HPET)<br>- {<br>- Name (_HID, EISAID("PNP0103"))<br>- Name (_CID, 0x010CD041)<br>-<br>- Name(BUF0, ResourceTemplate()<br>- {<br>- Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0)<br>- })<br>-<br>- Method (_STA, 0) // Device Status<br>- {<br>- If (HPTE) {<br>- // Note: Ancient versions of Windows don't want<br>- // to see the HPET in order to work right<br>- If (LGreaterEqual(OSYS, 2001)) {<br>- Return (0xf) // Enable and show device<br>- } Else {<br>- Return (0xb) // Enable and don't show device<br>- }<br>- }<br>-<br>- Return (0x0) // Not enabled, don't show.<br>- }<br>-<br>- Method (_CRS, 0, Serialized) // Current resources<br>- {<br>- If (HPTE) {<br>- CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)<br>- If (Lequal(HPAS, 1)) {<br>- Store(0xfed01000, HPT0)<br>- }<br>-<br>- If (Lequal(HPAS, 2)) {<br>- Store(0xfed02000, HPT0)<br>- }<br>-<br>- If (Lequal(HPAS, 3)) {<br>- Store(0xfed03000, HPT0)<br>- }<br>- }<br>-<br>- Return (BUF0)<br>- }<br>- }<br>-<br>- Device(PIC) // 8259 Interrupt Controller<br>- {<br>- Name(_HID,EISAID("PNP0000"))<br>- Name(_CRS, ResourceTemplate()<br>- {<br>- IO (Decode16, 0x20, 0x20, 0x01, 0x02)<br>- IO (Decode16, 0x24, 0x24, 0x01, 0x02)<br>- IO (Decode16, 0x28, 0x28, 0x01, 0x02)<br>- IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)<br>- IO (Decode16, 0x30, 0x30, 0x01, 0x02)<br>- IO (Decode16, 0x34, 0x34, 0x01, 0x02)<br>- IO (Decode16, 0x38, 0x38, 0x01, 0x02)<br>- IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)<br>- IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)<br>- IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)<br>- IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)<br>- IO (Decode16, 0xac, 0xac, 0x01, 0x02)<br>- IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)<br>- IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)<br>- IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)<br>- IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)<br>- IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)<br>- IRQNoFlags () { 2 }<br>- })<br>- }<br>-<br>- Device(MATH) // FPU<br>- {<br>- Name (_HID, EISAID("PNP0C04"))<br>- Name (_CRS, ResourceTemplate()<br>- {<br>- IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)<br>- IRQNoFlags() { 13 }<br>- })<br>- }<br>-<br>- Device(LDRC) // LPC device: Resource consumption<br>- {<br>- Name (_HID, EISAID("PNP0C02"))<br>- Name (_UID, 2)<br>- Name (_CRS, ResourceTemplate()<br>- {<br>- IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO<br>- IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO<br>- IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status<br>- IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved<br>- IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved<br>- IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved<br>- IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post<br>- IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved<br>- IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI<br>- // IO (Decode16, 0x680, 0x680, 0x1, 0x70) // IO ???<br>- IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap<br>- IO (Decode16, 0x0500, 0x0500, 0x1, 0x80) // ICH7-M ACPI<br>- IO (Decode16, 0x0480, 0x0480, 0x1, 0x40) // ICH7-M GPIO<br>- // IO (Decode16, 0x1640, 0x1640, 0x1, 0x10) // IO ???<br>- })<br>- }<br>-<br>- Device (RTC) // Real Time Clock<br>- {<br>- Name (_HID, EISAID("PNP0B00"))<br>- Name (_CRS, ResourceTemplate()<br>- {<br>- IO (Decode16, 0x70, 0x70, 1, 8)<br>- IRQNoFlags() { 8 }<br>- })<br>- }<br>-<br>- Device (TIMR) // Intel 8254 timer<br>- {<br>- Name(_HID, EISAID("PNP0100"))<br>- Name(_CRS, ResourceTemplate()<br>- {<br>- IO (Decode16, 0x40, 0x40, 0x01, 0x04)<br>- IO (Decode16, 0x50, 0x50, 0x10, 0x04)<br>- IRQNoFlags() {0}<br>- })<br>- }<br>-<br>- #include "acpi/superio.asl"<br>-<br>- Device (PS2K) // Keyboard<br>- {<br>- Name(_HID, EISAID("PNP0303"))<br>- Name(_CID, EISAID("PNP030B"))<br>-<br>- Name(_CRS, ResourceTemplate()<br>- {<br>- IO (Decode16, 0x60, 0x60, 0x01, 0x01)<br>- IO (Decode16, 0x64, 0x64, 0x01, 0x01)<br>- IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1<br>- })<br>-<br>- Method (_STA, 0)<br>- {<br>- Return (0xf)<br>- }<br>- }<br>-<br>- Device (PS2M) // Mouse<br>- {<br>- Name(_HID, EISAID("PNP0F13"))<br>- Name(_CRS, ResourceTemplate()<br>- {<br>- IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12<br>- })<br>-<br>- Method(_STA, 0)<br>- {<br>- Return (0xf)<br>- }<br>- }<br>-<br>- Device (FDC0) // Floppy controller<br>- {<br>- Name (_HID, EisaId ("PNP0700"))<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- Return (0x0f) // FIXME<br>- }<br>-<br>- Name(_CRS, ResourceTemplate()<br>- {<br>- IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)<br>- IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)<br>- IRQNoFlags () {6}<br>- DMA (Compatibility, NotBusMaster, Transfer8) {2}<br>- })<br>-<br>- Name(_PRS, ResourceTemplate()<br>- {<br>- IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)<br>- IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)<br>- IRQNoFlags () {6}<br>- DMA (Compatibility, NotBusMaster, Transfer8) {2}<br>- })<br>-<br>- }<br>-}<br>diff --git a/src/soc/intel/sch/acpi/pata.asl b/src/soc/intel/sch/acpi/pata.asl<br>deleted file mode 100644<br>index 3d37b67..0000000<br>--- a/src/soc/intel/sch/acpi/pata.asl<br>+++ /dev/null<br>@@ -1,74 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-// Intel PATA Controller 0:1f.1<br>-<br>-Device (PATA)<br>-{<br>- Name (_ADR, 0x001f0001)<br>-<br>- Device (PRID)<br>- {<br>- Name (_ADR, 0)<br>-<br>- // Get Timing Mode<br>- Method (_GTM)<br>- {<br>- Name(PBUF, Buffer(20) {<br>- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>- 0x00,0x00,0x00,0x00 })<br>-<br>- CreateDwordField (PBUF, 0, PIO0)<br>- CreateDwordField (PBUF, 4, DMA0)<br>- CreateDwordField (PBUF, 8, PIO1)<br>- CreateDwordField (PBUF, 12, DMA1)<br>- CreateDwordField (PBUF, 16, FLAG)<br>-<br>- // TODO fill return structure<br>-<br>- Return (PBUF)<br>- }<br>-<br>- // Set Timing Mode<br>- Method (_STM, 3)<br>- {<br>- CreateDwordField (Arg0, 0, PIO0)<br>- CreateDwordField (Arg0, 4, DMA0)<br>- CreateDwordField (Arg0, 8, PIO1)<br>- CreateDwordField (Arg0, 12, DMA1)<br>- CreateDwordField (Arg0, 16, FLAG)<br>-<br>- // TODO: Do the deed<br>- }<br>-<br>- Device (DSK0)<br>- {<br>- Name (_ADR, 0)<br>- // TODO: _RMV ?<br>- // TODO: _GTF ?<br>- }<br>-<br>- Device (DSK1)<br>- {<br>- Name (_ADR, 1)<br>-<br>- // TODO: _RMV ?<br>- // TODO: _GTF ?<br>- }<br>-<br>- }<br>-}<br>diff --git a/src/soc/intel/sch/acpi/pci.asl b/src/soc/intel/sch/acpi/pci.asl<br>deleted file mode 100644<br>index d1b0e8b..0000000<br>--- a/src/soc/intel/sch/acpi/pci.asl<br>+++ /dev/null<br>@@ -1,71 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-// Intel PCI to PCI bridge 0:1e.0<br>-<br>-Device (PCIB)<br>-{<br>- Name (_ADR, 0x001e0000)<br>-<br>- Device (SLT1)<br>- {<br>- Name (_ADR, 0x00000000)<br>- Name (_PRW, Package(){ 11, 4 })<br>- }<br>-<br>- Device (SLT2)<br>- {<br>- Name (_ADR, 0x00010000)<br>- Name (_PRW, Package(){ 11, 4 })<br>- }<br>-<br>- Device (SLT3)<br>- {<br>- Name (_ADR, 0x00020000)<br>- Name (_PRW, Package(){ 11, 4 })<br>- }<br>-<br>- Device (SLT6)<br>- {<br>- Name (_ADR, 0x00050000)<br>- Name (_PRW, Package(){ 11, 4 })<br>- }<br>-<br>- Device (LANC)<br>- {<br>- Name (_ADR, 0x00080000)<br>- Name (_PRW, Package(){ 11, 3 })<br>- }<br>-<br>- Device (LANR)<br>- {<br>- Name (_ADR, 0x00000000)<br>- Name (_PRW, Package(){ 11, 3 })<br>- }<br>-<br>- // TODO: How many slots, where?<br>-<br>- // PCI Interrupt Routing.<br>- // If PICM is set, interrupts are routed over the i8259, otherwise<br>- // over the IOAPIC. (Really? If they're above 15 they need to be routed<br>- // fixed over the IOAPIC?)<br>-<br>- Method (_PRT)<br>- {<br>- #include "acpi/southbridge_pci_irqs.asl"<br>- }<br>-<br>-}<br>diff --git a/src/soc/intel/sch/acpi/pcie.asl b/src/soc/intel/sch/acpi/pcie.asl<br>deleted file mode 100644<br>index 3c644e2..0000000<br>--- a/src/soc/intel/sch/acpi/pcie.asl<br>+++ /dev/null<br>@@ -1,179 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* Intel i82801G PCIe support */<br>-<br>-// PCI Express Ports<br>-<br>-Device (RP01)<br>-{<br>- NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation?<br>- //#include "pcie_port.asl"<br>- Method(_PRT)<br>- {<br>- If (PICM) {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, 0, 16 },<br>- Package() { 0x0000ffff, 1, 0, 17 },<br>- Package() { 0x0000ffff, 2, 0, 18 },<br>- Package() { 0x0000ffff, 3, 0, 19 }<br>- })<br>- } Else {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }<br>- })<br>-<br>- }<br>-<br>- }<br>-}<br>-<br>-Device (RP02)<br>-{<br>- NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation?<br>- //#include "pcie_port.asl"<br>- Method(_PRT)<br>- {<br>- If (PICM) {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, 0, 17 },<br>- Package() { 0x0000ffff, 1, 0, 18 },<br>- Package() { 0x0000ffff, 2, 0, 19 },<br>- Package() { 0x0000ffff, 3, 0, 16 }<br>- })<br>- } Else {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },<br>- Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },<br>- Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }<br>- })<br>-<br>- }<br>-<br>- }<br>-}<br>-<br>-<br>-Device (RP03)<br>-{<br>- NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation?<br>- //#include "pcie_port.asl"<br>- Method(_PRT)<br>- {<br>- If (PICM) {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, 0, 18 },<br>- Package() { 0x0000ffff, 1, 0, 19 },<br>- Package() { 0x0000ffff, 2, 0, 16 },<br>- Package() { 0x0000ffff, 3, 0, 17 }<br>- })<br>- } Else {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },<br>- Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },<br>- Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 }<br>- })<br>-<br>- }<br>-<br>- }<br>-}<br>-<br>-<br>-Device (RP04)<br>-{<br>- NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation?<br>- //#include "pcie_port.asl"<br>- Method(_PRT)<br>- {<br>- If (PICM) {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, 0, 19 },<br>- Package() { 0x0000ffff, 1, 0, 16 },<br>- Package() { 0x0000ffff, 2, 0, 17 },<br>- Package() { 0x0000ffff, 3, 0, 18 }<br>- })<br>- } Else {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },<br>- Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }<br>- })<br>-<br>- }<br>-<br>- }<br>-}<br>-<br>-<br>-Device (RP05)<br>-{<br>- NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation?<br>- //#include "pcie_port.asl"<br>- Method(_PRT)<br>- {<br>- If (PICM) {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, 0, 16 },<br>- Package() { 0x0000ffff, 1, 0, 17 },<br>- Package() { 0x0000ffff, 2, 0, 18 },<br>- Package() { 0x0000ffff, 3, 0, 19 }<br>- })<br>- } Else {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }<br>- })<br>-<br>- }<br>-<br>- }<br>-}<br>-<br>-<br>-Device (RP06)<br>-{<br>- NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation?<br>- //#include "pcie_port.asl"<br>- Method(_PRT)<br>- {<br>- If (PICM) {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, 0, 17 },<br>- Package() { 0x0000ffff, 1, 0, 18 },<br>- Package() { 0x0000ffff, 2, 0, 19 },<br>- Package() { 0x0000ffff, 3, 0, 16 }<br>- })<br>- } Else {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },<br>- Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },<br>- Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }<br>- })<br>-<br>- }<br>-<br>- }<br>-}<br>diff --git a/src/soc/intel/sch/acpi/peg.asl b/src/soc/intel/sch/acpi/peg.asl<br>deleted file mode 100644<br>index 227ca27..0000000<br>--- a/src/soc/intel/sch/acpi/peg.asl<br>+++ /dev/null<br>@@ -1,41 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-Device (PEGP)<br>-{<br>- Name (_ADR, 0x00010000)<br>-<br>- // PCI Interrupt Routing.<br>- Method (_PRT)<br>- {<br>- If (PICM) {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, 0, 16 },<br>- Package() { 0x0000ffff, 1, 0, 17 },<br>- Package() { 0x0000ffff, 2, 0, 18 },<br>- Package() { 0x0000ffff, 3, 0, 19 }<br>- })<br>- } Else {<br>- Return (Package() {<br>- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }<br>- })<br>- }<br>-<br>- }<br>-}<br>diff --git a/src/soc/intel/sch/acpi/sch.asl b/src/soc/intel/sch/acpi/sch.asl<br>deleted file mode 100644<br>index 9816e77..0000000<br>--- a/src/soc/intel/sch/acpi/sch.asl<br>+++ /dev/null<br>@@ -1,219 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include "hostbridge.asl"<br>-<br>-/* PCI Device Resource Consumption */<br>-Device (PDRC)<br>-{<br>- Name (_HID, EISAID("PNP0C02"))<br>- Name (_UID, 1)<br>-<br>- // This does not seem to work correctly yet - set values statically for<br>- // now.<br>-<br>- //Name (PDRS, ResourceTemplate() {<br>- // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA<br>- // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR<br>- // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR<br>- // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR<br>- // Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR<br>- // Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH<br>- //})<br>-<br>- Name (PDRS, ResourceTemplate() {<br>- Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA<br>- Memory32Fixed(ReadWrite, 0xfed14000, 0x00004000) // MCHBAR<br>- Memory32Fixed(ReadWrite, 0xfed18000, 0x00001000) // DMIBAR<br>- Memory32Fixed(ReadWrite, 0xfed19000, 0x00001000) // EPBAR<br>- Memory32Fixed(ReadWrite, 0xf0000000, 0x04000000) // PCIE BAR<br>- Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH<br>- Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH<br>- Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH<br>- })<br>-<br>- // Current Resource Settings<br>- Method (_CRS, 0, Serialized)<br>- {<br>- //CreateDwordField(PDRS, ^RCRB._BAS, RBR0)<br>- //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)<br>-<br>- //CreateDwordField(PDRS, ^MCHB._BAS, MBR0)<br>- //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)<br>-<br>- //CreateDwordField(PDRS, ^DMIB._BAS, DBR0)<br>- //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)<br>-<br>- //CreateDwordField(PDRS, ^EGPB._BAS, EBR0)<br>- //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)<br>-<br>- //CreateDwordField(PDRS, ^PCIE._BAS, PBR0)<br>- //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)<br>-<br>- //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)<br>- //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)<br>-<br>- Return(PDRS)<br>- }<br>-}<br>-<br>-// PCIe graphics port 0:1.0<br>-#include "peg.asl"<br>-<br>-// Integrated graphics 0:2.0<br>-#include "igd.asl"<br>-<br>-/* Intel PCH support */<br>-<br>-Scope(\)<br>-{<br>- // IO-Trap at 0x800. This is the ACPI->SMI communication interface.<br>-<br>- OperationRegion(IO_T, SystemIO, 0x800, 0x10)<br>- Field(IO_T, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset(0x8),<br>- TRP0, 8 // IO-Trap at 0x808<br>- }<br>-<br>- // ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)<br>- // this doesn't work as ACPI initializes regions and packages first, devices second.<br>- // use dynamic operation region? if so, how? XXX<br>- //OperationRegion(PMIO, SystemIO, And(\_SB_.PCI0.LPCB.PMBS, 0xfffc), 0x80)<br>- OperationRegion(PMIO, SystemIO, 0x500, 0x80)<br>- Field(PMIO, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset(0x42), // General Purpose Control<br>- , 1, // skip 1 bit<br>- GPEC, 1, // TCO status<br>- , 9, // skip 9 more bits<br>- SCIS, 1, // TCO DMI status<br>- , 6 // To the end of the word<br>- }<br>-<br>- // ICH7 GPIO IO mapped registers (0x1f.0 reg 0x48.l)<br>- OperationRegion(GPIO, SystemIO, 0x1180, 0x3c)<br>- Field(GPIO, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset(0x00), // GPIO Use Select<br>- GU00, 8,<br>- GU01, 8,<br>- GU02, 8,<br>- GU03, 8,<br>- Offset(0x04), // GPIO IO Select<br>- GIO0, 8,<br>- GIO1, 8,<br>- GIO2, 8,<br>- GIO3, 8,<br>- Offset(0x0c), // GPIO Level<br>- GL00, 8,<br>- GL01, 8,<br>- , 3,<br>- GP27, 1, // SATA_PWR_EN #0<br>- GP28, 1, // SATA_PWR_EN #1<br>- , 3,<br>- Offset(0x18), // GPIO Blink<br>- GB00, 8,<br>- GB01, 8,<br>- GB02, 8,<br>- GB03, 8,<br>- Offset(0x2c), // GPIO Invert<br>- GIV0, 8,<br>- GIV1, 8,<br>- GIV2, 8,<br>- GIV3, 8,<br>- Offset(0x30), // GPIO Use Select 2<br>- GU04, 8,<br>- GU05, 8,<br>- GU06, 8,<br>- GU07, 8,<br>- Offset(0x34), // GPIO IO Select 2<br>- GIO4, 8,<br>- GIO5, 8,<br>- GIO6, 8,<br>- GIO7, 8,<br>- Offset(0x38), // GPIO Level 2<br>- , 5,<br>- GP37, 1, // PATA_PWR_EN<br>- GP38, 1, // Battery / Power (?)<br>- GP39, 1, // ??<br>- GL05, 8,<br>- GL06, 8,<br>- GL07, 8<br>- }<br>-<br>-<br>- // ICH7 Root Complex Register Block. Memory Mapped through RCBA)<br>- OperationRegion(RCRB, SystemMemory, 0xfed1c000, 0x4000)<br>- Field(RCRB, DWordAcc, Lock, Preserve)<br>- {<br>- Offset(0x0000), // Backbone<br>- Offset(0x1000), // Chipset<br>- Offset(0x3000), // Legacy Configuration Registers<br>- Offset(0x3404), // High Performance Timer Configuration<br>- HPAS, 2, // Address Select<br>- , 5,<br>- HPTE, 1, // Address Enable<br>- Offset(0x3418), // FD (Function Disable)<br>- , 1, // Reserved<br>- PATD, 1, // PATA disable<br>- SATD, 1, // SATA disable<br>- SMBD, 1, // SMBUS disable<br>- HDAD, 1, // Azalia disable<br>- A97D, 1, // AC'97 disable<br>- M97D, 1, // AC'97 disable<br>- ILND, 1, // Internal LAN disable<br>- US1D, 1, // UHCI #1 disable<br>- US2D, 1, // UHCI #2 disable<br>- US3D, 1, // UHCI #3 disable<br>- US4D, 1, // UHCI #4 disable<br>- , 2, // Reserved<br>- LPBD, 1, // LPC bridge disable<br>- EHCD, 1, // EHCI disable<br>- Offset(0x341a), // FD Root Ports<br>- RP1D, 1, // Root Port 1 disable<br>- RP2D, 1, // Root Port 2 disable<br>- RP3D, 1, // Root Port 3 disable<br>- RP4D, 1, // Root Port 4 disable<br>- RP5D, 1, // Root Port 5 disable<br>- RP6D, 1 // Root Port 6 disable<br>- }<br>-<br>-}<br>-<br>-// 0:1b.0 High Definition Audio (Azalia)<br>-#include "audio.asl"<br>-<br>-// PCI Express Ports<br>-#include "pcie.asl"<br>-<br>-// USB<br>-#include "usb.asl"<br>-<br>-// PCI Bridge<br>-#include "pci.asl"<br>-<br>-// AC97 Audio and Modem<br>-#include "ac97.asl"<br>-<br>-// LPC Bridge<br>-#include "lpc.asl"<br>-<br>-// PATA<br>-#include "pata.asl"<br>-<br>-// SMBus<br>-#include "smbus.asl"<br>diff --git a/src/soc/intel/sch/acpi/sleepstates.asl b/src/soc/intel/sch/acpi/sleepstates.asl<br>deleted file mode 100644<br>index c05835a..0000000<br>--- a/src/soc/intel/sch/acpi/sleepstates.asl<br>+++ /dev/null<br>@@ -1,21 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-Name(\_S0, Package(4){0x0,0x0,0,0})<br>-Name(\_S1, Package(4){0x1,0x0,0,0})<br>-Name(\_S3, Package(4){0x5,0x0,0,0})<br>-Name(\_S4, Package(4){0x6,0x0,0,0})<br>-Name(\_S5, Package(4){0x7,0x0,0,0})<br>diff --git a/src/soc/intel/sch/acpi/smbus.asl b/src/soc/intel/sch/acpi/smbus.asl<br>deleted file mode 100644<br>index 3354b03..0000000<br>--- a/src/soc/intel/sch/acpi/smbus.asl<br>+++ /dev/null<br>@@ -1,240 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-// Intel SMBus Controller 0:1f.3<br>-<br>-Device (SBUS)<br>-{<br>- Name (_ADR, 0x001f0003)<br>-<br>- OperationRegion (SMBP, PCI_Config, 0x00, 0x100)<br>- Field(SMBP, DWordAcc, NoLock, Preserve)<br>- {<br>- Offset(0x40),<br>- , 2,<br>- I2CE, 1<br>- }<br>-<br>- /*<br>- OperationRegion (SMBI, SystemIO, 0x400, 0x20)<br>- Field (SMBI, ByteAcc, NoLock, Preserve)<br>- {<br>- HSTS, 8, // Host Status<br>- , 8,<br>- HCNT, 8, // Host Control<br>- HCMD, 8, // Host Command<br>- TXSA, 8, // Transmit Slave Address<br>- DAT0, 8, // Host Data 0<br>- DAT1, 8, // Host Data 1<br>- HBDB, 8, // Host Block Data Byte<br>- PECK, 8, // Packet Error Check<br>- RXSA, 8, // Receive Slave Address<br>- RXDA, 16, // Receive Slave Data<br>- AUXS, 8, // Auxiliary Status<br>- AUXC, 8, // Auxiliary Control<br>- SLPC, 8, // SMLink Pin Control<br>- SBPC, 8, // SMBus Pin Control<br>- SSTS, 8, // Slave Status<br>- SCMD, 8, // Slave Command<br>- NADR, 8, // Notify Device Address<br>- NDLB, 8, // Notify Data Low Byte<br>- NDLH, 8, // Notify Data High Byte<br>- }<br>-<br>- // Kill all SMBus communication<br>- Method (KILL, 0, Serialized)<br>- {<br>- Or (HCNT, 0x02, HCNT) // Send Kill<br>- Or (HSTS, 0xff, HSTS) // Clean Status<br>- }<br>-<br>- // Check if last operation completed<br>- // return Failure = 0, Success = 1<br>- Method (CMPL, 0, Serialized)<br>- {<br>- Store (4000, Local0) // Timeout 200ms in 50us steps<br>- While (Local0) {<br>- If (And(HSTS, 0x02)) { // Completion Status?<br>- Return (1) // Operation Completed<br>- } Else {<br>- Stall (50)<br>- Decrement (Local0)<br>- If (LEqual(Local0, 0)) {<br>- KILL()<br>- }<br>- }<br>- }<br>-<br>- Return (0) // Failure<br>- }<br>-<br>-<br>- // Wait for SMBus to become ready<br>- Method (SRDY, 0, Serialized)<br>- {<br>- Store (200, Local0) // Timeout 200ms<br>- While (Local0) {<br>- If (And(HSTS, 0x40)) { // IN_USE?<br>- Sleep(1) // Wait 1ms<br>- Decrement(Local0) // timeout--<br>- If (LEqual(Local0, 0)) {<br>- Return (1)<br>- }<br>- } Else {<br>- Store (0, Local0) // We're ready<br>- }<br>- }<br>-<br>- Store (4000, Local0) // Timeout 200ms (50us * 4000)<br>- While (Local0) {<br>- If (And (HSTS, 0x01)) { // Host Busy?<br>- Stall(50) // Wait 50us<br>- Decrement(Local0) // timeout--<br>- If (LEqual(Local0, 0)) {<br>- KILL()<br>- }<br>- } Else {<br>- Return (0) // Success<br>- }<br>- }<br>-<br>- Return (1) // Failure<br>- }<br>-<br>- // SMBus Send Byte<br>- // Arg0: Address<br>- // Arg1: Data<br>- // Return: 1 = Success, 0=Failure<br>-<br>- Method (SSXB, 2, Serialized)<br>- {<br>-<br>- // Is the SMBus Controller Ready?<br>- If (SRDY()) {<br>- Return (0)<br>- }<br>-<br>- // Send Byte<br>- Store (0, I2CE) // SMBus Enable<br>- Store (0xbf, HSTS)<br>- Store (Arg0, TXSA) // Write Address<br>- Store (Arg1, HCMD) // Write Data<br>-<br>- Store (0x48, HCNT) // Start + Byte Data Protocol<br>-<br>- If (CMPL()) {<br>- Or (HSTS, 0xff, HSTS) // Clean up<br>- Return (1) // Success<br>- }<br>-<br>- Return (0)<br>- }<br>-<br>-<br>- // SMBus Receive Byte<br>- // Arg0: Address<br>- // Return: 0xffff = Failure, Data (8bit) = Success<br>-<br>- Method (SRXB, 2, Serialized)<br>- {<br>-<br>- // Is the SMBus Controller Ready?<br>- If (SRDY()) {<br>- Return (0xffff)<br>- }<br>-<br>- // Receive Byte<br>- Store (0, I2CE) // SMBus Enable<br>- Store (0xbf, HSTS)<br>- Store (Or (Arg0, 1), TXSA) // Write Address<br>-<br>- Store (0x44, HCNT) // Start<br>-<br>- If (CMPL()) {<br>- Or (HSTS, 0xff, HSTS) // Clean up<br>- Return (DAT0) // Success<br>- }<br>-<br>- Return (0xffff)<br>- }<br>-<br>-<br>- // SMBus Write Byte<br>- // Arg0: Address<br>- // Arg1: Command<br>- // Arg2: Data<br>- // Return: 1 = Success, 0=Failure<br>-<br>- Method (SWRB, 3, Serialized)<br>- {<br>-<br>- // Is the SMBus Controller Ready?<br>- If (SRDY()) {<br>- Return (0)<br>- }<br>-<br>- // Send Byte<br>- Store (0, I2CE) // SMBus Enable<br>- Store (0xbf, HSTS)<br>- Store (Arg0, TXSA) // Write Address<br>- Store (Arg1, HCMD) // Write Command<br>- Store (Arg2, DAT0) // Write Data<br>-<br>- Store (0x48, HCNT) // Start + Byte Protocol<br>-<br>- If (CMPL()) {<br>- Or (HSTS, 0xff, HSTS) // Clean up<br>- Return (1) // Success<br>- }<br>-<br>- Return (0)<br>- }<br>-<br>-<br>- // SMBus Read Byte<br>- // Arg0: Address<br>- // Arg1: Command<br>- // Return: 0xffff = Failure, Data (8bit) = Success<br>-<br>- Method (SRDB, 2, Serialized)<br>- {<br>-<br>- // Is the SMBus Controller Ready?<br>- If (SRDY()) {<br>- Return (0xffff)<br>- }<br>-<br>- // Receive Byte<br>- Store (0, I2CE) // SMBus Enable<br>- Store (0xbf, HSTS)<br>- Store (Or (Arg0, 1), TXSA) // Write Address<br>- Store (Arg1, HCMD) // Command<br>-<br>- Store (0x48, HCNT) // Start<br>-<br>- If (CMPL()) {<br>- Or (HSTS, 0xff, HSTS) // Clean up<br>- Return (DAT0) // Success<br>- }<br>-<br>- Return (0xffff)<br>- }<br>- */<br>-<br>- // Todo: Does anyone ever use these?<br>- // Missing: Read / Write Word<br>- // Missing: Read / Write Block<br>-}<br>diff --git a/src/soc/intel/sch/acpi/usb.asl b/src/soc/intel/sch/acpi/usb.asl<br>deleted file mode 100644<br>index fc5f07c..0000000<br>--- a/src/soc/intel/sch/acpi/usb.asl<br>+++ /dev/null<br>@@ -1,210 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* Intel i82801G USB support */<br>-<br>-// USB Controller 0:1d.0<br>-<br>-Device (USB1)<br>-{<br>- Name(_ADR, 0x001d0000)<br>-<br>- OperationRegion(U01P, PCI_Config, 0, 256)<br>- Field(U01P, DWordAcc, NoLock, Preserve)<br>- {<br>- Offset(0xc4),<br>- U1WE, 2 // USB Wake Enable<br>- }<br>-<br>- Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake<br>-<br>- Method (_PSW, 1) // Power State Wake method<br>- {<br>- // USB Controller can wake OS from Sleep State<br>- If (Arg0) {<br>- Store (3, U1WE)<br>- } Else {<br>- Store (0, U1WE)<br>- }<br>- }<br>-<br>- // Leave USB ports on for to allow Wake from USB<br>-<br>- Method(_S3D,0) // Highest D State in S3 State<br>- {<br>- Return (2)<br>- }<br>-<br>- Method(_S4D,0) // Highest D State in S4 State<br>- {<br>- Return (2)<br>- }<br>-}<br>-<br>-<br>-// USB Controller 0:1d.1<br>-<br>-Device (USB2)<br>-{<br>- Name(_ADR, 0x001d0001)<br>-<br>- OperationRegion(U02P, PCI_Config, 0, 256)<br>- Field(U02P, DWordAcc, NoLock, Preserve)<br>- {<br>- Offset(0xc4),<br>- U2WE, 2 // USB Wake Enable<br>- }<br>-<br>- Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake<br>-<br>- Method (_PSW, 1) // Power State Wake method<br>- {<br>- // USB Controller can wake OS from Sleep State<br>- If (Arg0) {<br>- Store (3, U2WE)<br>- } Else {<br>- Store (0, U2WE)<br>- }<br>- }<br>-<br>- // Leave USB ports on for to allow Wake from USB<br>-<br>- Method(_S3D,0) // Highest D State in S3 State<br>- {<br>- Return (2)<br>- }<br>-<br>- Method(_S4D,0) // Highest D State in S4 State<br>- {<br>- Return (2)<br>- }<br>-<br>-}<br>-<br>-<br>-// USB Controller 0:1d.2<br>-<br>-Device (USB3)<br>-{<br>- Name(_ADR, 0x001d0002)<br>-<br>- OperationRegion(U03P, PCI_Config, 0, 256)<br>- Field(U03P, DWordAcc, NoLock, Preserve)<br>- {<br>- Offset(0xc4),<br>- U3WE, 2 // USB Wake Enable<br>- }<br>-<br>- Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake<br>-<br>- Method (_PSW, 1) // Power State Wake method<br>- {<br>- // USB Controller can wake OS from Sleep State<br>- If (Arg0) {<br>- Store (3, U3WE)<br>- } Else {<br>- Store (0, U3WE)<br>- }<br>- }<br>-<br>- // Leave USB ports on for to allow Wake from USB<br>-<br>- Method(_S3D,0) // Highest D State in S3 State<br>- {<br>- Return (2)<br>- }<br>-<br>- Method(_S4D,0) // Highest D State in S4 State<br>- {<br>- Return (2)<br>- }<br>-<br>-}<br>-<br>-<br>-// USB Controller 0:1d.3<br>-<br>-Device (USB4)<br>-{<br>- Name(_ADR, 0x001d0003)<br>-<br>- OperationRegion(U04P, PCI_Config, 0, 256)<br>- Field(U04P, DWordAcc, NoLock, Preserve)<br>- {<br>- Offset(0xc4),<br>- U4WE, 2 // USB Wake Enable<br>- }<br>-<br>- Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake<br>-<br>- Method (_PSW, 1) // Power State Wake method<br>- {<br>- // USB Controller can wake OS from Sleep State<br>- If (Arg0) {<br>- Store (3, U4WE)<br>- } Else {<br>- Store (0, U4WE)<br>- }<br>- }<br>-<br>- // Leave USB ports on for to allow Wake from USB<br>-<br>- Method(_S3D,0) // Highest D State in S3 State<br>- {<br>- Return (2)<br>- }<br>-<br>- Method(_S4D,0) // Highest D State in S4 State<br>- {<br>- Return (2)<br>- }<br>-<br>-}<br>-<br>-<br>-// EHCI Controller 0:1d.7<br>-<br>-Device (EHC1)<br>-{<br>- Name(_ADR, 0x001d0007)<br>-<br>- Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake<br>-<br>- // Leave USB ports on for to allow Wake from USB<br>-<br>- Method(_S3D,0) // Highest D State in S3 State<br>- {<br>- Return (2)<br>- }<br>-<br>- Method(_S4D,0) // Highest D State in S4 State<br>- {<br>- Return (2)<br>- }<br>-<br>- Device (HUB7)<br>- {<br>- Name (_ADR, 0x00000000)<br>-<br>- // How many are there?<br>- Device (PRT1) { Name (_ADR, 1) } // USB Port 0<br>- Device (PRT2) { Name (_ADR, 2) } // USB Port 1<br>- Device (PRT3) { Name (_ADR, 3) } // USB Port 2<br>- Device (PRT4) { Name (_ADR, 4) } // USB Port 3<br>- Device (PRT5) { Name (_ADR, 5) } // USB Port 4<br>- Device (PRT6) { Name (_ADR, 6) } // USB Port 5<br>- }<br>-}<br>diff --git a/src/soc/intel/sch/audio.c b/src/soc/intel/sch/audio.c<br>deleted file mode 100644<br>index 765d8de..0000000<br>--- a/src/soc/intel/sch/audio.c<br>+++ /dev/null<br>@@ -1,312 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Advanced Micro Devices, Inc.<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/azalia_device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <arch/io.h><br>-#include <delay.h><br>-<br>-#define HDA_ICII_REG 0x68<br>-#define HDA_ICII_BUSY (1 << 0)<br>-#define HDA_ICII_VALID (1 << 1)<br>-<br>-typedef struct southbridge_intel_sch_config config_t;<br>-<br>-static int set_bits(void *port, u32 mask, u32 val)<br>-{<br>- u32 reg32;<br>- int count;<br>-<br>- /* Write (val & mask) to port */<br>- val &= mask;<br>- reg32 = read32(port);<br>- reg32 &= ~mask;<br>- reg32 |= val;<br>- write32(port, reg32);<br>-<br>- /* Wait for readback of register to<br>- * match what was just written to it<br>- */<br>- count = 50;<br>- do {<br>- /* Wait 1ms based on BKDG wait time */<br>- mdelay(1);<br>- reg32 = read32(port);<br>- reg32 &= mask;<br>- } while ((reg32 != val) && --count);<br>-<br>- /* Timeout occurred */<br>- if (!count)<br>- return -1;<br>- return 0;<br>-}<br>-<br>-static int codec_detect(u8 *base)<br>-{<br>- u32 reg32;<br>- int count;<br>-<br>- /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */<br>- if (set_bits(base + 0x08, 1, 1) == -1)<br>- goto no_codec;<br>-<br>- /* clear STATESTS bits (BAR + 0xE)[2:0] */<br>- reg32 = read32(base + 0x0E);<br>- reg32 |= 7;<br>- write32(base + 0x0E, reg32);<br>-<br>- /* Wait for readback of register to<br>- * match what was just written to it<br>- */<br>- count = 50;<br>- do {<br>- /* Wait 1ms based on BKDG wait time */<br>- mdelay(1);<br>- reg32 = read32(base + 0x0E);<br>- } while ((reg32 != 0) && --count);<br>- /* Timeout occurred */<br>- if (!count)<br>- goto no_codec;<br>-<br>- /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */<br>- if (set_bits(base + 0x08, 1, 0) == -1)<br>- goto no_codec;<br>-<br>- /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */<br>- if (set_bits(base + 0x08, 1, 1) == -1)<br>- goto no_codec;<br>-<br>- /* Read in Codec location (BAR + 0xe)[2..0] */<br>- reg32 = read32(base + 0xe);<br>- reg32 &= 0x0f;<br>- if (!reg32)<br>- goto no_codec;<br>-<br>- return reg32;<br>-<br>-no_codec:<br>- /* Codec Not found */<br>- /* Put HDA back in reset (BAR + 0x8) [0] */<br>- set_bits(base + 0x08, 1, 0);<br>- printk(BIOS_DEBUG, "sch_audio: No codec!\n");<br>- return 0;<br>-}<br>-<br>-static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)<br>-{<br>- printk(BIOS_DEBUG, "sch_audio: dev=%s\n", dev_path(dev));<br>- printk(BIOS_DEBUG, "sch_audio: Reading viddid=%x\n", viddid);<br>-<br>- int idx = 0;<br>-<br>- while (idx < (cim_verb_data_size / sizeof(u32))) {<br>- u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32<br>- verb_size++; // we ship an additional gain value<br>- if (cim_verb_data[idx] != viddid) {<br>- idx += verb_size + 3; // skip verb + header<br>- continue;<br>- }<br>- *verb = &cim_verb_data[idx + 3];<br>- return verb_size;<br>- }<br>-<br>- /* Not all codecs need to load another verb */<br>- return 0;<br>-}<br>-<br>-/**<br>- * Wait 50usec for the codec to indicate it is ready<br>- * no response would imply that the codec is non-operative<br>- */<br>-<br>-static int wait_for_ready(u8 *base)<br>-{<br>- /* Use a 50 usec timeout - the Linux kernel uses the<br>- * same duration */<br>-<br>- int timeout = 50;<br>-<br>- while (timeout--) {<br>- u32 reg32 = read32(base + HDA_ICII_REG);<br>- if (!(reg32 & HDA_ICII_BUSY))<br>- return 0;<br>- udelay(1);<br>- }<br>-<br>- return -1;<br>-}<br>-<br>-/**<br>- * Wait 50usec for the codec to indicate that it accepted<br>- * the previous command. No response would imply that the code<br>- * is non-operative<br>- */<br>-<br>-static int wait_for_valid(u8 *base)<br>-{<br>- /* Use a 50 usec timeout - the Linux kernel uses the<br>- * same duration */<br>-<br>- int timeout = 25;<br>-<br>- write32(base + 0x68, 1);<br>- while (timeout--) {<br>- udelay(1);<br>- }<br>- timeout = 50;<br>- while (timeout--) {<br>- u32 reg32 = read32(base + 0x68);<br>- if ((reg32 & ((1 << 1) | (1 << 0))) == (1 << 1)) {<br>-<br>- write32(base + 0x68, 2);<br>- return 0;<br>- }<br>- udelay(1);<br>- }<br>-<br>- return -1;<br>-}<br>-<br>-static void codec_init(struct device *dev, u8 *base, int addr)<br>-{<br>- u32 reg32;<br>- const u32 *verb;<br>- u32 verb_size;<br>- int i;<br>-<br>- printk(BIOS_DEBUG, "sch_audio: Initializing codec #%d\n", addr);<br>-<br>- /* 1 */<br>- if (wait_for_ready(base) == -1)<br>- return;<br>-<br>- reg32 = (addr << 28) | 0x000f0000;<br>- write32(base + 0x60, reg32);<br>-<br>- if (wait_for_valid(base) == -1)<br>- return;<br>-<br>- reg32 = read32(base + 0x0);<br>- printk(BIOS_DEBUG, "sch_audio: GCAP: %08x\n", reg32);<br>-<br>- reg32 = read32(base + 0x4);<br>- printk(BIOS_DEBUG, "sch_audio: OUTPAY: %08x\n", reg32);<br>- reg32 = read32(base + 0x6);<br>- printk(BIOS_DEBUG, "sch_audio: INPAY: %08x\n", reg32);<br>-<br>- reg32 = read32(base + 0x64);<br>-<br>- /* 2 */<br>- printk(BIOS_DEBUG, "sch_audio: codec viddid: %08x\n", reg32);<br>- verb_size = find_verb(dev, reg32, &verb);<br>-<br>- if (!verb_size) {<br>- printk(BIOS_DEBUG, "sch_audio: No verb!\n");<br>- return;<br>- }<br>- printk(BIOS_DEBUG, "sch_audio: verb_size: %d\n", verb_size);<br>-<br>- /* 3 */<br>- for (i = 0; i < verb_size; i++) {<br>- if (wait_for_ready(base) == -1)<br>- return;<br>-<br>- write32(base + 0x60, verb[i]);<br>-<br>- if (wait_for_valid(base) == -1)<br>- return;<br>- }<br>- printk(BIOS_DEBUG, "sch_audio: verb loaded.\n");<br>-}<br>-<br>-static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)<br>-{<br>- int i;<br>-<br>- for (i = 2; i >= 0; i--) {<br>- if (codec_mask & (1 << i))<br>- codec_init(dev, base, i);<br>- }<br>-}<br>-<br>-static void sch_audio_init(struct device *dev)<br>-{<br>- u8 *base;<br>- struct resource *res;<br>- u32 codec_mask;<br>- u32 reg32;<br>-<br>- res = find_resource(dev, 0x10);<br>- if (!res)<br>- return;<br>-<br>- reg32 = pci_read_config32(dev, PCI_COMMAND);<br>- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MEMORY);<br>-<br>- // NOTE this will break as soon as the sch_audio get's a bar above<br>- // 4G. Is there anything we can do about it?<br>- base = res2mmio(res, 0, 0);<br>- printk(BIOS_DEBUG, "sch_audio: base = %px\n", base);<br>- codec_mask = codec_detect(base);<br>-<br>- if (codec_mask) {<br>- printk(BIOS_DEBUG, "sch_audio: codec_mask = %02x\n",<br>- codec_mask);<br>- codecs_init(dev, base, codec_mask);<br>- } else {<br>- /* No audio codecs found disable HD audio controller */<br>- pci_write_config32(dev, 0x10, 0);<br>- pci_write_config32(dev, PCI_COMMAND, 0);<br>- reg32 = pci_read_config32(dev, 0xFC);<br>- pci_write_config32(dev, 0xFC, reg32 | 1);<br>- }<br>-}<br>-<br>-static void sch_audio_set_subsystem(device_t dev, unsigned vendor,<br>- unsigned device)<br>-{<br>- if (!vendor || !device) {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- pci_read_config32(dev, PCI_VENDOR_ID));<br>- } else {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- }<br>-}<br>-<br>-static struct pci_operations sch_audio_pci_ops = {<br>- .set_subsystem = sch_audio_set_subsystem,<br>-};<br>-<br>-static struct device_operations sch_audio_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = sch_audio_init,<br>- .scan_bus = 0,<br>- .ops_pci = &sch_audio_pci_ops,<br>-};<br>-<br>-/* SCH audio function */<br>-static const struct pci_driver sch_audio __pci_driver = {<br>- .ops = &sch_audio_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x811B,<br>-};<br>diff --git a/src/soc/intel/sch/bootblock.c b/src/soc/intel/sch/bootblock.c<br>deleted file mode 100644<br>index deff35e..0000000<br>--- a/src/soc/intel/sch/bootblock.c<br>+++ /dev/null<br>@@ -1,38 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-<br>-/* Copy the bare minimum from port_access.c to enable MMCONF. */<br>-<br>-#define MSG_OPCODE_READ 0xD0000000<br>-#define MSG_OPCODE_WRITE 0xE0000000<br>-<br>-#define MCR 0xD0<br>-#define MDR 0xD4<br>-<br>-static void sch_port_access_write(int port, int reg, int bytes, long data)<br>-{<br>- pci_io_write_config32(PCI_DEV(0, 0, 0), MDR, data);<br>- pci_io_write_config32(PCI_DEV(0, 0, 0), MCR,<br>- (MSG_OPCODE_WRITE | (port << 16) | (reg << 8)));<br>- pci_io_read_config32(PCI_DEV(0, 0, 0), MDR);<br>-}<br>-<br>-static void bootblock_northbridge_init(void)<br>-{<br>- /* Enable PCI MMCONF decoding BAR. */<br>- sch_port_access_write(0, 0, 4, DEFAULT_PCIEXBAR | 1); /* pre-b1 */<br>- sch_port_access_write(2, 9, 4, DEFAULT_PCIEXBAR | 1); /* b1+ */<br>-}<br>diff --git a/src/soc/intel/sch/chip.h b/src/soc/intel/sch/chip.h<br>deleted file mode 100644<br>index 27d7c73..0000000<br>--- a/src/soc/intel/sch/chip.h<br>+++ /dev/null<br>@@ -1,39 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2008 coresystems GmbH<br>- * 2012 secunet Security Networks AG<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef SOC_INTEL_SCH_CHIP_H<br>-#define SOC_INTEL_SCH_CHIP_H<br>-<br>-#include <drivers/intel/gma/i915.h><br>-<br>-struct soc_intel_sch_config {<br>- struct i915_gpu_controller_info gfx;<br>-<br>- /**<br>- * Interrupt Routing configuration<br>- * If bit7 is 1, the interrupt is disabled.<br>- */<br>- uint8_t pirqa_routing;<br>- uint8_t pirqb_routing;<br>- uint8_t pirqc_routing;<br>- uint8_t pirqd_routing;<br>- uint8_t pirqe_routing;<br>- uint8_t pirqf_routing;<br>- uint8_t pirqg_routing;<br>- uint8_t pirqh_routing;<br>-};<br>-<br>-#endif /* SOC_INTEL_SCH_CHIP_H */<br>diff --git a/src/soc/intel/sch/early_init.c b/src/soc/intel/sch/early_init.c<br>deleted file mode 100644<br>index cd77776..0000000<br>--- a/src/soc/intel/sch/early_init.c<br>+++ /dev/null<br>@@ -1,213 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include "sch.h"<br>-<br>-#if 0<br>-static void sch_set_mtrr(void)<br>-{<br>- msr_t msr;<br>- printk(BIOS_DEBUG, "1");<br>- msr.hi = 0x06060606;<br>- msr.lo = 0x06060606;<br>- wrmsr(0x250, msr);<br>- printk(BIOS_DEBUG, "2");<br>- msr.hi = 0x06060606;<br>- msr.lo = 0x06060606;<br>- wrmsr(0x258, msr);<br>- printk(BIOS_DEBUG, "3");<br>- msr.hi = 0x0;<br>- msr.lo = 0x0;<br>- wrmsr(0x259, msr);<br>- printk(BIOS_DEBUG, "4");<br>- msr.hi = 0x04040404;<br>- msr.lo = 0x04040404;<br>- wrmsr(0x268, msr);<br>- printk(BIOS_DEBUG, "5");<br>- msr.hi = 0x04040404;<br>- msr.lo = 0x04040404;<br>- wrmsr(0x269, msr);<br>- printk(BIOS_DEBUG, "6");<br>- msr.hi = 0x04040404;<br>- msr.lo = 0x04040404;<br>- wrmsr(0x26A, msr);<br>- printk(BIOS_DEBUG, "7");<br>- msr.hi = 0x04040404;<br>- msr.lo = 0x04040404;<br>- wrmsr(0x26B, msr);<br>- printk(BIOS_DEBUG, "8");<br>- msr.hi = 0x04040404;<br>- msr.lo = 0x04040404;<br>- wrmsr(0x26C, msr);<br>- printk(BIOS_DEBUG, "9");<br>- msr.hi = 0x05050505;<br>- msr.lo = 0x05050505;<br>- wrmsr(0x26D, msr);<br>- printk(BIOS_DEBUG, "10");<br>- msr.hi = 0x05050505;<br>- msr.lo = 0x05050505;<br>- wrmsr(0x26E, msr);<br>- printk(BIOS_DEBUG, "11");<br>- msr.hi = 0x05050505;<br>- msr.lo = 0x05050505;<br>- wrmsr(0x26f, msr);<br>- printk(BIOS_DEBUG, "12");<br>- msr.hi = 0x0;<br>- msr.lo = 0x6;<br>- wrmsr(0x202, msr);<br>- printk(BIOS_DEBUG, "13");<br>- msr.hi = 0x0;<br>- msr.lo = 0xC0000800;<br>- wrmsr(0x203, msr);<br>- printk(BIOS_DEBUG, "14");<br>- msr.hi = 0x0;<br>- msr.lo = 0x3FAF0000;<br>- wrmsr(0x204, msr);<br>- printk(BIOS_DEBUG, "15");<br>- msr.hi = 0x0;<br>- msr.lo = 0xFFFF0800;<br>- wrmsr(0x205, msr);<br>- printk(BIOS_DEBUG, "16");<br>- msr.hi = 0x0;<br>- msr.lo = 0x3FB00000;<br>- wrmsr(0x206, msr);<br>- printk(BIOS_DEBUG, "16");<br>- msr.hi = 0x0;<br>- msr.lo = 0xFFF00800;<br>- wrmsr(0x207, msr);<br>- printk(BIOS_DEBUG, "17");<br>- msr.hi = 0x0;<br>- msr.lo = 0x3FC00000;<br>- wrmsr(0x208, msr);<br>- printk(BIOS_DEBUG, "18");<br>- msr.hi = 0x0;<br>- msr.lo = 0xFFC00800;<br>- wrmsr(0x209, msr);<br>- printk(BIOS_DEBUG, "19");<br>- msr.hi = 0x0;<br>- msr.lo = 0x0;<br>- wrmsr(0x20A, msr);<br>- printk(BIOS_DEBUG, "20");<br>- msr.hi = 0x0;<br>- msr.lo = 0x0;<br>- wrmsr(0x20B, msr);<br>- printk(BIOS_DEBUG, "21");<br>- msr.hi = 0x0;<br>- msr.lo = 0x0;<br>- wrmsr(0x20a, msr);<br>- printk(BIOS_DEBUG, "22");<br>- msr.hi = 0x0;<br>- msr.lo = 0x0;<br>- wrmsr(0x20B, msr);<br>- printk(BIOS_DEBUG, "23");<br>- msr.hi = 0x0;<br>- msr.lo = 0x0;<br>- wrmsr(0x20c, msr);<br>- msr.hi = 0x0;<br>- msr.lo = 0x0;<br>- wrmsr(0x20d, msr);<br>- msr.hi = 0x0;<br>- msr.lo = 0x0;<br>- wrmsr(0x20E, msr);<br>- msr.hi = 0x0;<br>- msr.lo = 0x0;<br>- wrmsr(0x20F, msr);<br>- msr.hi = 0x0;<br>- msr.lo = 0XC00;<br>- wrmsr(0x2FF, msr);<br>- printk(BIOS_DEBUG, "end");<br>-}<br>-#endif<br>-<br>-static void sch_detect_chipset(void)<br>-{<br>- u16 reg16;<br>- u8 reg8;<br>- printk(BIOS_INFO, "\n");<br>- reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), 0x2);<br>- switch (reg16) {<br>- case 0x8101:<br>- printk(BIOS_INFO, "UL11L/US15L");<br>- break;<br>- case 0x8100:<br>- printk(BIOS_INFO, "US15W");<br>- break;<br>- default:<br>- /* Others reserved. */<br>- printk(BIOS_INFO, "Unknown (%02x)", reg16);<br>- }<br>- printk(BIOS_INFO, " Chipset ");<br>-<br>- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x8);<br>- switch (reg8) {<br>- case 3:<br>- printk(BIOS_INFO, "Qual. Sample ES1, Stepping B1");<br>- break;<br>- case 4:<br>- printk(BIOS_INFO, "Qual. Sample ES2, Stepping C0");<br>- break;<br>- case 5:<br>- printk(BIOS_INFO, "Qual. Sample ES2-Prime, Stepping D0");<br>- break;<br>- case 6:<br>- printk(BIOS_INFO, "Qual. Sample QS, Stepping D1");<br>- break;<br>- default:<br>- /* Others reserved. */<br>- printk(BIOS_INFO, "Unknown (%02x)", reg8);<br>- }<br>- printk(BIOS_INFO, "\n");<br>-}<br>-<br>-static void sch_setup_non_standard_bars(void)<br>-{<br>- printk(BIOS_DEBUG, "Setting up ACPI PM1 block ");<br>- /* Address 0x1000 size 16B */<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x48,<br>- (0x80000000 | DEFAULT_PMBASE));<br>-<br>- printk(BIOS_DEBUG, "Setting up ACPI P block ");<br>- /* Address 0x1010 size 16B */<br>- sch_port_access_write(4, 0x70, 4, 0x80001010);<br>-<br>- /* SMBus address 0x1040 size 64B */<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x40, 0x80001040);<br>-<br>- /* GPIO address 0x1080 size 64B */<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x44, 0x80001080);<br>-<br>- /* GPE0 address 0x10C0 size 64B */<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x4C, 0x800010C0);<br>-<br>- sch_port_access_write(2, 4, 4, 0x3F703F76); /* FIXME: SMM Control */<br>-<br>- /* Base of Stolen Memory Address 0x1080 size 64B */<br>- pci_write_config32(PCI_DEV(0, 0x02, 0), 0x5C, 0x3F800000);<br>-<br>- /* RCBA */<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0,<br>- ((uintptr_t)DEFAULT_RCBABASE | 1));<br>-<br>- printk(BIOS_DEBUG, " done.\n");<br>-}<br>-<br>-static void sch_early_initialization(void)<br>-{<br>- /* Print some chipset specific information. */<br>- sch_detect_chipset();<br>-<br>- /* Setup all non standard BARs. */<br>- sch_setup_non_standard_bars();<br>-}<br>diff --git a/src/soc/intel/sch/early_smbus.c b/src/soc/intel/sch/early_smbus.c<br>deleted file mode 100644<br>index 2f9cdeb..0000000<br>--- a/src/soc/intel/sch/early_smbus.c<br>+++ /dev/null<br>@@ -1,57 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <console/console.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_def.h><br>-#include "i82801gx.h"<br>-#include "smbus.h"<br>-<br>-void enable_smbus(void)<br>-{<br>- device_t dev;<br>-<br>- /* Set the SMBus device statically. */<br>- dev = PCI_DEV(0x0, 0x1f, 0x3);<br>-<br>- /* Check to make sure we've got the right device. */<br>- if (pci_read_config16(dev, 0x2) != 0x27da) {<br>- die("SMBus controller not found!");<br>- }<br>-<br>- /* Set SMBus I/O base. */<br>- pci_write_config32(dev, SMB_BASE,<br>- SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);<br>-<br>- /* Set SMBus enable. */<br>- pci_write_config8(dev, HOSTC, HST_EN);<br>-<br>- /* Set SMBus I/O space enable. */<br>- pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);<br>-<br>- /* Disable interrupt generation. */<br>- outb(0, SMBUS_IO_BASE + SMBHSTCTL);<br>-<br>- /* Clear any lingering errors, so transactions can run. */<br>- outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);<br>- printk(BIOS_DEBUG, "SMBus controller enabled.\n");<br>-}<br>-<br>-int smbus_read_byte(unsigned device, unsigned address)<br>-{<br>- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);<br>-}<br>diff --git a/src/soc/intel/sch/gma.c b/src/soc/intel/sch/gma.c<br>deleted file mode 100644<br>index 4c92444..0000000<br>--- a/src/soc/intel/sch/gma.c<br>+++ /dev/null<br>@@ -1,85 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <drivers/intel/gma/i915.h><br>-#include "chip.h"<br>-<br>-static void gma_func0_init(struct device *dev)<br>-{<br>- u32 reg32;<br>-<br>- /* IGD needs to be bus master. */<br>- reg32 = pci_read_config32(dev, PCI_COMMAND);<br>- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);<br>-<br>- pci_dev_init(dev);<br>-}<br>-<br>-static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- if (!vendor || !device) {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- pci_read_config32(dev, PCI_VENDOR_ID));<br>- } else {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- }<br>-}<br>-<br>-const struct i915_gpu_controller_info *<br>-intel_gma_get_controller_info(void)<br>-{<br>- device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));<br>- if (!dev) {<br>- return NULL;<br>- }<br>- struct soc_intel_sch_config *chip = dev->chip_info;<br>- return &chip->gfx;<br>-}<br>-<br>-static void gma_ssdt(device_t device)<br>-{<br>- const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();<br>- if (!gfx) {<br>- return;<br>- }<br>-<br>- drivers_intel_gma_displays_ssdt_generate(gfx);<br>-}<br>-<br>-static struct pci_operations gma_pci_ops = {<br>- .set_subsystem = gma_set_subsystem,<br>-};<br>-<br>-static struct device_operations gma_func0_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .acpi_fill_ssdt_generator = gma_ssdt,<br>- .init = gma_func0_init,<br>- .scan_bus = 0,<br>- .enable = 0,<br>- .ops_pci = &gma_pci_ops,<br>-};<br>-<br>-static const struct pci_driver sch_gma_func0_driver __pci_driver = {<br>- .ops = &gma_func0_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x8108,<br>-};<br>diff --git a/src/soc/intel/sch/ide.c b/src/soc/intel/sch/ide.c<br>deleted file mode 100644<br>index 56e51a5..0000000<br>--- a/src/soc/intel/sch/ide.c<br>+++ /dev/null<br>@@ -1,87 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-<br>-/* PCI Configuration Space (D31:F1): IDE */<br>-#define INTR_LN 0x3c<br>-#define IDE_TIM_PRI 0x80 /* IDE timings, primary */<br>-<br>-extern int sch_port_access_read(int port, int reg, int bytes);<br>-<br>-static void ide_init(struct device *dev)<br>-{<br>- u32 ideTimingConfig, reg32;<br>-<br>- printk(BIOS_DEBUG, "sch_ide: initializing... ");<br>-<br>- reg32 = pci_read_config32(dev, PCI_COMMAND);<br>- pci_write_config32(dev, PCI_COMMAND,<br>- reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);<br>-<br>- /* Program the clock. */<br>- if (sch_port_access_read(5, 3, 4) & (1 << 3)) {<br>- /* 533MHz, Read PCI MC register */<br>- reg32 = pci_read_config32(dev, 0x60);<br>- pci_write_config32(dev, 0x60, reg32 | 1);<br>- } else {<br>- /* 400MHz */<br>- reg32 = pci_read_config32(dev, 0x60);<br>- reg32 &= ~1;<br>- pci_write_config32(dev, 0x60, reg32);<br>- }<br>-<br>- /* Enable primary IDE interface. 80=04 81=00 82=02 83=80 */<br>- ideTimingConfig = 0x80020000;<br>- printk(BIOS_DEBUG, "IDE0 ");<br>- pci_write_config32(dev, IDE_TIM_PRI, ideTimingConfig);<br>-<br>- /* Set Interrupt Line. */<br>- /* Interrupt Pin is set by D31IP.PIP */<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- if (!vendor || !device) {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- pci_read_config32(dev, PCI_VENDOR_ID));<br>- } else {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- }<br>-}<br>-<br>-static struct pci_operations ide_pci_ops = {<br>- .set_subsystem = ide_set_subsystem,<br>-};<br>-<br>-static struct device_operations ide_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = ide_init,<br>- .scan_bus = 0,<br>- .ops_pci = &ide_pci_ops,<br>-};<br>-<br>-static const struct pci_driver sch_ide __pci_driver = {<br>- .ops = &ide_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x811A,<br>-};<br>diff --git a/src/soc/intel/sch/lpc.c b/src/soc/intel/sch/lpc.c<br>deleted file mode 100644<br>index f5e17d8..0000000<br>--- a/src/soc/intel/sch/lpc.c<br>+++ /dev/null<br>@@ -1,230 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <arch/io.h><br>-#include <arch/ioapic.h><br>-#include <arch/acpigen.h><br>-#include <arch/acpigen.h><br>-#include <cpu/cpu.h><br>-#include <cbmem.h><br>-#include <string.h><br>-#include <drivers/intel/gma/i915.h><br>-#include "nvs.h"<br>-#include "chip.h"<br>-<br>-/* SCH LPC defines */<br>-#define SCH_ACPI_CTL 0x58<br>-#define SCH_SIRQ_CTL 0x68<br>-#define PIRQA_ROUT 0x60<br>-#define PIRQB_ROUT 0x61<br>-#define PIRQC_ROUT 0x62<br>-#define PIRQD_ROUT 0x63<br>-#define PIRQE_ROUT 0x64<br>-#define PIRQF_ROUT 0x65<br>-#define PIRQG_ROUT 0x66<br>-#define PIRQH_ROUT 0x67<br>-<br>-typedef struct soc_intel_sch_config config_t;<br>-<br>-/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control<br>- * 0x00 - 0000 = Reserved<br>- * 0x01 - 0001 = Reserved<br>- * 0x02 - 0010 = Reserved<br>- * 0x03 - 0011 = IRQ3<br>- * 0x04 - 0100 = IRQ4<br>- * 0x05 - 0101 = IRQ5<br>- * 0x06 - 0110 = IRQ6<br>- * 0x07 - 0111 = IRQ7<br>- * 0x08 - 1000 = Reserved<br>- * 0x09 - 1001 = IRQ9<br>- * 0x0A - 1010 = IRQ10<br>- * 0x0B - 1011 = IRQ11<br>- * 0x0C - 1100 = IRQ12<br>- * 0x0D - 1101 = Reserved<br>- * 0x0E - 1110 = IRQ14<br>- * 0x0F - 1111 = IRQ15<br>- * PIRQ[n]_ROUT[7] - PIRQ Routing Control<br>- * 0x80 - The PIRQ is not routed.<br>- */<br>-<br>-#define PIRQA 0x03<br>-#define PIRQB 0x05<br>-#define PIRQC 0x06<br>-#define PIRQD 0x07<br>-#define PIRQE 0x09<br>-#define PIRQF 0x0A<br>-#define PIRQG 0x0B<br>-#define PIRQH 0x0C<br>-<br>-static void sch_pirq_init(device_t dev)<br>-{<br>- device_t irq_dev;<br>-<br>- /* Get the chip configuration */<br>- config_t *config = dev->chip_info;<br>-<br>- pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);<br>- pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);<br>- pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);<br>- pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);<br>-<br>- pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);<br>- pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);<br>- pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);<br>- pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);<br>-<br>- /* Eric Biederman once said we should let the OS do this.<br>- * I am not so sure anymore he was right.<br>- */<br>-<br>- for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {<br>- u8 int_pin = 0, int_line = 0;<br>-<br>- if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)<br>- continue;<br>-<br>- int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);<br>-<br>- switch (int_pin) {<br>- case 1: /* INTA# */<br>- int_line = config->pirqa_routing;<br>- break;<br>- case 2: /* INTB# */<br>- int_line = config->pirqb_routing;<br>- break;<br>- case 3: /* INTC# */<br>- int_line = config->pirqc_routing;<br>- break;<br>- case 4: /* INTD# */<br>- int_line = config->pirqd_routing;<br>- break;<br>- }<br>-<br>- if (!int_line)<br>- continue;<br>-<br>- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);<br>- }<br>-}<br>-<br>-static void sch_fixups(struct device *dev)<br>-{<br>- u32 rcba_base;<br>-<br>- /* This needs to happen after PCI enumeration. */<br>- /* RCBA32(0x1d40) |= 1; */<br>- rcba_base = pci_read_config32(dev, 0xF0);<br>-<br>- /* Remove the enable bit. */<br>- rcba_base = rcba_base >> 1;<br>- rcba_base = rcba_base << 1;<br>- *((volatile u32 *)(rcba_base +0x104)) &= 0xFF00FFFF;<br>-}<br>-<br>-static void lpc_init(struct device *dev)<br>-{<br>- printk(BIOS_DEBUG, "SCH: lpc_init\n");<br>-<br>- /* Setup the PIRQ. */<br>- sch_pirq_init(dev);<br>- pci_write_config8(dev, SCH_SIRQ_CTL,0x80);<br>- sch_fixups(dev);<br>-}<br>-<br>-static void sch_lpc_read_resources(device_t dev)<br>-{<br>- struct resource *res;<br>-<br>- /* Get the normal PCI resources of this device. */<br>- pci_dev_read_resources(dev);<br>-<br>- /* Add an extra subtractive resource for both memory and I/O. */<br>- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));<br>- res->base = 0;<br>- res->size = 0xe000;<br>- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |<br>- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-<br>- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));<br>- res->base = 0xff800000;<br>- res->size = 0x00800000; /* 8 MB for flash */<br>- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |<br>- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-<br>- res = new_resource(dev, 3);<br>- res->base = IO_APIC_ADDR;<br>- res->size = 0x00001000;<br>- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-}<br>-<br>-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- if (!vendor || !device) {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- pci_read_config32(dev, PCI_VENDOR_ID));<br>- } else {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- }<br>-}<br>-<br>-static void southbridge_inject_dsdt(device_t dev)<br>-{<br>- global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));<br>-<br>- if (gnvs) {<br>- const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();<br>- memset(gnvs, 0, sizeof(*gnvs));<br>- acpi_create_gnvs(gnvs);<br>-<br>- gnvs->ndid = gfx->ndid;<br>- memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));<br>-<br>- /* And tell SMI about it */<br>- smm_setup_structures(gnvs, NULL, NULL);<br>-<br>- /* Add it to SSDT. */<br>- acpigen_write_scope("\\");<br>- acpigen_write_name_dword("NVSA", (u32) gnvs);<br>- acpigen_pop_len();<br>- }<br>-}<br>-<br>-static struct pci_operations pci_ops = {<br>- .set_subsystem = set_subsystem,<br>-};<br>-<br>-static struct device_operations device_ops = {<br>- .read_resources = sch_lpc_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .acpi_inject_dsdt_generator = southbridge_inject_dsdt,<br>- .write_acpi_tables = acpi_write_hpet,<br>- .init = lpc_init,<br>- .scan_bus = scan_lpc_bus,<br>- .ops_pci = &pci_ops,<br>-};<br>-<br>-/* SCH LPC Interface */<br>-static const struct pci_driver sch_lpc __pci_driver = {<br>- .ops = &device_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x8119,<br>-};<br>diff --git a/src/soc/intel/sch/mmc.c b/src/soc/intel/sch/mmc.c<br>deleted file mode 100644<br>index ccc2dc1..0000000<br>--- a/src/soc/intel/sch/mmc.c<br>+++ /dev/null<br>@@ -1,76 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <arch/io.h><br>-<br>-static void sch_mmc_init(struct device *dev)<br>-{<br>- u32 reg32;<br>-<br>- printk(BIOS_DEBUG, "MMC: Setting up controller.. ");<br>- reg32 = pci_read_config32(dev, PCI_COMMAND);<br>- reg32 |= PCI_COMMAND_MASTER;<br>- reg32 |= PCI_COMMAND_MEMORY;<br>- pci_write_config32(dev, PCI_COMMAND, reg32);<br>- printk(BIOS_DEBUG, "done.\n");<br>-}<br>-<br>-static void sch_mmc_set_subsystem(device_t dev, unsigned vendor,<br>- unsigned device)<br>-{<br>- if (!vendor || !device) {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- pci_read_config32(dev, PCI_VENDOR_ID));<br>- } else {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- }<br>-}<br>-<br>-static struct pci_operations lops_pci = {<br>- .set_subsystem = &sch_mmc_set_subsystem,<br>-};<br>-<br>-static struct device_operations sch_mmc_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = sch_mmc_init,<br>- .scan_bus = 0,<br>- .ops_pci = &lops_pci,<br>-};<br>-<br>-static const struct pci_driver sch_mmc1 __pci_driver = {<br>- .ops = &sch_mmc_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x811C,<br>-};<br>-<br>-static const struct pci_driver sch_mmc2 __pci_driver = {<br>- .ops = &sch_mmc_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x811D,<br>-};<br>-<br>-static const struct pci_driver sch_mmc3 __pci_driver = {<br>- .ops = &sch_mmc_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x811E,<br>-<br>-};<br>diff --git a/src/soc/intel/sch/northbridge.c b/src/soc/intel/sch/northbridge.c<br>deleted file mode 100644<br>index 6bbce68..0000000<br>--- a/src/soc/intel/sch/northbridge.c<br>+++ /dev/null<br>@@ -1,259 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include <cbmem.h><br>-#include <cpu/cpu.h><br>-#include <arch/acpi.h><br>-#include "sch.h"<br>-<br>-static int get_pcie_bar(u32 *base)<br>-{<br>- device_t dev;<br>- u32 pciexbar_reg;<br>-<br>- dev = dev_find_slot(0, PCI_DEVFN(0, 0));<br>- if (!dev)<br>- return 0;<br>-<br>- /* FIXME: Determine at runtime. */<br>-#ifdef POULSBO_PRE_B1<br>- pciexbar_reg = sch_port_access_read(0, 0, 4);<br>-#else<br>- pciexbar_reg = sch_port_access_read(2, 9, 4);<br>-#endif<br>-<br>- if (!(pciexbar_reg & (1 << 0)))<br>- return 0;<br>-<br>- switch ((pciexbar_reg >> 1) & 3) {<br>- case 0: /* 256MB */<br>- *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |<br>- (1 << 28));<br>- return 256;<br>- case 1: /* 128M */<br>- *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |<br>- (1 << 28) | (1 << 27));<br>- return 128;<br>- case 2: /* 64M */<br>- *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |<br>- (1 << 28) | (1 << 27) | (1 << 26));<br>- return 64;<br>- }<br>-<br>- return 0;<br>-}<br>-<br>-static void add_fixed_resources(struct device *dev, int index)<br>-{<br>- struct resource *resource;<br>-<br>- printk(BIOS_DEBUG, "Adding CMC shadow area\n");<br>- resource = new_resource(dev, index++);<br>- resource->base = (resource_t) CMC_SHADOW;<br>- resource->size = (resource_t) (64 * 1024);<br>- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |<br>- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;<br>-}<br>-<br>-static void pci_domain_set_resources(device_t dev)<br>-{<br>- u32 pci_tolm;<br>- u8 reg8;<br>- u16 reg16;<br>- unsigned long long tomk, tolud, tomk_stolen;<br>- uint64_t uma_memory_base = 0, uma_memory_size = 0;<br>- uint64_t tseg_memory_base = 0, tseg_memory_size = 0;<br>-<br>- /* Can we find out how much memory we can use at most this way? */<br>- pci_tolm = find_pci_tolm(dev->link_list);<br>- printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);<br>- printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",<br>- pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));<br>-<br>- tolud = sch_port_access_read(2, 8, 4);<br>- printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08llx\n", tolud);<br>-<br>- tomk = tolud / 1024;<br>- tomk_stolen = tomk;<br>-<br>- /* Note: subtract IGD device and TSEG. */<br>- reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);<br>- if (reg8 & 1) {<br>- int tseg_size = 0;<br>- printk(BIOS_DEBUG, "TSEG decoded, subtracting ");<br>- reg8 >>= 1;<br>- reg8 &= 3;<br>- switch (reg8) {<br>- case 0:<br>- tseg_size = 1024; /* TSEG = 1M */<br>- break;<br>- case 1:<br>- tseg_size = 2048; /* TSEG = 2M */<br>- break;<br>- case 2:<br>- tseg_size = 8192; /* TSEG = 8M */<br>- break;<br>- }<br>-<br>- printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10);<br>- tomk_stolen -= tseg_size;<br>-<br>- /* For reserving TSEG memory in the memory map */<br>- tseg_memory_base = tomk_stolen * 1024ULL;<br>- tseg_memory_size = tseg_size * 1024ULL;<br>- }<br>-<br>- reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(2, 0)), GGC);<br>- if (!(reg16 & 2)) {<br>- int uma_size = 0;<br>- printk(BIOS_DEBUG, "IGD decoded, subtracting ");<br>- reg16 >>= 4;<br>- reg16 &= 7;<br>- switch (reg16) {<br>- case 1:<br>- uma_size = 1024;<br>- break;<br>- case 2:<br>- uma_size = 4096;<br>- break;<br>- case 3:<br>- uma_size = 8192;<br>- break;<br>- }<br>- printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);<br>- tomk_stolen -= uma_size;<br>-<br>- /* For reserving UMA memory in the memory map. */<br>- uma_memory_base = tomk_stolen * 1024ULL;<br>- uma_memory_size = uma_size * 1024ULL;<br>- }<br>-<br>- /*<br>- * The following needs to be 2 lines, otherwise the second<br>- * number is always 0.<br>- */<br>- printk(BIOS_INFO, "Available memory: %dK", (u32) tomk);<br>- printk(BIOS_INFO, " (%dM)\n", (u32) (tomk >> 10));<br>-<br>- /* Report the memory regions. */<br>- ram_resource(dev, 3, 0, 640);<br>- ram_resource(dev, 4, 768, (tomk - 768));<br>- uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10);<br>- mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10);<br>-<br>- add_fixed_resources(dev, 7);<br>-<br>- assign_resources(dev->link_list);<br>-<br>- set_late_cbmem_top(tomk * 1024 - uma_memory_size - tseg_memory_base);<br>-}<br>-<br>-/*<br>- * TODO: We could determine how many PCIe busses we need in the bar. For now<br>- * that number is hardcoded to a max of 64.<br>- * See e7525/northbridge.c for an example.<br>- */<br>-static struct device_operations pci_domain_ops = {<br>- .read_resources = pci_domain_read_resources,<br>- .set_resources = pci_domain_set_resources,<br>- .enable_resources = NULL,<br>- .init = NULL,<br>- .scan_bus = pci_domain_scan_bus,<br>- .ops_pci_bus = pci_bus_default_ops,<br>-};<br>-<br>-static void mc_read_resources(device_t dev)<br>-{<br>- u32 pcie_config_base;<br>- int buses;<br>-<br>- pci_dev_read_resources(dev);<br>-<br>- /*<br>- * We use 0xcf as an unused index for our PCIe bar so that we find<br>- * it again.<br>- */<br>- buses = get_pcie_bar(&pcie_config_base);<br>- if (buses) {<br>- struct resource *resource = new_resource(dev, 0xcf);<br>- mmconf_resource_init(resource, pcie_config_base, buses);<br>- }<br>-}<br>-<br>-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- if (!vendor || !device) {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- pci_read_config32(dev, PCI_VENDOR_ID));<br>- } else {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- }<br>-}<br>-<br>-static struct pci_operations intel_pci_ops = {<br>- .set_subsystem = intel_set_subsystem,<br>-};<br>-<br>-static struct device_operations mc_ops = {<br>- .read_resources = mc_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .acpi_fill_ssdt_generator = generate_cpu_entries,<br>- .scan_bus = 0,<br>- .ops_pci = &intel_pci_ops,<br>-};<br>-<br>-static const struct pci_driver mc_driver __pci_driver = {<br>- .ops = &mc_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x8100,<br>-};<br>-<br>-static void cpu_bus_init(device_t dev)<br>-{<br>- initialize_cpus(dev->link_list);<br>-}<br>-<br>-static struct device_operations cpu_bus_ops = {<br>- .read_resources = DEVICE_NOOP,<br>- .set_resources = DEVICE_NOOP,<br>- .enable_resources = DEVICE_NOOP,<br>- .init = cpu_bus_init,<br>- .scan_bus = 0,<br>-};<br>-<br>-static void enable_dev(device_t dev)<br>-{<br>- /* Set the operations if it is a special bus type. */<br>- if (dev->path.type == DEVICE_PATH_DOMAIN) {<br>- dev->ops = &pci_domain_ops;<br>- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {<br>- dev->ops = &cpu_bus_ops;<br>- }<br>-}<br>-<br>-struct chip_operations northbridge_intel_sch_ops = {<br>- CHIP_NAME("Intel SCH Northbridge")<br>- .enable_dev = enable_dev,<br>-};<br>diff --git a/src/soc/intel/sch/nvs.h b/src/soc/intel/sch/nvs.h<br>deleted file mode 100644<br>index f62715e..0000000<br>--- a/src/soc/intel/sch/nvs.h<br>+++ /dev/null<br>@@ -1,141 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef SOC_INTEL_SCH_NVS_H<br>-#define SOC_INTEL_SCH_NVS_H<br>-<br>-#include <compiler.h><br>-typedef struct {<br>- /* Miscellaneous */<br>- u16 osys; /* 0x00 - Operating System */<br>- u8 smif; /* 0x02 - SMI function call ("TRAP") */<br>- u8 prm0; /* 0x03 - SMI function call parameter */<br>- u8 prm1; /* 0x04 - SMI function call parameter */<br>- u8 scif; /* 0x05 - SCI function call (via _L00) */<br>- u8 prm2; /* 0x06 - SCI function call parameter */<br>- u8 prm3; /* 0x07 - SCI function call parameter */<br>- u8 lckf; /* 0x08 - Global Lock function for EC */<br>- u8 prm4; /* 0x09 - Lock function parameter */<br>- u8 prm5; /* 0x0a - Lock function parameter */<br>- u32 p80d; /* 0x0b - Debug port (IO 0x80) value */<br>- u8 lids; /* 0x0f - LID state (open = 1) */<br>- u8 pwrs; /* 0x10 - Power state (AC = 1) */<br>- u8 dbgs; /* 0x11 - Debug state */<br>- u8 linx; /* 0x12 - Linux OS */<br>- u8 dckn; /* 0x13 - PCIe docking state */<br>- /* Thermal policy */<br>- u8 actt; /* 0x14 - active trip point */<br>- u8 psvt; /* 0x15 - passive trip point */<br>- u8 tc1v; /* 0x16 - passive trip point TC1 */<br>- u8 tc2v; /* 0x17 - passive trip point TC2 */<br>- u8 tspv; /* 0x18 - passive trip point TSP */<br>- u8 crtt; /* 0x19 - critical trip point */<br>- u8 dtse; /* 0x1a - Digital Thermal Sensor enable */<br>- u8 dts1; /* 0x1b - DT sensor 1 */<br>- u8 dts2; /* 0x1c - DT sensor 2 */<br>- u8 rsvd2;<br>- /* Battery Support */<br>- u8 bnum; /* 0x1e - number of batteries */<br>- u8 b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */<br>- u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */<br>- u8 rsvd3[3];<br>- /* Processor Identification */<br>- u8 apic; /* 0x28 - APIC enabled */<br>- u8 mpen; /* 0x29 - MP capable/enabled */<br>- u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */<br>- u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */<br>- u8 ppcm; /* 0x2c - Max. PPC state */<br>- u8 rsvd4[5];<br>- /* Super I/O & CMOS config */<br>- u8 natp; /* 0x32 - SIO type */<br>- u8 cmap; /* 0x33 - */<br>- u8 cmbp; /* 0x34 - */<br>- u8 lptp; /* 0x35 - LPT port */<br>- u8 fdcp; /* 0x36 - Floppy Disk Controller */<br>- u8 rfdv; /* 0x37 - */<br>- u8 hotk; /* 0x38 - Hot Key */<br>- u8 rtcf;<br>- u8 util;<br>- u8 acin;<br>- /* Integrated Graphics Device */<br>- u8 igds; /* 0x3c - IGD state */<br>- u8 tlst; /* 0x3d - Display Toggle List Pointer */<br>- u8 cadl; /* 0x3e - currently attached devices */<br>- u8 padl; /* 0x3f - previously attached devices */<br>- u16 cste; /* 0x40 - current display state */<br>- u16 nste; /* 0x42 - next display state */<br>- u16 sste; /* 0x44 - set display state */<br>- u8 ndid; /* 0x46 - number of device ids */<br>- u32 did[5]; /* 0x47 - 5b device id 1..5 */<br>- u8 rsvd5[0x9];<br>- /* Backlight Control */<br>- u8 blcs; /* 0x64 - Backlight Control possible */<br>- u8 brtl;<br>- u8 odds;<br>- u8 rsvd6[0x7];<br>- /* Ambient Light Sensors*/<br>- u8 alse; /* 0x6e - ALS enable */<br>- u8 alaf;<br>- u8 llow;<br>- u8 lhih;<br>- u8 rsvd7[0x6];<br>- /* EMA */<br>- u8 emae; /* 0x78 - EMA enable */<br>- u16 emap;<br>- u16 emal;<br>- u8 rsvd8[0x5];<br>- /* MEF */<br>- u8 mefe; /* 0x82 - MEF enable */<br>- u8 rsvd9[0x9];<br>- /* TPM support */<br>- u8 tpmp; /* 0x8c - TPM */<br>- u8 tpme;<br>- u8 rsvd10[8];<br>- /* SATA */<br>- u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */<br>- u8 gtf1[7];<br>- u8 gtf2[7];<br>- u8 idem;<br>- u8 idet;<br>- u8 rsvd11[7];<br>- /* IGD OpRegion (not implemented yet) */<br>- u32 aslb; /* 0xb4 - IGD OpRegion Base Address */<br>- u8 ibtt;<br>- u8 ipat;<br>- u8 itvf;<br>- u8 itvm;<br>- u8 ipsc;<br>- u8 iblc;<br>- u8 ibia;<br>- u8 issc;<br>- u8 i409;<br>- u8 i509;<br>- u8 i609;<br>- u8 i709;<br>- u8 idmm;<br>- u8 idms;<br>- u8 if1e;<br>- u8 hvco;<br>- u32 nxd[8];<br>- u8 rsvd12[8];<br>- /* Mainboard specific */<br>- u8 dock; /* 0xf0 - Docking Status */<br>- u8 bten;<br>- u8 rsvd13[14];<br>-} __packed global_nvs_t;<br>-<br>-void acpi_create_gnvs(global_nvs_t * gnvs);<br>-<br>-#endif /* SOC_INTEL_SCH_NVS_H */<br>diff --git a/src/soc/intel/sch/pcie.c b/src/soc/intel/sch/pcie.c<br>deleted file mode 100644<br>index 6ad5345..0000000<br>--- a/src/soc/intel/sch/pcie.c<br>+++ /dev/null<br>@@ -1,91 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-<br>-static void pci_init(struct device *dev)<br>-{<br>- u16 reg16;<br>- u32 reg32;<br>-<br>- printk(BIOS_DEBUG, "Initializing SCH PCIe bridge.\n");<br>-<br>- /* Enable Bus Master */<br>- reg32 = pci_read_config32(dev, PCI_COMMAND);<br>- reg32 |= PCI_COMMAND_MASTER;<br>- pci_write_config32(dev, PCI_COMMAND, reg32);<br>-<br>- /* Set Cache Line Size to 0x10 */<br>- // This has no effect but the OS might expect it<br>- pci_write_config8(dev, 0x0c, 0x10);<br>- //pci_write_config32(dev, 0x18, 0x11);<br>-<br>- //reg16 = pci_read_config16(dev, 0x3e);<br>- //reg16 &= ~(1 << 0); /* disable parity error response */<br>- // reg16 &= ~(1 << 1); /* disable SERR */<br>- //reg16 |= (1 << 2); /* ISA enable */<br>- //pci_write_config16(dev, 0x3e, reg16);<br>- /* Slot implemented. */<br>- reg16 = pci_read_config16(dev, 0x42);<br>- reg16 |= (1 << 8);<br>- pci_write_config16(dev, 0x42, reg16);<br>-<br>- reg16 = pci_read_config16(dev, 0x48);<br>- reg16 |= 0xf;<br>- pci_write_config16(dev, 0x48, reg16);<br>-}<br>-<br>-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- /* NOTE: This is not the default position! */<br>- if (!vendor || !device) {<br>- pci_write_config32(dev, 0x94, pci_read_config32(dev, 0));<br>- } else {<br>- pci_write_config32(dev, 0x94,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- }<br>-}<br>-<br>-static struct pci_operations pci_ops = {<br>- .set_subsystem = pcie_set_subsystem,<br>-};<br>-<br>-static struct device_operations device_ops = {<br>- .read_resources = pci_bus_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_bus_enable_resources,<br>- .init = pci_init,<br>- .scan_bus = pci_scan_bridge,<br>- .ops_pci = &pci_ops,<br>-};<br>-<br>-/* Port 1 */<br>-static const struct pci_driver sch_pcie_port1 __pci_driver = {<br>- .ops = &device_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x8110,<br>-};<br>-<br>-/*Port 2 */<br>-static const struct pci_driver sch_pcie_port2 __pci_driver = {<br>- .ops = &device_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x8112,<br>-};<br>diff --git a/src/soc/intel/sch/port_access.c b/src/soc/intel/sch/port_access.c<br>deleted file mode 100644<br>index 320c537..0000000<br>--- a/src/soc/intel/sch/port_access.c<br>+++ /dev/null<br>@@ -1,73 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-// Use simple device model for this file even in ramstage<br>-#define __SIMPLE_DEVICE__<br>-<br>-#include <stdint.h><br>-#include <arch/io.h><br>-#include <device/pci_def.h><br>-#include <device/pnp_def.h><br>-#include <cpu/x86/lapic.h><br>-#include "sch.h"<br>-<br>-/*<br>- * Restricted Access Regions:<br>- *<br>- * MCR - Message Control Register<br>- * 31 24 16 8 4 0<br>- * ----------------------------------------------------------------------------<br>- * | | | Target | Write | |<br>- * | Opcode | Port | register | byte | Reserved |<br>- * | | | Address | Enables | |<br>- * ----------------------------------------------------------------------------<br>- *<br>- * MDR - Message Data Register<br>- * 31 0<br>- * ----------------------------------------------------------------------------<br>- * | |<br>- * | Data |<br>- * | |<br>- * ----------------------------------------------------------------------------<br>- */<br>-<br>-#define MSG_OPCODE_READ 0xD0000000<br>-#define MSG_OPCODE_WRITE 0xE0000000<br>-<br>-#define MCR 0xD0<br>-#define MDR 0xD4<br>-<br>-int sch_port_access_read(int port, int reg, int bytes)<br>-{<br>- pci_write_config32(PCI_DEV(0, 0, 0), MCR,<br>- (MSG_OPCODE_READ | (port << 16) | (reg << 8)));<br>- return pci_read_config32(PCI_DEV(0, 0, 0), MDR);<br>-}<br>-<br>-void sch_port_access_write(int port, int reg, int bytes, long data)<br>-{<br>- pci_write_config32(PCI_DEV(0, 0, 0), MDR, data);<br>- pci_write_config32(PCI_DEV(0, 0, 0), MCR,<br>- (MSG_OPCODE_WRITE | (port << 16) | (reg << 8)));<br>- pci_read_config32(PCI_DEV(0, 0, 0), MDR);<br>-}<br>-<br>-void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data)<br>-{<br>- pci_write_config32(PCI_DEV(0, 0, 0), MDR, data);<br>- pci_write_config32(PCI_DEV(0, 0, 0), MCR,<br>- ((cmd << 24) | (port << 16) | (reg << 8)));<br>- pci_read_config32(PCI_DEV(0, 0, 0), MDR);<br>-}<br>diff --git a/src/soc/intel/sch/raminit.c b/src/soc/intel/sch/raminit.c<br>deleted file mode 100644<br>index 1131510..0000000<br>--- a/src/soc/intel/sch/raminit.c<br>+++ /dev/null<br>@@ -1,373 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <string.h><br>-#include <cpu/x86/mtrr.h><br>-#include <cpu/x86/cache.h><br>-#include <spd.h><br>-#include "raminit.h"<br>-#include "sch.h"<br>-<br>-#define DEBUG_RAM_SETUP<br>-#define SOFTSTRSP(base, off) *((volatile u8 *)((base) + (off)))<br>-<br>-/* Debugging macros. */<br>-#if defined(DEBUG_RAM_SETUP)<br>-#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)<br>-#else<br>-#define PRINTK_DEBUG(x...)<br>-#endif<br>-<br>-#define BOOT_MODE_RESUME 1<br>-#define BOOT_MODE_NORMAL 0<br>-<br>-#include "port_access.c"<br>-<br>-static void detect_fsb(struct sys_info *sysinfo)<br>-{<br>- u32 reg32;<br>-<br>- reg32 = sch_port_access_read(5, 3, 4);<br>- if (reg32 & BIT(3))<br>- sysinfo->fsb_frequency = 533;<br>- else<br>- sysinfo->fsb_frequency = 400;<br>-}<br>-<br>-static u32 detect_softstrap_base(void)<br>-{<br>- u32 reg32, base_addr;<br>-<br>- reg32 = sch_port_access_read(4, 0x71, 2);<br>- reg32 &= 0x700;<br>- reg32 = reg32 >> 7;<br>- switch (reg32) {<br>- case 7:<br>- base_addr = 0xFFFB0000;<br>- break;<br>- case 6:<br>- base_addr = 0xFFFC0000;<br>- break;<br>- case 5:<br>- base_addr = 0xFFFD0000;<br>- break;<br>- case 4:<br>- base_addr = 0xFFFE0000;<br>- break;<br>- default:<br>- base_addr = 0;<br>- die("No valid softstrap base found.\n");<br>- }<br>- return base_addr;<br>-}<br>-<br>-static void detect_softstraps(struct sys_info *sysinfo)<br>-{<br>- u8 reg8, temp;<br>- u32 sbase = detect_softstrap_base();<br>-<br>- reg8 = SOFTSTRSP(sbase, 0x87f2);<br>- sysinfo->ranks = reg8;<br>- if (reg8 == 0) {<br>- sysinfo->ram_param_source = RAM_PARAM_SOURCE_SPD;<br>- /* FIXME: Implement SPD reading. */<br>- die("No support for reading DIMM config from SPD yet!");<br>- return;<br>- } else {<br>- sysinfo->ram_param_source = RAM_PARAM_SOURCE_SOFTSTRAP;<br>- /* Timings from soft strap */<br>- reg8 = SOFTSTRSP(sbase, 0x87f0);<br>- temp = reg8 & 0x30;<br>- temp = temp >> 4;<br>- sysinfo->cl = temp;<br>- temp = reg8 & 0x0c;<br>- temp = temp >> 2;<br>- sysinfo->trcd = temp;<br>- temp = reg8 & 0x03;<br>- sysinfo->trp = temp;<br>-<br>- /* Geometry from Softstrap */<br>- reg8 = SOFTSTRSP(sbase, 0x87f1);<br>-<br>- temp = reg8 & 0x06;<br>- temp = temp >> 1;<br>- sysinfo->device_density = temp;<br>-<br>- temp = reg8 & 0x01;<br>- sysinfo->data_width = temp;<br>-<br>- /* Refresh rate default 7.8us */<br>- sysinfo->refresh = 3;<br>- }<br>-}<br>-<br>-static void program_sch_dram_data(struct sys_info *sysinfo)<br>-{<br>- u32 reg32;<br>-<br>- /*<br>- * Program DRP DRAM Rank Population and Interface Register as per data<br>- * in sysinfo SCH port 1 register 0..0xFF.<br>- */<br>- reg32 =<br>- sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);<br>- reg32 &= ~(DRP_FIELDS); /* Clear all DRP fields we'll change. */<br>- /* Rank0 Device Width, Density, Enable */<br>- reg32 |= sysinfo->data_width | (sysinfo->device_density << 1) | (1 << 3);<br>- /* Rank1 Device Width, Density, Enable */<br>- reg32 |= (sysinfo->data_width << 4)<br>- | ((sysinfo->device_density) << 5) | (1 << 7);<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT,<br>- SCH_MSG_DUNIT_REG_DRP, 4, reg32);<br>-<br>- /*<br>- * Program DTR DRAM Timing Register as per data in sysinfo SCH port 1<br>- * register 1.<br>- *<br>- * tRD_dly = 2 (15:13 = 010b)<br>- * 0X3F<br>- */<br>- reg32 =<br>- sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DTR, 4);<br>- reg32 &= ~(DTR_FIELDS); /* Clear all DTR fields we'll change. */<br>-<br>- reg32 = (sysinfo->trp);<br>- reg32 |= (sysinfo->trcd) << 2;<br>- reg32 |= (sysinfo->cl) << 4;<br>- reg32 |= 0X4000; /* tRD_dly = 2 (15:13 = 010b) */<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DTR, 4,<br>- reg32);<br>-<br>- /*<br>- * DCO DRAM Controller Operation Register as per data in sysinfo<br>- * SCH port 1 register 2 0xF.<br>- */<br>- reg32 =<br>- sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4);<br>- reg32 &= ~(DCO_FIELDS); /* Clear all DTR fields we'll change. */<br>-<br>- if (sysinfo->fsb_frequency == 533)<br>- reg32 |= 1;<br>- else<br>- reg32 &= ~(BIT(0));<br>- reg32 = 0x006911c; // FIXME ?<br>-<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4,<br>- reg32);<br>-}<br>-<br>-static void program_dll_config(struct sys_info *sysinfo)<br>-{<br>- if (sysinfo->fsb_frequency == 533) {<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x21, 4, 0x46464646);<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x22, 4, 0x46464646);<br>- } else {<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x21, 4, 0x58585858);<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x22, 4, 0x58585858);<br>- }<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x23, 4, 0x2222);<br>- if (sysinfo->fsb_frequency == 533)<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x20, 4, 0x993B);<br>- else<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x20, 4, 0xCC3B);<br>-}<br>-<br>-static void do_jedec_init(struct sys_info *sysinfo)<br>-{<br>- u32 reg32, rank, cmd, temp, num_ranks;<br>-<br>- /* Performs JEDEC memory initializattion for all memory rows */<br>- /* Set CKE0/1 low */<br>- reg32 =<br>- sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);<br>- reg32 |= DRP_CKE_DIS;<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT,<br>- SCH_MSG_DUNIT_REG_DRP, 4, reg32);<br>- reg32 =<br>- sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);<br>- rank = 0;<br>- num_ranks = sysinfo->ranks;<br>-<br>- do {<br>- /* Start clocks */<br>- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT,<br>- SCH_MSG_DUNIT_REG_DRP, 4);<br>- reg32 &= ~(DRP_SCK_DIS); /* Enable all SCK/SCKB by def. */<br>- sch_port_access_write(1, SCH_MSG_DUNIT_REG_DRP, 4, reg32);<br>- /* Program misc. SCH registers on rank 0 initialization. */<br>- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT,<br>- SCH_MSG_DUNIT_REG_DRP, 4);<br>- if (rank == 0)<br>- program_dll_config(sysinfo);<br>-<br>- printk(BIOS_DEBUG, "Setting up RAM\n");<br>-<br>- /*<br>- * Wait 200us<br>- * reg32 = inb(ACPI_BASE + 8); PM1 Timer<br>- * reg32 &=0xFFFFFF;<br>- * reg32 +=0x2EE;<br>- * do {<br>- * reg32 = inb(ACPI_BASE + 8);PM1 Timer<br>- * reg32 &= 0xFFFFFF;<br>- * } while (reg32 < 0x2EE);<br>- */<br>-<br>- /* Apply NOP. */<br>- cmd = rank;<br>- cmd |= SCH_DRAMINIT_CMD_NOP;<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,<br>- SCH_MSG_DUNIT_PORT, 0, cmd);<br>- /* Set CKE=high. */<br>- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT,<br>- SCH_MSG_DUNIT_REG_DRP, 4);<br>- reg32 &= 0xFFFF9FFF; /* Clear both the CKE static disables. */<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT,<br>- SCH_MSG_DUNIT_REG_DRP, 4, reg32);<br>- /*<br>- * Wait 400ns (not needed when executing from flash).<br>- * Precharge all.<br>- */<br>- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT,<br>- SCH_MSG_DUNIT_REG_DRP, 4);<br>- cmd = rank;<br>- cmd |= SCH_DRAMINIT_CMD_PALL;<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,<br>- SCH_MSG_DUNIT_PORT, 0, cmd);<br>-<br>- /*<br>- * EMRS(2); High temp self refresh=disabled,<br>- * partial array self refresh=full.<br>- */<br>- cmd = rank;<br>- cmd |= SCH_DRAMINIT_CMD_EMRS2;<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,<br>- SCH_MSG_DUNIT_PORT, 0, cmd);<br>-<br>- /* EMRS(3) (no command). */<br>- cmd = rank;<br>- cmd |= SCH_DRAMINIT_CMD_EMRS3;<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,<br>- SCH_MSG_DUNIT_PORT, 0, cmd);<br>-<br>- /* EMRS(1); Enable DLL (Leave all bits in the command at 0). */<br>- cmd = rank;<br>- cmd |= SCH_DRAMINIT_CMD_EMRS1;<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,<br>- SCH_MSG_DUNIT_PORT, 0, cmd);<br>-<br>- /* MRS; Reset DLL (Set memory address bit 8). */<br>- cmd = rank;<br>- cmd |= SCH_DRAMINIT_CMD_MRS;<br>- cmd |= (SCH_JEDEC_DLLRESET << SCH_DRAMINIT_ADDR_OFFSET);<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,<br>- SCH_MSG_DUNIT_PORT, 0, cmd);<br>-<br>- /* Precharge all. */<br>- cmd = rank;<br>- cmd |= SCH_DRAMINIT_CMD_PALL;<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,<br>- SCH_MSG_DUNIT_PORT, 0, cmd);<br>-<br>- /* Issue 2 auto-refresh commands. */<br>- cmd = rank;<br>- cmd |= SCH_DRAMINIT_CMD_AREF;<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,<br>- SCH_MSG_DUNIT_PORT, 0, cmd);<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,<br>- SCH_MSG_DUNIT_PORT, 0, cmd);<br>-<br>- /* MRS command including tCL, tWR, burst length (always 4). */<br>- cmd = rank;<br>- cmd |= (SCH_DRAMINIT_CMD_MRS + JEDEC_STATIC_PARAM); /* Static param */<br>- temp = sysinfo->cl;<br>- temp += TCL_LOW; /* Adjust for the TCL base. */<br>- temp = temp << ((SCH_JEDEC_CL_OFFSET<br>- + SCH_DRAMINIT_ADDR_OFFSET)); /* Ready the CAS latency */<br>- cmd |= temp;<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,<br>- SCH_MSG_DUNIT_PORT, 0, cmd);<br>-<br>- /*<br>- * Wait 200 clocks (max of 1us, so no need to delay).<br>- * Issue EMRS(1):OCD default.<br>- */<br>- cmd = rank;<br>- cmd |= SCH_DRAMINIT_CMD_EMRS1;<br>- cmd |= (SCH_JEDEC_OCD_DEFAULT << SCH_DRAMINIT_ADDR_OFFSET);<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,<br>- SCH_MSG_DUNIT_PORT, 0, cmd);<br>-<br>- /* Issue EMRS(1): OCD cal. mode exit. */<br>- cmd = rank;<br>- cmd |= SCH_DRAMINIT_CMD_EMRS1;<br>- cmd |= (SCH_JEDEC_DQS_DIS << SCH_DRAMINIT_ADDR_OFFSET);<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,<br>- SCH_MSG_DUNIT_PORT, 0, cmd);<br>- rank += SCH_DRAMINIT_RANK_MASK;<br>- num_ranks--;<br>- } while (num_ranks);<br>-}<br>-<br>-/**<br>- * @param boot_mode 0 = normal, 1 = resume<br>- */<br>-void sdram_initialize(int boot_mode)<br>-{<br>- struct sys_info sysinfo;<br>- u32 reg32;<br>-<br>- printk(BIOS_DEBUG, "Setting up RAM controller.\n");<br>-<br>- memset(&sysinfo, 0, sizeof(sysinfo));<br>-<br>- detect_fsb(&sysinfo);<br>- detect_softstraps(&sysinfo);<br>-<br>- program_sch_dram_data(&sysinfo);<br>-<br>- /* cold boot */<br>- if (boot_mode == BOOT_MODE_NORMAL)<br>- do_jedec_init(&sysinfo);<br>- else<br>- program_dll_config(&sysinfo);<br>-<br>- /* RAM init complete. */<br>- reg32 =<br>- sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4);<br>- reg32 |= DCO_IC;<br>- reg32 |= ((sysinfo.refresh) << 2);<br>- reg32 = 0x006919c;<br>- sch_port_access_write(SCH_MSG_DUNIT_PORT,<br>- SCH_MSG_DUNIT_REG_DCO, 4, reg32);<br>-<br>- /* Setting up TOM. */<br>- reg32 = 0x10000000;<br>- reg32 = reg32 >> sysinfo.data_width;<br>- reg32 = reg32 << sysinfo.device_density;<br>- reg32 = reg32 << sysinfo.ranks;<br>- reg32 = 0x40000000;<br>- sch_port_access_write(2, 8, 4, reg32);<br>-<br>- /* Resume mode. */<br>- if (boot_mode == BOOT_MODE_RESUME)<br>- sch_port_access_write_ram_cmd(SCH_OPCODE_WAKEFULLON,<br>- SCH_MSG_DUNIT_PORT, 0, 0);<br>-<br>- sch_port_access_write(2, 0, 4, 0x98);<br>- sch_port_access_write(2, 3, 4, 0x7);<br>- sch_port_access_write(3, 2, 4, 0x408);<br>- sch_port_access_write(4, 0x71, 4, 0x600);<br>-}<br>diff --git a/src/soc/intel/sch/raminit.h b/src/soc/intel/sch/raminit.h<br>deleted file mode 100644<br>index 0d4f436..0000000<br>--- a/src/soc/intel/sch/raminit.h<br>+++ /dev/null<br>@@ -1,180 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef RAMINIT_H<br>-#define RAMINIT_H<br>-<br>-#include <compiler.h><br>-<br>-/**<br>- * Bit Equates<br>- **/<br>-#define BIT(x) (1<<x)<br>-<br>-#define EBP_TRP_MASK (BIT(1) | BIT(0))<br>-#define TRP_LOW 3h<br>-#define TRP_HIGH 5h<br>-#define EBP_TRP_OFFSET 0 /* Start of TRP field in EBP*/<br>-#define EBP_TRCD_MASK (BIT(3) | BIT(2))<br>-#define TRCD_LOW 3h<br>-#define TRCD_HIGH 5h<br>-#define EBP_TRCD_OFFSET 2 /* Start of TRCD field in EBP*/<br>-#define EBP_TCL_MASK (BIT(5) | BIT(4))<br>-#define TCL_LOW 3 /* Minimum supported CL*/<br>-#define TCL_HIGH 5 /* Maximum supported CL*/<br>-#define EBP_TCL_OFFSET 4 /* EBP bit( )for CL mask*/<br>-#define EBP_DDR2_CL_5_0 BIT(5) /* CL 5.0 = 10b*/<br>-#define EBP_DDR2_CL_4_0 BIT(4) /* CL 4.0 = 01b*/<br>-#define EBP_DDR2_CL_3_0 00h /* CL 3.0 = 00b*/<br>-#define EBP_FREQ_MASK (BIT(10)| BIT(9))<br>-#define EBP_FREQ_OFFSET 9 /* EBP bit( )for frequency mask*/<br>-#define EBP_FREQ_400 0 /* 400MHz EBP[10:9] = 00b*/<br>-#define EBP_FREQ_533 BIT(9) /* 533MHz EBP[10:9] = 01b*/<br>-#define EBP_REFRESH_MASK (BIT(12)| BIT(11))<br>-#define EBP_REFRESH_OFFSET 11 /* Bit offset of refresh field*/<br>-#define EBP_REF_DIS 00h /* Mask for refresh disabled*/<br>-#define EBP_REF_128CLK BIT(11) /* Mask for 128 clks referesh rate*/<br>-#define EBP_REF_3_9 BIT(12) /* Mask for 3.9us refresh rate*/<br>-#define EBP_REF_7_8 (BIT(12)| BIT(11))/* Mask for 7.8us refresh rate*/<br>-#define EBP_WIDTH_MASK BIT(15)<br>-#define EBP_WIDTH_OFFSET 15 /* Bit offset of EBP width field*/<br>-#define EBP_SOCKET_X16 BIT(15) /* Bit mask of x8/x16 bit*/<br>-#define EBP_DENSITY_MASK (BIT(17)| BIT(16))<br>-#define EBP_DENSITY_OFFSET 16<br>-#define EBP_DENSITY_512 BIT(16) /* 512Mbit density*/<br>-#define EBP_DENSITY_1024 BIT(17) /* 1024Mbit density*/<br>-#define EBP_DENSITY_2048 (BIT(17)| BIT(16))/* 2048Mbit density*/<br>-#define EBP_RANKS_MASK BIT(18)<br>-#define EBP_RANKS_OFFSET 18<br>-#define EBP_RANKS BIT(18) /* Bit offset of # of ranks bit*/<br>-#define EBP_PACKAGE_TYPE BIT(19) /* Package type (stacked or not)*/<br>-#define EBP_2X_MASK BIT(20)<br>-#define EBP_2X_OFFSET 20 /* Bit offset of ebp 2x refresh field*/<br>-#define EBP_2X_AUTO_REFRESH BIT(20) /* Bit mask of 2x refresh field*/<br>-#define EBP_DRAM_PARM_MASK BIT(21)<br>-#define EBP_DRAM_PARM_OFFSET 21<br>-#define EBP_DRAM_PARM_SPD 0 /* Use SPD to get DRAM parameters*/<br>-#define EBP_DRAM_PARM_CMC BIT(21) /* DRAM parameters in CMC binary*/<br>-#define EBP_BOOT_PATH BIT(31)<br>-<br>-<br>-<br>-<br>-#define HB_REG_MCR 0xD0 /* Message Control Register */<br>-#define HB_REG_MCR_OP_OFFSET 24 /* Offset of the opcode field in MCR */<br>-#define HB_REG_MCR_PORT_OFFSET 16 /* Offset of the port field in MCR */<br>-#define HB_REG_MCR_REG_OFFSET 8 /* Offset of the register field in MCR */<br>-#define HB_REG_MDR 0xD4 /* Message Data Register */<br>-<br>-/* SCH Message OpCodes and Attributes*/<br>-#define SCH_OPCODE_WAKEFULLON 0x2 /* SCH message bus "Wake Full On" opcode*/<br>-#define SCH_OPCODE_DRAMINIT 0xA0 /* SCH message bus "DRAM Init" opcode */<br>-#define SCH_DRAMINIT_CMD_MRS 0x4000 /* MRS command */<br>-#define SCH_DRAMINIT_CMD_EMRS1 0x8 /* EMRS 1 command */<br>-#define SCH_DRAMINIT_CMD_EMRS2 0x10 /* EMRS 2 command */<br>-#define SCH_DRAMINIT_CMD_EMRS3 0x18 /* EMRS 3 command */<br>-#define SCH_DRAMINIT_CMD_CBR 0x1 /* CBR command */<br>-#define SCH_DRAMINIT_CMD_AREF 0x10001 /* Refresh command, MA10=0->All */<br>-#define SCH_DRAMINIT_CMD_PALL 0x10002 /* Precharge command, MA10=1->All */<br>-#define SCH_DRAMINIT_CMD_BACT 0x3 /* Bank activate command */<br>-#define SCH_DRAMINIT_CMD_NOP 0x7 /* NOP command */<br>-#define SCH_DRAMINIT_RANK_OFFSET 21 /* Offset of the rank selection bit */<br>-#define SCH_DRAMINIT_RANK_MASK BIT(21)<br>-#define SCH_DRAMINIT_ADDR_OFFSET 6 /* Offset of the address field in MDR */<br>-#define SCH_DRAMINIT_INTLV BIT(3) /* Interleave burst type */<br>-#define SCH_DRAMINIT_BL4 2 /* Burst Length = 4 */<br>-#define SCH_DRAMINIT_CL_OFFSET 4 /* CAS Latency bit offset */<br>-#define SCH_DRAMINIT_OCD_DEFAULT 0xE000 /* OCD Default command */<br>-#define SCH_DRAMINIT_DQS_DIS BIT(16) /* DQS Disable command */<br>-#define SCH_OPCODE_READ 0xD0 /* SCH message bus "read" opcode */<br>-#define SCH_OPCODE_WRITE 0xE0 /* SCH message bus "write" opcode */<br>-<br>-/* SCH Message Ports and Registers*/<br>-<br>-#define SCH_MSG_DUNIT_PORT 0x1 /* DRAM unit port */<br>-#define SCH_MSG_DUNIT_REG_DRP 0x0 /* DRAM Rank Population and Interface */<br>-#define DRP_FIELDS 0xFF /* Pertinent fields in DRP */<br>-#define DRP_RANK0_OFFSET 3 /* Rank 0 enable offset */<br>-#define DRP_RANK1_OFFSET 7 /* Rank 1 enable offset */<br>-#define DRP_DENSITY0_OFFSET 1 /* Density offset - Rank 0 */<br>-#define DRP_DENSITY1_OFFSET 5 /* Density offset - Rank 1 */<br>-#define DRP_WIDTH0_OFFSET 0 /* Width offset - Rank 0 */<br>-#define DRP_WIDTH1_OFFSET 4 /* Width offset - Rank 1 */<br>-#define DRP_CKE_DIS (BIT(14)| BIT(13)) /* CKE disable bits for both ranks */<br>-#define DRP_CKE_DIS0 BIT(13) /* CKE disable bit - Rank 0 */<br>-#define DRP_CKE_DIS1 BIT(14) /* CKE disable bit - Rank 1 */<br>-#define DRP_SCK_DIS (BIT(11)| BIT(10)) /* SCK/SCKB disable bits */<br>-#define DRP_SCK_DIS1 BIT(11) /* SCK[1]/SCKB[1] disable */<br>-#define DRP_SCK_DIS0 BIT(10) /* SCK[0]/SCKB[0] disable */<br>-#define SCH_MSG_DUNIT_REG_DTR 0x01 /* DRAM Timing Register */<br>-#define DTR_FIELDS 0x3F /* Pertinent fields in DTR */<br>-#define DTR_TCL_OFFSET 4 /* CAS latency offset */<br>-#define DTR_TRCD_OFFSET 2 /* RAS CAS Delay Offset */<br>-#define DTR_TRP_OFFSET 0 /* RAS Precharge Delay Offset */<br>-#define SCH_MSG_DUNIT_REG_DCO 0x2 /* DRAM Control Register */<br>-#define DCO_FIELDS 0xF /* Pertinent fields in DCO */<br>-#define DCO_REFRESH_OFFSET 2 /* Refresh Rate Field Offset */<br>-#define DCO_FREQ_OFFSET 0 /* DRAM Frequency Field Offset */<br>-#define DCO_IC BIT(7) /* Initialization complete bit */<br>-#define SCH_MSG_PUNIT_PORT 04h /* Punit Port */<br>-#define SCH_MSG_PUNIT_REG_PCR 71h /* Punit Control Register */<br>-#define SCH_MSG_TEST_PORT 05h /* Test port */<br>-#define SCH_MSG_TEST_REG_MSR 03h /* Mode and Status Register */<br>-<br>-<br>-/* Jedec initialization mapping into the MDR address field for DRAM init messages*/<br>-<br>-<br>-#define SCH_JEDEC_DLLRESET BIT(8) /* DLL Reset bit( ) */<br>-#define SCH_JEDEC_INTLV BIT(3) /* Interleave/NOT(Sequential) bit( ) */<br>-#define SCH_JEDEC_CL_OFFSET 4 /* Offset of the CAS latency field */<br>-#define SCH_JEDEC_OCD_DEFAULT (BIT(7)| BIT(8)| BIT(9)) /* OCD default value */<br>-#define SCH_JEDEC_DQS_DIS BIT(10) /* DQS disable bit */<br>-#define SCH_JEDEC_BL4 BIT(1) /* Burst length 4 value */<br>-/*static values used during JEDEC iniatialization. These values are not<br>-dependent on memory or chipset configuration.*/<br>-#define JEDEC_STATIC_PARAM ((SCH_JEDEC_INTLV << SCH_DRAMINIT_ADDR_OFFSET) + (SCH_JEDEC_BL4 << SCH_DRAMINIT_ADDR_OFFSET))<br>-<br>-#define DIMM_SOCKETS 2<br>-<br>-#define DIMM_SPD_BASE 0x50<br>-#define DIMM_TCO_BASE 0x30<br>-<br>-/* Burst length is always 8 */<br>-#define BURSTLENGTH 8<br>-#define RAM_PARAM_SOURCE_SOFTSTRAP 1<br>-#define RAM_PARAM_SOURCE_SPD 0<br>-struct sys_info {<br>-<br>- u16 memory_frequency; /* 400 or 533*/<br>- u16 fsb_frequency; /* 400 or 533*/<br>-<br>- u8 trp; /*3,4,5 DRAM clocks */<br>- u8 trcd; /*3,4,5 DRAM clocks */<br>- u8 cl; /*CAS Latency 3,4,5*/<br>-<br>- u8 refresh; /*Refresh rate disabled,128 DRAM clocks,3.9us,7.8us */<br>-<br>- u8 data_width; /*x8/x16 data width */<br>- u8 device_density; /*SDRAM Device Density 512/1024/2048Mbit */<br>- u8 ranks; /*Single/Double */<br>- u8 ram_param_source; /*DRAM Parameter Source SPD/SoftStraps(R) Block (down memory) */<br>- u8 boot_path;<br>-<br>-} __packed;<br>-<br>-void sdram_initialize(int boot_mode);<br>-<br>-#endif /* RAMINIT_H */<br>diff --git a/src/soc/intel/sch/reset.c b/src/soc/intel/sch/reset.c<br>deleted file mode 100644<br>index 91bcd69..0000000<br>--- a/src/soc/intel/sch/reset.c<br>+++ /dev/null<br>@@ -1,29 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <reset.h><br>-<br>-void do_soft_reset(void)<br>-{<br>- outb(0x04, 0xcf9);<br>-}<br>-<br>-void do_hard_reset(void)<br>-{<br>- outb(0x02, 0xcf9);<br>- outb(0x06, 0xcf9);<br>-}<br>diff --git a/src/soc/intel/sch/sch.h b/src/soc/intel/sch/sch.h<br>deleted file mode 100644<br>index bdaddb2..0000000<br>--- a/src/soc/intel/sch/sch.h<br>+++ /dev/null<br>@@ -1,69 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2010 coresystems GmbH<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef __SCH_POULSBO_H__<br>-#define __SCH_POULSBO_H__<br>-<br>-#if !defined(__ASSEMBLER__)<br>-int sch_port_access_read(int port, int reg, int bytes);<br>-void sch_port_access_write(int port, int reg, int bytes, long data);<br>-void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);<br>-#endif<br>-<br>-/* Southbridge IO BARs */<br>-/* TODO Make sure these don't get changed by stage2 */<br>-#define SCH_ENABLE_BIT (1<<31)<br>-#define DEFAULT_ACPIPBLKBASE 0x510<br>-<br>-#define DEFAULT_SMBUSBASE 0x540<br>-#define DEFAULT_GPIOBASE 0x588<br>-#define DEFAULT_GPE0BASE 0x5C0<br>-#define DEFAULT_SMMCNTRLBASE 0x3F703F76<br>-<br>-#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)<br>-<br>-#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */<br>-<br>-/* IGD */<br>-#define GGC 0x52<br>-<br>-/* Root Complex Register Block */<br>-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBABASE + x))<br>-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBABASE + x))<br>-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBABASE + x))<br>-<br>-/* FIXME: should probably be in southbridge, but is setup in romstage, too */<br>-#define CMC_SHADOW 0x3faf0000<br>-<br>-#define DEFAULT_PMBASE 0x500<br>-<br>-/* SMBus I/O bits. */<br>-#define SMBHSTSTAT 0x0<br>-#define SMBHSTCTL 0x2<br>-#define SMBHSTCMD 0x3<br>-#define SMBXMITADD 0x4<br>-#define SMBHSTDAT0 0x5<br>-#define SMBHSTDAT1 0x6<br>-#define SMBBLKDAT 0x7<br>-#define SMBTRNSADD 0x9<br>-#define SMBSLVDATA 0xa<br>-#define SMLINK_PIN_CTL 0xe<br>-#define SMBUS_PIN_CTL 0xf<br>-<br>-#define SMBUS_TIMEOUT (10 * 1000 * 100)<br>-<br>-#endif /* __SCH_POULSBO_H__ */<br>diff --git a/src/soc/intel/sch/smbus.c b/src/soc/intel/sch/smbus.c<br>deleted file mode 100644<br>index 54baa68..0000000<br>--- a/src/soc/intel/sch/smbus.c<br>+++ /dev/null<br>@@ -1,75 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/path.h><br>-#include <device/smbus.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <arch/io.h><br>-#include "sch.h"<br>-#include "smbus.h"<br>-<br>-static int lsmbus_read_byte(device_t dev, u8 address)<br>-{<br>- u16 device;<br>- struct resource *res;<br>- struct bus *pbus;<br>-<br>- device = dev->path.i2c.device;<br>- pbus = get_pbus_smbus(dev);<br>- res = find_resource(pbus->dev, 0x20);<br>-<br>- return do_smbus_read_byte(res->base, device, address);<br>-}<br>-<br>-static struct smbus_bus_operations lops_smbus_bus = {<br>- .read_byte = lsmbus_read_byte,<br>-};<br>-<br>-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- if (!vendor || !device) {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- pci_read_config32(dev, PCI_VENDOR_ID));<br>- } else {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- }<br>-}<br>-<br>-static struct pci_operations smbus_pci_ops = {<br>- .set_subsystem = smbus_set_subsystem,<br>-};<br>-<br>-static struct device_operations smbus_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = 0,<br>- .scan_bus = scan_smbus,<br>- .ops_smbus_bus = &lops_smbus_bus,<br>- .ops_pci = &smbus_pci_ops,<br>-};<br>-<br>-// FIXME<br>-/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */<br>-static const struct pci_driver i82801gx_smbus __pci_driver = {<br>- .ops = &smbus_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x27da,<br>-};<br>diff --git a/src/soc/intel/sch/smbus.h b/src/soc/intel/sch/smbus.h<br>deleted file mode 100644<br>index 19d70b6..0000000<br>--- a/src/soc/intel/sch/smbus.h<br>+++ /dev/null<br>@@ -1,94 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com><br>- * Copyright (C) 2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <device/smbus_def.h><br>-<br>-static void smbus_delay(void)<br>-{<br>- inb(0x80);<br>-}<br>-<br>-static int smbus_wait_until_ready(u16 smbus_base)<br>-{<br>- unsigned loops = SMBUS_TIMEOUT;<br>- unsigned char byte;<br>- do {<br>- smbus_delay();<br>- if (--loops == 0)<br>- break;<br>- byte = inb(smbus_base + SMBHSTSTAT);<br>- } while (byte & 1);<br>- return loops ? 0 : -1;<br>-}<br>-<br>-static int smbus_wait_until_done(u16 smbus_base)<br>-{<br>- unsigned loops = SMBUS_TIMEOUT;<br>- unsigned char byte;<br>- do {<br>- smbus_delay();<br>- if (--loops == 0)<br>- break;<br>- byte = inb(smbus_base + SMBHSTSTAT);<br>- } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);<br>- return loops ? 0 : -1;<br>-}<br>-<br>-static int do_smbus_read_byte(unsigned smbus_base, unsigned device,<br>- unsigned address)<br>-{<br>- unsigned char global_status_register;<br>- unsigned char byte;<br>-<br>- if (smbus_wait_until_ready(smbus_base) < 0) {<br>- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;<br>- }<br>- /* Setup transaction */<br>- /* Disable interrupts */<br>- outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);<br>- /* Set the device I'm talking to */<br>- outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);<br>- /* Set the command/address... */<br>- outb(address & 0xff, smbus_base + SMBHSTCMD);<br>- /* Set up for a byte data read */<br>- outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),<br>- (smbus_base + SMBHSTCTL));<br>- /* Clear any lingering errors, so the transaction will run */<br>- outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);<br>-<br>- /* Clear the data byte... */<br>- outb(0, smbus_base + SMBHSTDAT0);<br>-<br>- /* Start the command */<br>- outb((inb(smbus_base + SMBHSTCTL) | 0x40), smbus_base + SMBHSTCTL);<br>-<br>- /* Poll for transaction completion */<br>- if (smbus_wait_until_done(smbus_base) < 0) {<br>- return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;<br>- }<br>-<br>- global_status_register = inb(smbus_base + SMBHSTSTAT);<br>-<br>- /* Ignore the "In Use" status... */<br>- global_status_register &= ~(3 << 5);<br>-<br>- /* Read results of transaction */<br>- byte = inb(smbus_base + SMBHSTDAT0);<br>- if (global_status_register != (1 << 1)) {<br>- return SMBUS_ERROR;<br>- }<br>- return byte;<br>-}<br>diff --git a/src/soc/intel/sch/smi.c b/src/soc/intel/sch/smi.c<br>deleted file mode 100644<br>index 7e5ce24..0000000<br>--- a/src/soc/intel/sch/smi.c<br>+++ /dev/null<br>@@ -1,339 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <cpu/x86/cache.h><br>-#include <cpu/x86/smm.h><br>-#include <cpu/cpu.h><br>-#include <string.h><br>-#include "chip.h"<br>-#include "sch.h"<br>-<br>-/* I945 */<br>-#define SMRAM 0x9d<br>-#define D_OPEN (1 << 6)<br>-#define D_CLS (1 << 5)<br>-#define D_LCK (1 << 4)<br>-#define G_SMRAME (1 << 3)<br>-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))<br>-<br>-/* ICH7 */<br>-#define PM1_STS 0x00<br>-#define PM1_EN 0x02<br>-#define PM1_CNT 0x04<br>-#define PM1_TMR 0x08<br>-#define PROC_CNT 0x10<br>-#define LV2 0x14<br>-#define LV3 0x15<br>-#define LV4 0x16<br>-#define PM2_CNT 0x20 // mobile only<br>-#define GPE0_STS 0x28<br>-#define GPE0_EN 0x2c<br>-#define SMI_EN 0x30<br>-#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology<br>-#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic<br>-#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic<br>-#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS<br>-#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)<br>-#define MCSMI_EN (1 << 11) // Trap microcontroller range access<br>-#define BIOS_RLS (1 << 7) // asserts SCI on bit set<br>-#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set<br>-#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#<br>-#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#<br>-#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic<br>-#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit<br>-#define EOS (1 << 1) // End of SMI (deassert SMI#)<br>-#define GBL_SMI_EN (1 << 0) // SMI# generation at all?<br>-#define SMI_STS 0x34<br>-#define ALT_GP_SMI_EN 0x38<br>-#define ALT_GP_SMI_STS 0x3a<br>-#define GPE_CNTL 0x42<br>-#define DEVACT_STS 0x44<br>-#define SS_CNT 0x50<br>-#define C3_RES 0x54<br>-<br>-/* While we read PMBASE dynamically in case it changed, let's<br>- * initialize it with a sane value<br>- */<br>-<br>-static u16 pmbase = DEFAULT_PMBASE;<br>-/**<br>- * @brief read and clear PM1_STS<br>- * @return PM1_STS register<br>- */<br>-static u16 reset_pm1_status(void)<br>-{<br>- u16 reg16;<br>-<br>- reg16 = inw(pmbase + PM1_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outw(reg16, pmbase + PM1_STS);<br>-<br>- return reg16;<br>-}<br>-<br>-static void dump_pm1_status(u16 pm1_sts)<br>-{<br>- printk(BIOS_DEBUG, "PM1_STS: ");<br>- if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");<br>- if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");<br>- if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");<br>- if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");<br>- if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");<br>- if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");<br>- if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");<br>- if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-/**<br>- * @brief read and clear SMI_STS<br>- * @return SMI_STS register<br>- */<br>-static u32 reset_smi_status(void)<br>-{<br>- u32 reg32;<br>-<br>- reg32 = inl(pmbase + SMI_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg32, pmbase + SMI_STS);<br>-<br>- return reg32;<br>-}<br>-<br>-static void dump_smi_status(u32 smi_sts)<br>-{<br>- printk(BIOS_DEBUG, "SMI_STS: ");<br>- if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");<br>- if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");<br>- if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");<br>- if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");<br>- if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");<br>- if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");<br>- if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");<br>- if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");<br>- if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");<br>- if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");<br>- if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");<br>- if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");<br>- if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");<br>- if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");<br>- if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");<br>- if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");<br>- if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");<br>- if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");<br>- if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");<br>- if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-/**<br>- * @brief read and clear GPE0_STS<br>- * @return GPE0_STS register<br>- */<br>-static u32 reset_gpe0_status(void)<br>-{<br>- u32 reg32;<br>-<br>- reg32 = inl(pmbase + GPE0_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg32, pmbase + GPE0_STS);<br>-<br>- return reg32;<br>-}<br>-<br>-static void dump_gpe0_status(u32 gpe0_sts)<br>-{<br>- int i;<br>- printk(BIOS_DEBUG, "GPE0_STS: ");<br>- for (i=31; i>= 16; i--) {<br>- if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));<br>- }<br>- if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");<br>- if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");<br>- if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");<br>- if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");<br>- if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");<br>- if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");<br>- if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");<br>- if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");<br>- if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");<br>- if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");<br>- if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");<br>- if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");<br>- if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");<br>- if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-/**<br>- * @brief read and clear TCOx_STS<br>- * @return TCOx_STS registers<br>- */<br>-static u32 reset_tco_status(void)<br>-{<br>- u32 tcobase = pmbase + 0x60;<br>- u32 reg32;<br>-<br>- reg32 = inl(tcobase + 0x04);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS<br>- if (reg32 & (1 << 18))<br>- outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS<br>-<br>- return reg32;<br>-}<br>-<br>-static void dump_tco_status(u32 tco_sts)<br>-{<br>- printk(BIOS_DEBUG, "TCO_STS: ");<br>- if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");<br>- if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");<br>- if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");<br>- if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");<br>- if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");<br>- if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");<br>- if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");<br>- if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");<br>- if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");<br>- if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");<br>- if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");<br>- if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");<br>- if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-/**<br>- * @brief Set the EOS bit<br>- */<br>-static void smi_set_eos(void)<br>-{<br>-// FIXME: disabled until SMM actually works<br>-#if 0<br>- u8 reg8;<br>-<br>- reg8 = inb(pmbase + SMI_EN);<br>- reg8 |= EOS;<br>- outb(reg8, pmbase + SMI_EN);<br>-#endif<br>-}<br>-<br>-extern uint8_t smm_relocation_start, smm_relocation_end;<br>-<br>-static void smm_relocate(void)<br>-{<br>- u32 smi_en;<br>-<br>- printk(BIOS_DEBUG, "Initializing SMM handler...");<br>-<br>- pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc;<br>- printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);<br>-<br>- smi_en = inl(pmbase + SMI_EN);<br>- if (smi_en & APMC_EN) {<br>- printk(BIOS_INFO, "SMI# handler already enabled?\n");<br>- return;<br>- }<br>-<br>- /* copy the SMM relocation code */<br>- memcpy((void *)0x38000, &smm_relocation_start,<br>- &smm_relocation_end - &smm_relocation_start);<br>-<br>- printk(BIOS_DEBUG, "\n");<br>- dump_smi_status(reset_smi_status());<br>- dump_pm1_status(reset_pm1_status());<br>- dump_gpe0_status(reset_gpe0_status());<br>- dump_tco_status(reset_tco_status());<br>-<br>- /* Enable SMI generation:<br>- * - on TCO events<br>- * - on APMC writes (io 0xb2)<br>- * - on writes to SLP_EN (sleep states)<br>- * - on writes to GBL_RLS (bios commands)<br>- * No SMIs:<br>- * - on microcontroller writes (io 0x62/0x66)<br>- */<br>- outl(smi_en | (TCO_EN | APMC_EN | SLP_SMI_EN | BIOS_EN |<br>- EOS | GBL_SMI_EN), pmbase + SMI_EN);<br>-<br>- /**<br>- * There are several methods of raising a controlled SMI# via<br>- * software, among them:<br>- * - Writes to io 0xb2 (APMC)<br>- * - Writes to the Local Apic ICR with Delivery mode SMI.<br>- *<br>- * Using the local apic is a bit more tricky. According to<br>- * AMD Family 11 Processor BKDG no destination shorthand must be<br>- * used.<br>- * The whole SMM initialization is quite a bit hardware specific, so<br>- * I'm not too worried about the better of the methods at the moment<br>- */<br>-<br>- /* raise an SMI interrupt */<br>- printk(BIOS_SPEW, " ... raise SMI#\n");<br>- outb(0x00, 0xb2);<br>-}<br>-<br>-static void smm_install(void)<br>-{<br>- /* enable the SMM memory window */<br>- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,<br>- D_OPEN | G_SMRAME | C_BASE_SEG);<br>-<br>- /* copy the real SMM handler */<br>- memcpy((void *)0xa0000, _binary_smm_start,<br>- _binary_smm_end - _binary_smm_start);<br>- wbinvd();<br>-<br>- /* close the SMM memory window and enable normal SMM */<br>- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,<br>- G_SMRAME | C_BASE_SEG);<br>-}<br>-<br>-void smm_init(void)<br>-{<br>- smm_relocate();<br>- smm_install();<br>- smi_set_eos();<br>-}<br>-<br>-void smm_init_completion(void)<br>-{<br>-}<br>-<br>-void smm_lock(void)<br>-{<br>- /* LOCK the SMM memory window and enable normal SMM.<br>- * After running this function, only a full reset can<br>- * make the SMM registers writable again.<br>- */<br>- printk(BIOS_DEBUG, "Locking SMM.\n");<br>- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,<br>- D_LCK | G_SMRAME | C_BASE_SEG);<br>-}<br>-<br>-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)<br>-{<br>- /* The GDT or coreboot table is going to live here. But a long time<br>- * after we relocated the GNVS, so this is not troublesome.<br>- */<br>- *(u32 *)0x500 = (u32)gnvs;<br>- *(u32 *)0x504 = (u32)tcg;<br>- *(u32 *)0x508 = (u32)smi1;<br>- outb(0xea, 0xb2);<br>-}<br>diff --git a/src/soc/intel/sch/smihandler.c b/src/soc/intel/sch/smihandler.c<br>deleted file mode 100644<br>index 6982f58..0000000<br>--- a/src/soc/intel/sch/smihandler.c<br>+++ /dev/null<br>@@ -1,399 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <console/console.h><br>-#include <cpu/x86/cache.h><br>-#include <cpu/x86/smm.h><br>-#include "sch.h"<br>-<br>-#define DEBUG_SMI<br>-<br>-/* I945 */<br>-#define SMRAM 0x9d<br>-#define D_OPEN (1 << 6)<br>-#define D_CLS (1 << 5)<br>-#define D_LCK (1 << 4)<br>-#define G_SMRANE (1 << 3)<br>-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))<br>-<br>-/* ICH7 */<br>-#define PM1_STS 0x00<br>-#define PM1_EN 0x02<br>-#define PM1_CNT 0x04<br>-#define PM1_TMR 0x08<br>-#define PROC_CNT 0x10<br>-#define LV2 0x14<br>-#define LV3 0x15<br>-#define LV4 0x16<br>-#define PM2_CNT 0x20 // mobile only<br>-#define GPE0_STS 0x28<br>-#define GPE0_EN 0x2c<br>-#define SMI_EN 0x30<br>-#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology<br>-#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic<br>-#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic<br>-#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS<br>-#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)<br>-#define MCSMI_EN (1 << 11) // Trap microcontroller range access<br>-#define BIOS_RLS (1 << 7) // asserts SCI on bit set<br>-#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set<br>-#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#<br>-#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#<br>-#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic<br>-#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit<br>-#define EOS (1 << 1) // End of SMI (deassert SMI#)<br>-#define GBL_SMI_EN (1 << 0) // SMI# generation at all?<br>-#define SMI_STS 0x34<br>-#define ALT_GP_SMI_EN 0x38<br>-#define ALT_GP_SMI_STS 0x3a<br>-#define GPE_CNTL 0x42<br>-#define DEVACT_STS 0x44<br>-#define SS_CNT 0x50<br>-#define C3_RES 0x54<br>-<br>-//#include "i82801gx_nvs.h"<br>-<br>-/* While we read PMBASE dynamically in case it changed, let's<br>- * initialize it with a sane value<br>- */<br>-static u16 pmbase = DEFAULT_PMBASE;<br>-<br>-// disabled because SMM doesn't actually work yet<br>-#if 0<br>-/**<br>- * @brief read and clear PM1_STS<br>- * @return PM1_STS register<br>- */<br>-static u16 reset_pm1_status(void)<br>-{<br>- u16 reg16;<br>-<br>- reg16 = inw(pmbase + PM1_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outw(reg16, pmbase + PM1_STS);<br>-<br>- return reg16;<br>-}<br>-<br>-static void dump_pm1_status(u16 pm1_sts)<br>-{<br>- printk(BIOS_DEBUG, "PM1_STS: ");<br>- if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");<br>- if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");<br>- if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");<br>- if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");<br>- if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");<br>- if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");<br>- if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");<br>- if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-/**<br>- * @brief read and clear SMI_STS<br>- * @return SMI_STS register<br>- */<br>-static u32 reset_smi_status(void)<br>-{<br>- u32 reg32;<br>-<br>- reg32 = inl(pmbase + SMI_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg32, pmbase + SMI_STS);<br>-<br>- return reg32;<br>-}<br>-<br>-static void dump_smi_status(u32 smi_sts)<br>-{<br>- printk(BIOS_DEBUG, "SMI_STS: ");<br>- if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");<br>- if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");<br>- if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");<br>- if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");<br>- if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");<br>- if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");<br>- if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");<br>- if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");<br>- if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");<br>- if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");<br>- if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");<br>- if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");<br>- if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");<br>- if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");<br>- if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");<br>- if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");<br>- if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");<br>- if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");<br>- if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");<br>- if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-<br>-/**<br>- * @brief read and clear GPE0_STS<br>- * @return GPE0_STS register<br>- */<br>-static u32 reset_gpe0_status(void)<br>-{<br>- u32 reg32;<br>-<br>- reg32 = inl(pmbase + GPE0_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg32, pmbase + GPE0_STS);<br>-<br>- return reg32;<br>-}<br>-<br>-static void dump_gpe0_status(u32 gpe0_sts)<br>-{<br>- int i;<br>- printk(BIOS_DEBUG, "GPE0_STS: ");<br>- for (i=31; i>= 16; i--) {<br>- if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));<br>- }<br>- if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");<br>- if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");<br>- if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");<br>- if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");<br>- if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");<br>- if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");<br>- if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");<br>- if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");<br>- if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");<br>- if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");<br>- if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");<br>- if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");<br>- if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");<br>- if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-<br>-/**<br>- * @brief read and clear TCOx_STS<br>- * @return TCOx_STS registers<br>- */<br>-static u32 reset_tco_status(void)<br>-{<br>- u32 tcobase = pmbase + 0x60;<br>- u32 reg32;<br>-<br>- reg32 = inl(tcobase + 0x04);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS<br>- if (reg32 & (1 << 18))<br>- outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS<br>-<br>- return reg32;<br>-}<br>-<br>-<br>-static void dump_tco_status(u32 tco_sts)<br>-{<br>- printk(BIOS_DEBUG, "TCO_STS: ");<br>- if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");<br>- if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");<br>- if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");<br>- if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");<br>- if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");<br>- if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");<br>- if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");<br>- if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");<br>- if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");<br>- if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");<br>- if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");<br>- if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");<br>- if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-#endif<br>-<br>-int southbridge_io_trap_handler(int smif)<br>-{<br>- //global_nvs_t *gnvs = (global_nvs_t *)0xc00;<br>-<br>- switch (smif) {<br>- case 0x32:<br>- printk(BIOS_DEBUG, "OS Init\n");<br>- //gnvs->smif = 0;<br>- break;<br>- default:<br>- /* Not handled */<br>- return 0;<br>- }<br>-<br>- /* On success, the IO Trap Handler returns 0<br>- * On failure, the IO Trap Handler returns a value != 0<br>- *<br>- * For now, we force the return value to 0 and log all traps to<br>- * see what's going on.<br>- */<br>- //gnvs->smif = 0;<br>- return 1; /* IO trap handled */<br>-}<br>-<br>-/**<br>- * @brief Set the EOS bit<br>- */<br>-void southbridge_smi_set_eos(void)<br>-{<br>- u8 reg8;<br>-<br>- reg8 = inb(pmbase + SMI_EN);<br>- reg8 |= EOS;<br>- outb(reg8, pmbase + SMI_EN);<br>-}<br>-<br>-/**<br>- * @brief Interrupt handler for SMI#<br>- * @param node<br>- * @param state_save<br>- */<br>-void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)<br>-{<br>-// FIXME: the necessary magic isn't available yet. the code<br>-// below is a partially adapted ICH7 version of the handler<br>-#if 0<br>- u8 reg8;<br>- u16 pmctrl;<br>- u16 pm1_sts;<br>- u32 smi_sts, gpe0_sts, tco_sts;<br>-<br>- pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc;<br>- printk(BIOS_SPEW, "SMI#: pmbase = 0x%04x\n", pmbase);<br>-<br>- /* We need to clear the SMI status registers, or we won't see what's<br>- * happening in the following calls.<br>- */<br>- smi_sts = reset_smi_status();<br>- dump_smi_status(smi_sts);<br>-<br>- if (smi_sts & (1 << 21)) { // MONITOR<br>- global_nvs_t *gnvs = (global_nvs_t *)0xc00;<br>- u32 reg32;<br>-<br>- reg32 = RCBA32(0x1e00); TRSR - Trap Status Register<br>-//#if 0<br>- /* Comment in for some useful debug */<br>- for (i=0; i<4; i++) {<br>- if (reg32 & (1 << i)) {<br>- printk(BIOS_DEBUG, " io trap #%d\n", i);<br>- }<br>- }<br>-//#endif<br>- RCBA32(0x1e00) = reg32; TRSR<br>-<br>- reg32 = RCBA32(0x1e10);<br>-<br>- if ((reg32 & 0xfffc) != 0x808) {<br>- printk(BIOS_DEBUG, " trapped io address = 0x%x\n", reg32 & 0xfffc);<br>- printk(BIOS_DEBUG, " AHBE = %x\n", (reg32 >> 16) & 0xf);<br>- printk(BIOS_DEBUG, " read/write: %s\n", (reg32 & (1 << 24)) ? "read" :<br>- "write");<br>- }<br>-<br>- if (!(reg32 & (1 << 24))) {<br>- /* Write Cycle */<br>- reg32 = RCBA32(0x1e18);<br>- printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", reg32);<br>-<br>- }<br>-<br>- if (gnvs->smif)<br>- io_trap_handler(gnvs->smif); // call function smif<br>- }<br>-<br>- if (smi_sts & (1 << 13)) { // TCO<br>- tco_sts = reset_tco_status();<br>- dump_tco_status(tco_sts);<br>-<br>- if (tco_sts & (1 << 8)) { // BIOSWR<br>- u8 bios_cntl;<br>- bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);<br>- if (bios_cntl & 1) {<br>- /* BWE is RW, so the SMI was caused by a<br>- * write to BWE, not by a write to the BIOS<br>- */<br>-<br>- /* This is the place where we notice someone<br>- * is trying to tinker with the BIOS. We are<br>- * trying to be nice and just ignore it. A more<br>- * resolute answer would be to power down the<br>- * box.<br>- */<br>- printk(BIOS_DEBUG, "Switching back to RO\n");<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));<br>- } /* No else for now? */<br>- }<br>- }<br>-<br>- if (smi_sts & (1 << 8)) { // PM1<br>- pm1_sts = reset_pm1_status();<br>- dump_pm1_status(pm1_sts);<br>- }<br>-<br>- if (smi_sts & (1 << 9)) { // GPE0<br>- gpe0_sts = reset_gpe0_status();<br>- dump_gpe0_status(gpe0_sts);<br>- }<br>-<br>- if (smi_sts & (1 << 5)) { // APM<br>- /* Emulate B2 register as the FADT / Linux expects it */<br>-<br>- reg8 = inb(0xb2);<br>- switch (reg8) {<br>- case ACPI_DISABLE:<br>- pmctrl = inw(pmbase + 0x04);<br>- pmctrl |= (1 << 0);<br>- outw(pmctrl, pmbase + 0x04);<br>- printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");<br>- break;<br>- case ACPI_ENABLE:<br>- pmctrl = inw(pmbase + 0x04);<br>- pmctrl &= ~(1 << 0);<br>- outw(pmctrl, pmbase + 0x04);<br>- printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");<br>- break;<br>- }<br>- }<br>-<br>- if (smi_sts & (1 << 4)) { // SLP_SMI<br>- u32 reg32;<br>-<br>- /* First, disable further SMIs */<br>- reg8 = inb(pmbase + SMI_EN);<br>- reg8 &= ~SLP_SMI_EN;<br>- outb(reg8, pmbase + SMI_EN);<br>-<br>- /* Next, do the deed, we should change<br>- * power on after power loss bits here<br>- * if we're going to S5<br>- */<br>-<br>- /* Write back to the SLP register to cause the<br>- * originally intended event again. We need to set BIT13<br>- * (SLP_EN) though to make the sleep happen.<br>- */<br>- reg32 = inl(pmbase + 0x04);<br>- printk(BIOS_DEBUG, "SMI#: SLP = 0x%08x\n", reg32);<br>- printk(BIOS_DEBUG, "SMI#: Powering off.\n");<br>- outl(reg32 | (1 << 13), pmbase + 0x04);<br>- }<br>-#endif<br>-}<br>diff --git a/src/soc/intel/sch/south.c b/src/soc/intel/sch/south.c<br>deleted file mode 100644<br>index b096ab6..0000000<br>--- a/src/soc/intel/sch/south.c<br>+++ /dev/null<br>@@ -1,22 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-<br>-struct chip_operations southbridge_intel_sch_ops = {<br>- CHIP_NAME("Intel SCH Southbridge")<br>-};<br>diff --git a/src/soc/intel/sch/usb.c b/src/soc/intel/sch/usb.c<br>deleted file mode 100644<br>index a7ada4b..0000000<br>--- a/src/soc/intel/sch/usb.c<br>+++ /dev/null<br>@@ -1,87 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2010 coresystems GmbH<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-<br>-static void usb_init(struct device *dev)<br>-{<br>- u32 reg32;<br>-<br>- /* USB Specification says the device must be Bus Master. */<br>- printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");<br>-<br>- reg32 = pci_read_config32(dev, PCI_COMMAND);<br>- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);<br>- /* Disable clock gating. */<br>- reg32 = pci_read_config32(dev, 0xFC);<br>- reg32 |= (1 << 2);<br>- pci_write_config32(dev, 0xFC, reg32);<br>- pci_write_config8(dev, 0xF8, 0x86);<br>- pci_write_config8(dev, 0xF9, 0x0F);<br>- pci_write_config8(dev, 0xFA, 0x06);<br>- reg32 = pci_read_config32(dev, 0x4);<br>- printk(BIOS_DEBUG, "PCI_COMMAND %x.\n", reg32);<br>- reg32 = pci_read_config32(dev, 0x20);<br>- printk(BIOS_DEBUG, "PCI_BASE %x.\n", reg32);<br>- reg32 = pci_read_config32(dev, 0xFC);<br>- printk(BIOS_DEBUG, "PCI_FD %x.\n", reg32);<br>- printk(BIOS_DEBUG, "done.\n");<br>-}<br>-<br>-static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- if (!vendor || !device) {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- pci_read_config32(dev, PCI_VENDOR_ID));<br>- } else {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- }<br>-}<br>-<br>-static struct pci_operations usb_pci_ops = {<br>- .set_subsystem = usb_set_subsystem,<br>-};<br>-<br>-static struct device_operations usb_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = usb_init,<br>- .scan_bus = 0,<br>- .ops_pci = &usb_pci_ops,<br>-};<br>-<br>-static const struct pci_driver sch_usb0 __pci_driver = {<br>- .ops = &usb_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x8114,<br>-};<br>-<br>-static const struct pci_driver sch_usb1 __pci_driver = {<br>- .ops = &usb_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x8115,<br>-};<br>-<br>-static const struct pci_driver sch_usb2 __pci_driver = {<br>- .ops = &usb_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x8116,<br>-};<br>diff --git a/src/soc/intel/sch/usb_client.c b/src/soc/intel/sch/usb_client.c<br>deleted file mode 100644<br>index 02f5b82..0000000<br>--- a/src/soc/intel/sch/usb_client.c<br>+++ /dev/null<br>@@ -1,62 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <arch/io.h><br>-<br>-static void usb_client_init(struct device *dev)<br>-{<br>- u32 reg32;<br>-<br>- printk(BIOS_DEBUG, "USB Client: Setting up controller.. ");<br>- reg32 = pci_read_config32(dev, PCI_COMMAND);<br>- reg32 |= PCI_COMMAND_MASTER;<br>- reg32 |= PCI_COMMAND_MEMORY;<br>- pci_write_config32(dev, PCI_COMMAND, reg32);<br>- printk(BIOS_DEBUG, "done.\n");<br>-}<br>-<br>-static void usb_client_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- if (!vendor || !device) {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- pci_read_config32(dev, PCI_VENDOR_ID));<br>- } else {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- }<br>-}<br>-<br>-static struct pci_operations lops_pci = {<br>- .set_subsystem = &usb_client_set_subsystem,<br>-};<br>-<br>-static struct device_operations usb_client_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = usb_client_init,<br>- .scan_bus = 0,<br>- .ops_pci = &lops_pci,<br>-};<br>-<br>-static const struct pci_driver sch_usb_client __pci_driver = {<br>- .ops = &usb_client_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x8118,<br>-};<br>diff --git a/src/soc/intel/sch/usb_ehci.c b/src/soc/intel/sch/usb_ehci.c<br>deleted file mode 100644<br>index 8191d0a..0000000<br>--- a/src/soc/intel/sch/usb_ehci.c<br>+++ /dev/null<br>@@ -1,91 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2010 coresystems GmbH<br>- * Copyright (C) 2009-2010 iWave Systems<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <arch/io.h><br>-<br>-static void usb_ehci_init(struct device *dev)<br>-{<br>- u32 reg32;<br>-<br>- printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");<br>- reg32 = pci_read_config32(dev, PCI_COMMAND);<br>- reg32 |= PCI_COMMAND_MASTER;<br>- pci_write_config32(dev, PCI_COMMAND, reg32);<br>- /* Disable clock gating */<br>-#if 0<br>- reg32 = pci_read_config32(dev, 0xc0);<br>- reg32 |= (1 << 2);<br>- pci_write_config32(dev, 0xc0, reg32);<br>-#endif<br>- // pci_write_config32(dev, 0x3c, 0x17);<br>- reg32 = pci_read_config32(dev, 0xFC);<br>- reg32 |= (1 << 28);<br>- pci_write_config32(dev, 0xFC, reg32);<br>-<br>- reg32 = pci_read_config32(dev, 0x4);<br>- printk(BIOS_DEBUG, "PCI_COMMAND %x.\n", reg32);<br>- reg32 = pci_read_config32(dev, 0x20);<br>- printk(BIOS_DEBUG, "PCI_BASE %x.\n", reg32);<br>- reg32 = pci_read_config32(dev, 0xC0);<br>- printk(BIOS_DEBUG, "PCI_FD %x.\n", reg32);<br>- printk(BIOS_DEBUG, "done.\n");<br>-}<br>-<br>-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,<br>- unsigned device)<br>-{<br>- u8 access_cntl;<br>-<br>- access_cntl = pci_read_config8(dev, 0x80);<br>-<br>- /* Enable writes to protected registers. */<br>- pci_write_config8(dev, 0x80, access_cntl | 1);<br>-<br>- if (!vendor || !device) {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- pci_read_config32(dev, PCI_VENDOR_ID));<br>- } else {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- }<br>-<br>- /* Restore protection. */<br>- pci_write_config8(dev, 0x80, access_cntl);<br>-}<br>-<br>-static struct pci_operations lops_pci = {<br>- .set_subsystem = &usb_ehci_set_subsystem,<br>-};<br>-<br>-static struct device_operations usb_ehci_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = usb_ehci_init,<br>- .scan_bus = 0,<br>- .ops_pci = &lops_pci,<br>-};<br>-<br>-static const struct pci_driver sch_usb_ehci __pci_driver = {<br>- .ops = &usb_ehci_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x8117,<br>-};<br></pre><p>To view, visit <a href="https://review.coreboot.org/22027">change 22027</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22027"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ida0570988a23fd0d13c6fcbe54f94ab0668c9eae </div>
<div style="display:none"> Gerrit-Change-Number: 22027 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>