<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22025">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">AMD GX2 boards & chips: Remove - using LATE_CBMEM_INIT<br><br>All boards and chips that are still using LATE_CBMEM_INIT are being<br>removed as previously discussed.<br><br>If these boards and chips are updated to not use LATE_CBMEM_INIT, they<br>can be restored to the active codebase from the 4.8 branch.<br><br>chips:<br>cpu/amd/geode_gx2<br>northbridge/amd/gx2<br>southbridge/amd/cs5535<br><br>Mainboards:<br>mainboard/amd/rumba<br>mainboard/lippert/frontrunner<br>mainboard/wyse/s50<br><br>Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c<br>Signed-off-by: Martin Roth <gaumless@gmail.com><br>---<br>M src/cpu/amd/Kconfig<br>M src/cpu/amd/Makefile.inc<br>D src/cpu/amd/geode_gx2/Kconfig<br>D src/cpu/amd/geode_gx2/Makefile.inc<br>D src/cpu/amd/geode_gx2/cache_as_ram.inc<br>D src/cpu/amd/geode_gx2/cpubug.c<br>D src/cpu/amd/geode_gx2/cpureginit.c<br>D src/cpu/amd/geode_gx2/geode_gx2_init.c<br>D src/cpu/amd/geode_gx2/syspreinit.c<br>D src/mainboard/amd/rumba/Kconfig<br>D src/mainboard/amd/rumba/Kconfig.name<br>D src/mainboard/amd/rumba/board_info.txt<br>D src/mainboard/amd/rumba/cmos.layout<br>D src/mainboard/amd/rumba/devicetree.cb<br>D src/mainboard/amd/rumba/irq_tables.c<br>D src/mainboard/amd/rumba/mainboard.c<br>D src/mainboard/amd/rumba/romstage.c<br>D src/mainboard/lippert/frontrunner/Kconfig<br>D src/mainboard/lippert/frontrunner/Kconfig.name<br>D src/mainboard/lippert/frontrunner/board_info.txt<br>D src/mainboard/lippert/frontrunner/cmos.layout<br>D src/mainboard/lippert/frontrunner/devicetree.cb<br>D src/mainboard/lippert/frontrunner/irq_tables.c<br>D src/mainboard/lippert/frontrunner/romstage.c<br>D src/mainboard/wyse/s50/Kconfig<br>D src/mainboard/wyse/s50/Kconfig.name<br>D src/mainboard/wyse/s50/board_info.txt<br>D src/mainboard/wyse/s50/cmos.layout<br>D src/mainboard/wyse/s50/devicetree.cb<br>D src/mainboard/wyse/s50/irq_tables.c<br>D src/mainboard/wyse/s50/romstage.c<br>D src/northbridge/amd/gx2/Kconfig<br>D src/northbridge/amd/gx2/Makefile.inc<br>D src/northbridge/amd/gx2/grphinit.c<br>D src/northbridge/amd/gx2/northbridge.c<br>D src/northbridge/amd/gx2/northbridge.h<br>D src/northbridge/amd/gx2/northbridgeinit.c<br>D src/northbridge/amd/gx2/pll_reset.c<br>D src/northbridge/amd/gx2/raminit.c<br>D src/northbridge/amd/gx2/raminit.h<br>D src/southbridge/amd/cs5535/Kconfig<br>D src/southbridge/amd/cs5535/Makefile.inc<br>D src/southbridge/amd/cs5535/chip.h<br>D src/southbridge/amd/cs5535/chipsetinit.c<br>D src/southbridge/amd/cs5535/cs5535.c<br>D src/southbridge/amd/cs5535/cs5535.h<br>D src/southbridge/amd/cs5535/early_setup.c<br>D src/southbridge/amd/cs5535/early_smbus.c<br>D src/southbridge/amd/cs5535/ide.c<br>D src/southbridge/amd/cs5535/smbus.h<br>50 files changed, 0 insertions(+), 4,532 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/22025/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig<br>index 23e4deb..649363c 100644<br>--- a/src/cpu/amd/Kconfig<br>+++ b/src/cpu/amd/Kconfig<br>@@ -14,7 +14,6 @@<br> <br> source src/cpu/amd/model_fxx/Kconfig<br> source src/cpu/amd/family_10h-family_15h/Kconfig<br>-source src/cpu/amd/geode_gx2/Kconfig<br> source src/cpu/amd/geode_lx/Kconfig<br> <br> source src/cpu/amd/agesa/Kconfig<br>diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc<br>index da6862d..be7e3bc 100644<br>--- a/src/cpu/amd/Makefile.inc<br>+++ b/src/cpu/amd/Makefile.inc<br>@@ -10,7 +10,6 @@<br> subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32<br> subdirs-$(CONFIG_CPU_AMD_SOCKET_FM2_NON_AGESA) += socket_FM2<br> subdirs-$(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA) += socket_G34<br>-subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2<br> subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx<br> subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1<br> <br>diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig<br>deleted file mode 100644<br>index c7745ec..0000000<br>--- a/src/cpu/amd/geode_gx2/Kconfig<br>+++ /dev/null<br>@@ -1,69 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2010 coresystems GmbH<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-config CPU_AMD_GEODE_GX2<br>- bool<br>- select ARCH_BOOTBLOCK_X86_32<br>- select ARCH_VERSTAGE_X86_32<br>- select ARCH_ROMSTAGE_X86_32<br>- select ARCH_RAMSTAGE_X86_32<br>-<br>-if CPU_AMD_GEODE_GX2<br>-<br>-config CPU_SPECIFIC_OPTIONS<br>- def_bool y<br>- select NO_MMCONF_SUPPORT<br>-<br>-config DCACHE_RAM_BASE<br>- hex<br>- default 0xc8000<br>-<br>-config DCACHE_RAM_SIZE<br>- hex<br>- default 0x04000<br>-<br>-config DCACHE_BSP_STACK_SIZE<br>- hex<br>- default 0x1000<br>-<br>-config DCACHE_BSP_STACK_SLUSH<br>- hex<br>- default 0x1000<br>-<br>-config DCACHE_AP_STACK_SIZE<br>- hex<br>- default 0x400<br>-<br>-config GEODE_VSA<br>- bool<br>- default y<br>-<br>-config GEODE_VSA_FILE<br>- bool "Add a VSA image"<br>- help<br>- Select this option if you have an AMD Geode GX2 vsa that you would<br>- like to add to your ROM.<br>-<br>- You will be able to specify the location and file name of the<br>- image later.<br>-<br>-config VSA_FILENAME<br>- string "AMD Geode GX2 VSA path and filename"<br>- depends on GEODE_VSA_FILE<br>- default "gpl_vsa_gx_102.bin"<br>- help<br>- The path and filename of the file to use as VSA.<br>-<br>-endif # CPU_AMD_GEODE_GX2<br>diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc<br>deleted file mode 100644<br>index 1580f74..0000000<br>--- a/src/cpu/amd/geode_gx2/Makefile.inc<br>+++ /dev/null<br>@@ -1,14 +0,0 @@<br>-subdirs-y += ../../x86/tsc<br>-subdirs-y += ../../x86/lapic<br>-subdirs-y += ../../x86/cache<br>-subdirs-y += ../../x86/smm<br>-<br>-ramstage-y += geode_gx2_init.c<br>-ramstage-y += cpubug.c<br>-<br>-cpu_incs-y += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc<br>-<br>-cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa<br>-vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa<br>-vsa-type = stage<br>-vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty/blobs repository)<br>diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc<br>deleted file mode 100644<br>index 049d077..0000000<br>--- a/src/cpu/amd/geode_gx2/cache_as_ram.inc<br>+++ /dev/null<br>@@ -1,198 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007 Advanced Micro Devices, Inc.<br>- * Copyright (C) 2010 Nils Jacobs<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#define GX2_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */<br>-#define GX2_STACK_END GX2_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)<br>-<br>-#define GX2_NUM_CACHELINES 0x080 /* there are 128lines per way */<br>-#define GX2_CACHELINE_SIZE 0x020 /* there are 32bytes per line */<br>-#define GX2_CACHEWAY_SIZE (GX2_NUM_CACHELINES * GX2_CACHELINE_SIZE)<br>-#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */<br>-#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */<br>-<br>-#include <cpu/amd/gx2def.h><br>-#include <cpu/x86/post_code.h><br>-<br>-/*<br>- * DCacheSetup<br>- *<br>- * Setup data cache for use as RAM for a stack.<br>- *<br>- * Max. size data cache =0x4000 (16KB)<br>- */<br>-DCacheSetup:<br>- /* Save the BIST result */<br>- movl %eax, %ebx<br>-<br>- invd<br>- /* set cache properties */<br>- movl $CPU_RCONF_DEFAULT, %ecx<br>- rdmsr<br>- movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */<br>- wrmsr<br>-<br>- /* in GX2 DCDIS is set after POR which disables the cache..., clear this bit */<br>- movl $CPU_DM_CONFIG0, %ecx<br>- rdmsr<br>- andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */<br>- wrmsr<br>-<br>- /* Get cleaned up. */<br>- xorl %edi, %edi<br>- xorl %esi, %esi<br>- xorl %ebp, %ebp<br>-<br>- /* DCache Ways0 through Ways3 will be tagged for GX2_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */<br>- /* remember, there is NO stack yet... */<br>-<br>- /* Tell cache we want to fill WAY 0 starting at the top */<br>- xorl %edx, %edx<br>- xorl %eax, %eax<br>- movl $CPU_DC_INDEX, %ecx<br>- wrmsr<br>-<br>- /* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */<br>- movl $GX2_STACK_BASE, %ebp /* init to start address */<br>- orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */<br>-<br>- /* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */<br>- movl $GX2_NUM_CACHELINES, %edi<br>-DCacheSetupFillWay:<br>-<br>- /* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */<br>- /* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */<br>- movw $0x04, %si<br>- xorl %edx, %edx<br>- xorl %eax, %eax<br>- movl $CPU_DC_DATA, %ecx<br>-DCacheSetup_quadWordLoop:<br>- wrmsr<br>- decw %si<br>- jnz DCacheSetup_quadWordLoop<br>-<br>- /* Set the tag for this line,need to do this for every new cache line to validate it! */<br>- /* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */<br>- xorl %edx, %edx<br>- movl %ebp, %eax<br>- movl $CPU_DC_TAG, %ecx<br>- wrmsr<br>-<br>- /* switch to next line */<br>- /* lines are in Bits8:2 */<br>- /* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */<br>- movl $CPU_DC_INDEX, %ecx<br>- rdmsr<br>- addl $0x04, %eax /* inc DC_LINE. TODO: prob. would be more elegant to calc. this from counter var edi... */<br>- wrmsr<br>-<br>- decl %edi<br>- jnz DCacheSetupFillWay<br>-<br>- /* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */<br>- addl $GX2_CACHEWAY_SIZE, %ebp<br>- cmpl $GX2_STACK_END, %ebp<br>- jge leave_DCacheSetup<br>- movl $GX2_NUM_CACHELINES, %edi<br>-<br>- /* switch to next way */<br>- movl $CPU_DC_INDEX, %ecx<br>- rdmsr<br>- addl $0x01, %eax<br>- andl $0xFFFFFE03, %eax /* lets be sure: reset line index Bits8:2 */<br>- wrmsr<br>-<br>- jmp DCacheSetupFillWay<br>-<br>-leave_DCacheSetup:<br>- xorl %edi, %edi<br>- xorl %esi, %esi<br>- xorl %ebp, %ebp<br>-<br>- /* Disable the cache, but ... DO NOT INVALIDATE the tags. */<br>- /* Memory reads and writes will all hit in the cache. */<br>- /* Cache updates and memory write-backs will not occur ! */<br>- movl %cr0, %eax<br>- orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */<br>- movl %eax, %cr0<br>-<br>- /* Now point sp to the cached stack. */<br>- /* The stack will be fully functional at this location. No system memory is required at all ! */<br>- /* set up the stack pointer */<br>- movl $GX2_STACK_END, %eax<br>- movl %eax, %esp<br>-<br>- /* test the stack*/<br>- movl $0x0F0F05A5A, %edx<br>- pushl %edx<br>- popl %ecx<br>- cmpl %ecx, %edx<br>- je DCacheSetupGood<br>-<br>- post_code(0xc5)<br>-DCacheSetupBad:<br>- hlt /* issues */<br>- jmp DCacheSetupBad<br>-DCacheSetupGood:<br>- /* Go do early init and memory setup */<br>-<br>- /* Restore the BIST result */<br>- movl %ebx, %eax<br>- movl %esp, %ebp<br>- pushl %eax<br>-<br>- post_code(0x23)<br>-<br>- /* Call romstage.c main function */<br>- call mainboard_romstage_entry<br>-<br>-done_cache_as_ram_main:<br>-<br>- /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */<br>-<br>- push %edi<br>- mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx<br>- push %esi<br>- mov $(CONFIG_DCACHE_RAM_BASE),%edi<br>- mov %edi,%esi<br>- cld<br>- rep movsl %ds:(%esi),%es:(%edi)<br>- pop %esi<br>- pop %edi<br>-<br>- /* Clear the cache out to RAM */<br>- wbinvd<br>- /* re-enable the cache */<br>- movl %cr0, %eax<br>- xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */<br>- movl %eax, %cr0<br>-<br>-__main:<br>- post_code(POST_PREPARE_RAMSTAGE)<br>-<br>- /* TODO For suspend/resume low memory needs backup store. */<br>-<br>- cld /* clear direction flag */<br>-<br>- /* copy coreboot from it's initial load location to<br>- * the location it is compiled to run at.<br>- * Normally this is copying from FLASH ROM to RAM.<br>- */<br>- call copy_and_run<br>-<br>-.Lhlt:<br>- post_code(POST_DEAD_CODE)<br>- hlt<br>- jmp .Lhlt<br>diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c<br>deleted file mode 100644<br>index cf2b79d..0000000<br>--- a/src/cpu/amd/geode_gx2/cpubug.c<br>+++ /dev/null<br>@@ -1,359 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <device/device.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include <cpu/amd/gx2def.h><br>-#include <cpu/x86/msr.h><br>-#include <cpu/x86/cache.h><br>-<br>-#if 0<br>-void bug645(void)<br>-{<br>- msr_t msr;<br>- rdmsr(CPU_ID_CONFIG);<br>- msr.whatever |= ID_CONFIG_SERIAL_SET;<br>- wrmsr(msr);<br>-}<br>-<br>-void bug573(void)<br>-{<br>- msr_t msr;<br>- msr = rdmsr(MC_GLD_MSR_PM);<br>- msr.eax &= 0xfff3;<br>- wrmsr(MC_GLD_MSR_PM);<br>-}<br>-#endif<br>-<br>-/* pcideadlock<br>- *<br>- * Bugtool #465 and #609<br>- * PCI cache deadlock<br>- * There is also fix code in cache and PCI functions. This bug is very is pervasive.<br>- */<br>-static void pcideadlock(void)<br>-{<br>- msr_t msr;<br>-<br>- /* forces serialization of all load misses. Setting this bit prevents the<br>- * DM pipe from backing up if a read request has to be held up waiting<br>- * for PCI writes to complete.<br>- */<br>- msr = rdmsr(CPU_DM_CONFIG0);<br>- msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);<br>- msr.hi |= (2 << DM_CONFIG0_UPPER_WSREQ_SHIFT);<br>- msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;<br>- wrmsr(CPU_DM_CONFIG0, msr);<br>-<br>- /* interlock instruction fetches to WS regions with data accesses.<br>- * This prevents an instruction fetch from going out to PCI if the<br>- * data side is about to make a request.<br>- */<br>- msr = rdmsr(CPU_IM_CONFIG);<br>- msr.lo |= IM_CONFIG_LOWER_QWT_SET;<br>- wrmsr(CPU_IM_CONFIG, msr);<br>-<br>- /* write serialize memory hole to PCI. Need to unWS when something is<br>- * shadowed regardless of cachablility.<br>- */<br>- msr.lo = 0x021212121;<br>- msr.hi = 0x021212121;<br>- wrmsr( CPU_RCONF_A0_BF, msr);<br>- wrmsr( CPU_RCONF_C0_DF, msr);<br>- wrmsr( CPU_RCONF_E0_FF, msr);<br>-}<br>-<br>-/* CPUbug784<br>- *<br>- * Bugtool #784 + #792<br>- *<br>- * Fix CPUID instructions for < 3.0 CPUs<br>- */<br>-static void bug784(void)<br>-{<br>- msr_t msr;<br>- //static char *name = "Geode by NSC";<br>-<br>- /* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you<br>- * would do this -- the OS can figure this type of stuff out!<br>- */<br>- msr = rdmsr(0x3006);<br>- msr.hi = 0x646f6547;<br>- wrmsr(0x3006, msr);<br>-<br>- msr = rdmsr(0x3007);<br>- msr.hi = 0x79622065;<br>- msr.lo = 0x43534e20;<br>- wrmsr(0x3007, msr);<br>-<br>- msr = rdmsr(0x3002);<br>- wrmsr(0x3008, msr);<br>-<br>- /* More CPUID to match AMD better. #792*/<br>- msr = rdmsr(0x3009);<br>- msr.hi = 0x0C0C0A13D;<br>- msr.lo = 0x00000000;<br>- wrmsr(0x3009, msr);<br>-}<br>-<br>-/* cpubug 1398: enable MC if we KNOW we have DDR*/<br>-<br>-/* CPUbugIAENG1398<br>- *<br>- * ClearQuest #IAENG1398<br>- * The MC can not be enabled with SDR memory but can for DDR. Enable for<br>- * DDR here if the setup token is "Default"<br>- * Add this back to core by default once 2.0 CPUs are not supported.<br>- */<br>-static void eng1398(void)<br>-{<br>- msr_t msr;<br>-<br>- msr = rdmsr(MSR_GLCP+0x17);<br>- if ((msr.lo & 0xff) <= CPU_REV_2_0) {<br>- msr = rdmsr(GLCP_SYS_RSTPLL);<br>- if (msr.lo & (1 << RSTPPL_LOWER_SDRMODE_SHIFT))<br>- return;<br>- }<br>-<br>- /* no CMOS/NVRAM to check, so enable MC Clock Gating */<br>- msr = rdmsr(MC_GLD_MSR_PM);<br>- msr.lo |= 3; /* enable MC clock gating.*/<br>- wrmsr(MC_GLD_MSR_PM, msr);<br>-}<br>-<br>-/* CPUbugIAENG2900<br>- *<br>- * Clear Quest IAENG00002900, VSS 118.150<br>- *<br>- * BTB issue causes blue screen in windows, but the fix is required<br>- * for all operating systems.<br>- */<br>-static void eng2900(void)<br>-{<br>- msr_t msr;<br>-<br>- printk(BIOS_DEBUG, "CPU_BUG:%s\n", __func__);<br>- /* Clear bit 43, disables the sysenter/sysexit in CPUID3 */<br>- msr = rdmsr(0x3003);<br>- msr.hi &= 0xFFFFF7FF;<br>- wrmsr(0x3003, msr);<br>-<br>- /* change this value to zero if you need to disable this BTB SWAPSiF. */<br>- if (1) {<br>-<br>- /* Disable enable_actions in DIAGCTL while setting up GLCP */<br>- msr.hi = 0;<br>- msr.lo = 0;<br>- wrmsr(MSR_GLCP + 0x005f, msr);<br>-<br>- /* Changing DBGCLKCTL register to GeodeLink */<br>- msr.hi = 0;<br>- msr.lo = 0;<br>- wrmsr(MSR_GLCP + 0x0016, msr);<br>-<br>- msr.hi = 0;<br>- msr.lo = 2;<br>- wrmsr(MSR_GLCP + 0x0016, msr);<br>-<br>- /* The code below sets up the CPU to stall for 4 GeodeLink<br>- * clocks when CPU is snooped. Because setting XSTATE to 0<br>- * overrides any other XSTATE action, the code will always<br>- * stall for 4 GeodeLink clocks after a snoop request goes<br>- * away even if it occurred a clock or two later than a<br>- * different snoop; the stall signal will never 'glitch high'<br>- * for only one or two CPU clocks with this code.<br>- */<br>-<br>- /* Send mb0 port 3 requests to upper GeodeLink diag bits<br>- [63:32] */<br>- msr.hi = 0;<br>- msr.lo = 0x80338041;<br>- wrmsr(MSR_GLIU0 + 0x2005, msr);<br>-<br>- /* set5m watches request ready from mb0 to CPU (snoop) */<br>- msr.hi = 0x5ad68000;<br>- msr.lo = 0;<br>- wrmsr(MSR_GLCP + 0x0045, msr);<br>-<br>- /* SET4M will be high when state is idle (XSTATE=11) */<br>- msr.hi = 0;<br>- msr.lo = 0x0140;<br>- wrmsr(MSR_GLCP + 0x0044, msr);<br>-<br>- /* SET5n to watch for processor stalled state */<br>- msr.hi = 0x2000;<br>- msr.lo = 0;<br>- wrmsr(MSR_GLCP + 0x004D, msr);<br>-<br>- /* Writing action number 13: XSTATE=0 to occur when CPU is<br>- snooped unless we're stalled */<br>- msr.hi = 0;<br>- msr.lo = 0x00400000;<br>- wrmsr(MSR_GLCP + 0x0075, msr);<br>-<br>- /* Writing action number 11: inc XSTATE every GeodeLink clock<br>- unless we're idle */<br>- msr.hi = 0;<br>- msr.lo = 0x30000;<br>- wrmsr(MSR_GLCP + 0x0073, msr);<br>-<br>- /* Writing action number 5: STALL_CPU_PIPE when exiting idle<br>- state or not in idle state */<br>- msr.hi = 0;<br>- msr.lo = 0x00430000;<br>- wrmsr(MSR_GLCP + 0x006D, msr);<br>-<br>- /* Writing DIAGCTL Register to enable the stall action and to<br>- let set5m watch the upper GeodeLink diag bits. */<br>- msr.hi = 0;<br>- msr.lo = 0x80004000;<br>- wrmsr(MSR_GLCP + 0x005f, msr);<br>- }<br>-}<br>-<br>-static void bug118253(void)<br>-{<br>- /* GLPCI PIO Post Control shouldn't be enabled */<br>- msr_t msr;<br>-<br>- msr = rdmsr(GLPCI_SPARE);<br>- msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;<br>- wrmsr(GLPCI_SPARE, msr);<br>-}<br>-<br>-static void bug118339(void)<br>-{<br>- /* per AMD, do this always */<br>- msr_t msr = {0,0};<br>- int msrnum;<br>-<br>- /* Disable enable_actions in DIAGCTL while setting up GLCP */<br>- wrmsr(MSR_GLCP + 0x005f, msr);<br>-<br>- /* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */<br>- msrnum = MSR_GLCP + 0x042;<br>- /* msr.hi = 2d6b8000h; */<br>- msr.hi = 0x596b8000;<br>- msr.lo = 0x00000a00;<br>- wrmsr(msrnum, msr);<br>-<br>- /* SET3M fires if MBUS changed and VG pri is odd */<br>- msrnum = MSR_GLCP + 0x043;<br>- msr.hi = 0x596b8040;<br>- msr.lo = 0;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Put VG request data on lower diag bus */<br>- msrnum = MSR_GLIU0 + 0x2005;<br>- msr.hi = 0;<br>- msr.lo = 0x80338041;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Increment Y state if SET3M if true */<br>- msrnum = MSR_GLCP + 0x074;<br>- msr.hi = 0;<br>- msr.lo = 0x0000c000;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Set up MBUS action to PRI=3 read of MBIU */<br>- msrnum = MSR_GLCP + 0x020;<br>- msr.hi = 0x0000d863;<br>- msr.lo = 0x20002000;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */<br>- msrnum = MSR_GLCP + 0x071;<br>- msr.hi = 0;<br>- msr.lo = 0x00000c00;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Writing DIAGCTL */<br>- msrnum = MSR_GLCP + 0x005f;<br>- msr.hi = 0;<br>- msr.lo = 0x80004000;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled<br>- * As per Todd Roberts in PBz1094 and PBz1095<br>- * Moved from CPUREG to CPUBUG per Tom Sylla<br>- */<br>- msrnum = 0x04C000042; /* GLCP SETMCTL Register */<br>- msr = rdmsr(msrnum);<br>- msr.hi |= 8; /* Bit 35 = MCP_IN */<br>- wrmsr(msrnum, msr);<br>-}<br>-<br>-<br>-<br>-/* DisableMemoryReorder<br>- *<br>- * PBZ 3659:<br>- * The MC reordered transactions incorrectly and breaks coherency.<br>- * Disable reordering and take a potential performance hit.<br>- * This is safe to do here and not in MC init since there is nothing<br>- * to maintain coherency with and the cache is not enabled yet.<br>- */<br>-static void disablememoryreadorder(void)<br>-{<br>- msr_t msr;<br>-<br>- msr = rdmsr(MC_CF8F_DATA);<br>- msr.hi |= CF8F_UPPER_REORDER_DIS_SET;<br>- wrmsr(MC_CF8F_DATA, msr);<br>-}<br>-<br>-void cpubug(void)<br>-{<br>- msr_t msr;<br>- int rev;<br>-<br>- msr = rdmsr(GLCP_CHIP_REVID);<br>-<br>- rev = msr.lo & 0xff;<br>- if (rev < 0x20) {<br>- printk(BIOS_ERR, "%s: rev < 0x20! bailing!\n", __func__);<br>- return;<br>- }<br>- printk(BIOS_DEBUG, "Doing cpubug fixes for rev 0x%x\n", rev);<br>- switch(rev)<br>- {<br>- case 0x20:<br>- pcideadlock();<br>- eng1398();<br>- /* cs 5530 bug; ignore<br>- bug752();<br>- */<br>- break;<br>- case 0x21:<br>- pcideadlock();<br>- eng1398();<br>- eng2900();<br>- bug118339();<br>- break;<br>- case 0x22:<br>- case 0x30:<br>- break;<br>- default:<br>- printk(BIOS_ERR, "unknown rev %x, bailing\n", rev);<br>- return;<br>- }<br>- bug784();<br>- bug118253();<br>- disablememoryreadorder();<br>- printk(BIOS_DEBUG, "Done cpubug fixes\n");<br>-}<br>diff --git a/src/cpu/amd/geode_gx2/cpureginit.c b/src/cpu/amd/geode_gx2/cpureginit.c<br>deleted file mode 100644<br>index 83d0097..0000000<br>--- a/src/cpu/amd/geode_gx2/cpureginit.c<br>+++ /dev/null<br>@@ -1,142 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-<br>-/* cpuRegInit */<br>-void cpuRegInit (void)<br>-{<br>- int msrnum;<br>- msr_t msr;<br>- /* The following is only for diagnostics mode; do not use for OLPC */<br>- if (0) {<br>- /* Set Diagnostic Mode */<br>- msrnum = CPU_GLD_MSR_DIAG;<br>- msr.hi = 0;<br>- msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Set up GLCP to grab BTM data. */<br>- msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */<br>- msr.hi = 0x0;<br>- msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */<br>- wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */<br>-<br>- /* Turn off debug clock */<br>- msrnum = GLCP_DBGCLKCTL; /* DBG_CLK_CTL */<br>- msr.lo = 0x00; /* No clock */<br>- msr.hi = 0x00;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Set debug clock to CPU */<br>- msrnum = GLCP_DBGCLKCTL; /* DBG_CLK_CTL */<br>- msr.lo = 0x01; /* CPU CLOCK */<br>- msr.hi = 0x00;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Set fifo ctl to BTM bits wide */<br>- msrnum = GLCP_FIFOCTL; /* FIFO_CTL */<br>- msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit) */<br>- wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0) */<br>- /* Bit [19] sets it up in slow data mode. */<br>-<br>- /* enable fifo loading - BTM sizing will constrain */<br>- /* only valid BTM packets to load - this action should always be on */<br>- msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo */<br>- msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger */<br>- msr.hi = 0x000000000;<br>- wrmsr(msrnum, msr);<br>-<br>- /* start storing diag data in the fifo */<br>- msrnum = 0x04C00005F; /* DIAG CTL */<br>- msr.lo = 0x080000000; /* enable actions */<br>- msr.hi = 0x000000000;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Set up delay on data lines, so that the hold time */<br>- /* is 1 ns. */<br>- msrnum = GLCP_PROCSTAT; /* GLCP IO DELAY CONTROLS */<br>- msr.lo = 0x082b5ad68;<br>- msr.hi = 0x080ad6b57; /* RGB delay = 0x07 */<br>- wrmsr(msrnum, msr);<br>-<br>- /* Set up DF to output diag information on DF pins. */<br>- msrnum = DF_GLD_MSR_MASTER_CONF;<br>- msr.lo = 0x0220;<br>- msr.hi = 0;<br>- wrmsr(msrnum, msr);<br>-<br>- msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */<br>- msr.hi = 0x0;<br>- msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */<br>- wrmsr(msrnum, msr);<br>- /* end of code for BTM */<br>- }<br>-<br>- /* Enable Suspend on Halt */<br>- msrnum = CPU_XC_CONFIG;<br>- msr = rdmsr(msrnum);<br>- msr.lo |= XC_CONFIG_SUSP_ON_HLT;<br>- wrmsr(msrnum, msr);<br>-<br>- /* ENable SUSP and allow TSC to run in Suspend */<br>- /* to keep speed detection happy */<br>- msrnum = CPU_BC_CONF_0;<br>- msr = rdmsr(msrnum);<br>- msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Setup throttling to proper mode if it is ever enabled. */<br>- msrnum = GLCP_TH_OD;<br>- msr.hi = 0x000000000;<br>- msr.lo = 0x00000603C;<br>- wrmsr(msrnum, msr);<br>-<br>-/* FooGlue Setup */<br>- /* Set CS5535/CS5536 mode in FooGlue */<br>- msrnum = FG_GIO_MSR_SEL;<br>- msr = rdmsr(msrnum);<br>- msr.lo &= ~3;<br>- msr.lo |= 2; /* IIOC mode CS5535/CS5536 enable. (according to Jordan Crouse the databook is wrong bits 1:0 have to be 2 instead of 1) */<br>- wrmsr(msrnum, msr);<br>-<br>-/* Disable DOT PLL. Graphics init will enable it if needed. */<br>- msrnum = GLCP_DOTPLL;<br>- msr = rdmsr(msrnum);<br>- msr.lo |= DOTPPL_LOWER_PD_SET;<br>- wrmsr(msrnum, msr);<br>-<br>-/* Enable RSDC */<br>- msrnum = CPU_AC_SMM_CTL;<br>- msr = rdmsr(msrnum);<br>- msr.lo |= 0x08;<br>- wrmsr(msrnum, msr);<br>-<br>-/* Enable BTB */<br>- /* I hate to put this check here but it doesn't really work in cpubug.asm */<br>- msrnum = GLCP_CHIP_REVID;<br>- msr = rdmsr(msrnum);<br>- if (msr.lo >= CPU_REV_2_1){<br>- msrnum = CPU_PF_BTB_CONF;<br>- msr = rdmsr(msrnum);<br>- msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET;<br>- wrmsr(msrnum, msr);<br>- }<br>-<br>-/* FPU imprecise exceptions bit */<br>- {<br>- msrnum = CPU_FPU_MSR_MODE;<br>- msr = rdmsr(msrnum);<br>- msr.lo |= FPU_IE_SET;<br>- wrmsr(msrnum, msr);<br>- }<br>-}<br>diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c<br>deleted file mode 100644<br>index 2aa9c8d..0000000<br>--- a/src/cpu/amd/geode_gx2/geode_gx2_init.c<br>+++ /dev/null<br>@@ -1,58 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <string.h><br>-#include <cpu/cpu.h><br>-#include <cpu/x86/lapic.h><br>-#include <cpu/x86/cache.h><br>-<br>-static void vsm_end_post_smi(void)<br>-{<br>- __asm__ volatile (<br>- "push %ax\n"<br>- "mov $0x5000, %ax\n"<br>- ".byte 0x0f, 0x38\n"<br>- "pop %ax\n"<br>- );<br>-}<br>-<br>-static void geode_gx2_init(device_t dev)<br>-{<br>- printk(BIOS_DEBUG, "geode_gx2_init\n");<br>-<br>- /* Turn on caching if we haven't already */<br>- x86_enable_cache();<br>-<br>- /* Enable the local CPU APICs */<br>- //setup_lapic();<br>-<br>- vsm_end_post_smi();<br>-<br>- printk(BIOS_DEBUG, "geode_gx2_init DONE\n");<br>-};<br>-<br>-static struct device_operations cpu_dev_ops = {<br>- .init = geode_gx2_init,<br>-};<br>-<br>-static struct cpu_device_id cpu_table[] = {<br>- { X86_VENDOR_NSC, 0x0552 },<br>- { 0, 0 },<br>-};<br>-<br>-static const struct cpu_driver driver __cpu_driver = {<br>- .ops = &cpu_dev_ops,<br>- .id_table = cpu_table,<br>-};<br>diff --git a/src/cpu/amd/geode_gx2/syspreinit.c b/src/cpu/amd/geode_gx2/syspreinit.c<br>deleted file mode 100644<br>index aa1a39d..0000000<br>--- a/src/cpu/amd/geode_gx2/syspreinit.c<br>+++ /dev/null<br>@@ -1,33 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* StartTimer1<br>- *<br>- * Entry: none<br>- * Exit: Starts Timer 1 for port 61 use<br>- * Destroys: Al,<br>- */<br>-static void StartTimer1(void)<br>-{<br>- outb(0x56, 0x43);<br>- outb(0x12, 0x41);<br>-}<br>-<br>-void SystemPreInit(void)<br>-{<br>- /* they want a jump ... */<br>-#if !IS_ENABLED(CONFIG_CACHE_AS_RAM)<br>- __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");<br>-#endif<br>- StartTimer1();<br>-}<br>diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig<br>deleted file mode 100644<br>index dfdf5ed..0000000<br>--- a/src/mainboard/amd/rumba/Kconfig<br>+++ /dev/null<br>@@ -1,41 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de><br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-if BOARD_AMD_RUMBA<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_AMD_GEODE_GX2<br>- select NORTHBRIDGE_AMD_GX2<br>- select SOUTHBRIDGE_AMD_CS5536<br>- select SUPERIO_WINBOND_W83627HF<br>- select UDELAY_TSC<br>- select HAVE_PIRQ_TABLE<br>- select BOARD_ROMSIZE_KB_256<br>- select POWER_BUTTON_FORCE_ENABLE<br>- select GX2_PROCESSOR_MHZ_366<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default amd/rumba<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "Rumba"<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 2<br>-<br>-endif # BOARD_AMD_RUMBA<br>diff --git a/src/mainboard/amd/rumba/Kconfig.name b/src/mainboard/amd/rumba/Kconfig.name<br>deleted file mode 100644<br>index e00444e..0000000<br>--- a/src/mainboard/amd/rumba/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_AMD_RUMBA<br>- bool "Rumba"<br>diff --git a/src/mainboard/amd/rumba/board_info.txt b/src/mainboard/amd/rumba/board_info.txt<br>deleted file mode 100644<br>index 7680e6f..0000000<br>--- a/src/mainboard/amd/rumba/board_info.txt<br>+++ /dev/null<br>@@ -1 +0,0 @@<br>-Category: half<br>diff --git a/src/mainboard/amd/rumba/cmos.layout b/src/mainboard/amd/rumba/cmos.layout<br>deleted file mode 100644<br>index b8ea936..0000000<br>--- a/src/mainboard/amd/rumba/cmos.layout<br>+++ /dev/null<br>@@ -1,28 +0,0 @@<br>-entries<br>-<br>-0 384 r 0 reserved_memory<br>-384 1 e 4 boot_option<br>-388 4 h 0 reboot_counter<br>-#392 3 r 0 unused<br>-400 1 e 1 power_on_after_fail<br>-412 4 e 6 debug_level<br>-456 1 e 1 ECC_memory<br>-1008 16 h 0 check_sum<br>-<br>-enumerations<br>-<br>-#ID value text<br>-1 0 Disable<br>-1 1 Enable<br>-2 0 Enable<br>-2 1 Disable<br>-4 0 Fallback<br>-4 1 Normal<br>-6 6 Notice<br>-6 7 Info<br>-6 8 Debug<br>-6 9 Spew<br>-<br>-checksums<br>-<br>-checksum 392 1007 1008<br>diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb<br>deleted file mode 100644<br>index d480355..0000000<br>--- a/src/mainboard/amd/rumba/devicetree.cb<br>+++ /dev/null<br>@@ -1,20 +0,0 @@<br>-chip northbridge/amd/gx2<br>- device cpu_cluster 0 on<br>- chip cpu/amd/geode_gx2<br>- device lapic 0 on end<br>- end<br>- end<br>- device domain 0 on<br>- device pci 1.0 on end<br>- device pci 1.1 on end<br>- chip southbridge/amd/cs5536<br>- register "lpc_serirq_enable" = "0x80" # enabled with default timing<br>- device pci d.0 on end # Realtek 8139 LAN<br>- device pci f.0 on end # ISA Bridge<br>- device pci f.2 on end # IDE Controller<br>- device pci f.3 on end # Audio<br>- device pci f.4 on end # OHCI<br>- device pci f.5 on end # EHCI<br>- end<br>- end<br>-end<br>diff --git a/src/mainboard/amd/rumba/irq_tables.c b/src/mainboard/amd/rumba/irq_tables.c<br>deleted file mode 100644<br>index ac225a4..0000000<br>--- a/src/mainboard/amd/rumba/irq_tables.c<br>+++ /dev/null<br>@@ -1,55 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-<br>-/* Platform IRQs */<br>-#define PIRQA 11<br>-#define PIRQB 5<br>-#define PIRQC 10<br>-#define PIRQD 10<br>-<br>-/* Map */<br>-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */<br>-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */<br>-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */<br>-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */<br>-<br>-/* Link */<br>-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */<br>-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */<br>-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */<br>-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */<br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */<br>- 0x00, /* Where the interrupt router lies (bus) */<br>- (0x12 << 3)|0x0, /* Where the interrupt router lies (dev) */<br>- 0x800, /* IRQs devoted exclusively to PCI usage */<br>- 0x1078, /* Vendor */<br>- 0x2, /* Device */<br>- 0, /* Miniport data */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */<br>- {<br>- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x00,(0x0e << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},<br>- {0x00,(0x0f << 3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},<br>- }<br>-};<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c<br>deleted file mode 100644<br>index a971db6..0000000<br>--- a/src/mainboard/amd/rumba/mainboard.c<br>+++ /dev/null<br>@@ -1,50 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <arch/io.h><br>-<br>-static void init(struct device *dev)<br>-{<br>- device_t nic = NULL;<br>- unsigned bus = 0;<br>- unsigned devfn = PCI_DEVFN(0xd, 0);<br>- int nicirq = 1;<br>-<br>- printk(BIOS_DEBUG, "AMD RUMBA ENTER %s\n", __func__);<br>-<br>- if (nicirq) {<br>- printk(BIOS_DEBUG, "%s (%x,%x)SET PCI interrupt line to %d\n",<br>- __func__, bus, devfn, nicirq);<br>- nic = dev_find_slot(bus, devfn);<br>- if (! nic){<br>- printk(BIOS_ERR, "Could not find NIC\n");<br>- } else {<br>- pci_write_config8(nic, PCI_INTERRUPT_LINE, nicirq);<br>- }<br>- }<br>- printk(BIOS_DEBUG, "AMD RUMBA EXIT %s\n", __func__);<br>-}<br>-<br>-static void mainboard_enable(struct device *dev)<br>-{<br>- dev->ops->init = init;<br>-}<br>-<br>-struct chip_operations mainboard_ops = {<br>- .enable_dev = mainboard_enable,<br>-};<br>diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c<br>deleted file mode 100644<br>index 4d9600a..0000000<br>--- a/src/mainboard/amd/rumba/romstage.c<br>+++ /dev/null<br>@@ -1,69 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <device/pci_def.h><br>-#include <arch/io.h><br>-#include <device/pnp_def.h><br>-#include <console/console.h><br>-#include <superio/winbond/common/winbond.h><br>-#include <superio/winbond/w83627hf/w83627hf.h><br>-#include <cpu/x86/bist.h><br>-#include <cpu/x86/msr.h><br>-#include <cpu/amd/gx2def.h><br>-#include <spd.h><br>-#include <southbridge/amd/cs5536/cs5536.h><br>-<br>-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)<br>-<br>-static inline int spd_read_byte(unsigned device, unsigned address)<br>-{<br>- if (device != DIMM0)<br>- return 0xFF; /* No DIMM1, don't even try. */<br>-<br>- return smbus_read_byte(device, address);<br>-}<br>-<br>-#include <northbridge/amd/gx2/raminit.h><br>-#include "northbridge/amd/gx2/pll_reset.c"<br>-#include "northbridge/amd/gx2/raminit.c"<br>-#include "lib/generic_sdram.c"<br>-#include "cpu/amd/geode_gx2/cpureginit.c"<br>-#include "cpu/amd/geode_gx2/syspreinit.c"<br>-#include "cpu/amd/geode_lx/msrinit.c"<br>-<br>-void asmlinkage mainboard_romstage_entry(unsigned long bist)<br>-{<br>- static const struct mem_controller memctrl [] = {<br>- {.channel0 = {DIMM0, DIMM1}}<br>- };<br>-<br>- SystemPreInit();<br>-<br>- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>- console_init();<br>-<br>- cs5536_early_setup();<br>-<br>- /* Halt if there was a built in self test failure */<br>- report_bist_failure(bist);<br>-<br>- pll_reset();<br>-<br>- cpuRegInit();<br>- printk(BIOS_ERR, "done cpuRegInit\n");<br>-<br>- sdram_initialize(1, memctrl);<br>-<br>- msr_init();<br>-}<br>diff --git a/src/mainboard/lippert/frontrunner/Kconfig b/src/mainboard/lippert/frontrunner/Kconfig<br>deleted file mode 100644<br>index 95dd96d..0000000<br>--- a/src/mainboard/lippert/frontrunner/Kconfig<br>+++ /dev/null<br>@@ -1,27 +0,0 @@<br>-if BOARD_LIPPERT_FRONTRUNNER<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_AMD_GEODE_GX2<br>- select NORTHBRIDGE_AMD_GX2<br>- select SOUTHBRIDGE_AMD_CS5535<br>- select SUPERIO_WINBOND_W83627HF<br>- select HAVE_DEBUG_SMBUS<br>- select UDELAY_TSC<br>- select HAVE_PIRQ_TABLE<br>- select BOARD_ROMSIZE_KB_256<br>- select GX2_PROCESSOR_MHZ_366<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default lippert/frontrunner<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "Cool Frontrunner"<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 2<br>-<br>-endif # BOARD_LIPPERT_FRONTRUNNER<br>diff --git a/src/mainboard/lippert/frontrunner/Kconfig.name b/src/mainboard/lippert/frontrunner/Kconfig.name<br>deleted file mode 100644<br>index 4024a7b..0000000<br>--- a/src/mainboard/lippert/frontrunner/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_LIPPERT_FRONTRUNNER<br>- bool "Cool FrontRunner"<br>diff --git a/src/mainboard/lippert/frontrunner/board_info.txt b/src/mainboard/lippert/frontrunner/board_info.txt<br>deleted file mode 100644<br>index a2b2d9f..0000000<br>--- a/src/mainboard/lippert/frontrunner/board_info.txt<br>+++ /dev/null<br>@@ -1,5 +0,0 @@<br>-Category: half<br>-Board URL: http://www.lippertembedded.com/en/productoverview/products-in-detail/85-lipperts-cool-frontrunner.html<br>-ROM package: PLCC<br>-ROM protocol: FWH<br>-ROM socketed: y<br>diff --git a/src/mainboard/lippert/frontrunner/cmos.layout b/src/mainboard/lippert/frontrunner/cmos.layout<br>deleted file mode 100644<br>index b8ea936..0000000<br>--- a/src/mainboard/lippert/frontrunner/cmos.layout<br>+++ /dev/null<br>@@ -1,28 +0,0 @@<br>-entries<br>-<br>-0 384 r 0 reserved_memory<br>-384 1 e 4 boot_option<br>-388 4 h 0 reboot_counter<br>-#392 3 r 0 unused<br>-400 1 e 1 power_on_after_fail<br>-412 4 e 6 debug_level<br>-456 1 e 1 ECC_memory<br>-1008 16 h 0 check_sum<br>-<br>-enumerations<br>-<br>-#ID value text<br>-1 0 Disable<br>-1 1 Enable<br>-2 0 Enable<br>-2 1 Disable<br>-4 0 Fallback<br>-4 1 Normal<br>-6 6 Notice<br>-6 7 Info<br>-6 8 Debug<br>-6 9 Spew<br>-<br>-checksums<br>-<br>-checksum 392 1007 1008<br>diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb<br>deleted file mode 100644<br>index 8e6cba0..0000000<br>--- a/src/mainboard/lippert/frontrunner/devicetree.cb<br>+++ /dev/null<br>@@ -1,20 +0,0 @@<br>-chip northbridge/amd/gx2<br>- device cpu_cluster 0 on<br>- chip cpu/amd/geode_gx2<br>- device lapic 0 on end<br>- end<br>- end<br>-<br>- device domain 0 on<br>- device pci 0.0 on<br>- chip southbridge/amd/cs5535<br>- register "setupflash" = "0"<br>- device pci 12.0 on end<br>- device pci 12.1 off end # SMI<br>- device pci 12.2 on end # IDE<br>- device pci 12.3 off end # Audio<br>- device pci 12.4 off end # VGA<br>- end<br>- end<br>- end<br>-end<br>diff --git a/src/mainboard/lippert/frontrunner/irq_tables.c b/src/mainboard/lippert/frontrunner/irq_tables.c<br>deleted file mode 100644<br>index 25e2dcb..0000000<br>--- a/src/mainboard/lippert/frontrunner/irq_tables.c<br>+++ /dev/null<br>@@ -1,42 +0,0 @@<br>-#include <arch/pirq_routing.h><br>-<br>-/* Platform IRQs */<br>-#define PIRQA 11<br>-#define PIRQB 5<br>-#define PIRQC 10<br>-#define PIRQD 10<br>-<br>-/* Map */<br>-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */<br>-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */<br>-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */<br>-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */<br>-<br>-/* Link */<br>-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */<br>-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */<br>-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */<br>-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */<br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */<br>- 0x00, /* Where the interrupt router lies (bus) */<br>- (0x12 << 3)|0x0, /* Where the interrupt router lies (dev) */<br>- 0x800, /* IRQs devoted exclusively to PCI usage */<br>- 0x1078, /* Vendor */<br>- 0x2, /* Device */<br>- 0, /* Miniport data */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */<br>- {<br>- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x00,(0x0e << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},<br>- {0x00,(0x0f << 3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},<br>- }<br>-};<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c<br>deleted file mode 100644<br>index e7fcbda..0000000<br>--- a/src/mainboard/lippert/frontrunner/romstage.c<br>+++ /dev/null<br>@@ -1,127 +0,0 @@<br>-#include <stdint.h><br>-#include <spd.h><br>-#include <device/pci_def.h><br>-#include <arch/io.h><br>-#include <device/pnp_def.h><br>-#include <console/console.h><br>-#include <superio/winbond/common/winbond.h><br>-#include <superio/winbond/w83627hf/w83627hf.h><br>-#include <cpu/x86/bist.h><br>-#include <cpu/x86/msr.h><br>-#include <cpu/amd/gx2def.h><br>-#include <southbridge/amd/cs5535/cs5535.h><br>-#include "southbridge/amd/cs5535/early_smbus.c"<br>-#include "southbridge/amd/cs5535/early_setup.c"<br>-<br>-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)<br>-<br>-static const unsigned char spdbytes[] = { /* 4x Qimonda HYB25DC512160CF-6 */<br>- 0xFF, 0xFF, /* only values used by raminit.c are set */<br>- [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, /* (Fundamental) memory type */<br>- [SPD_NUM_ROWS] = 0x0D, /* Number of row address bits [13] */<br>- [SPD_NUM_COLUMNS] = 0x0A, /* Number of column address bits [10] */<br>- [SPD_NUM_DIMM_BANKS] = 1, /* Number of module rows (banks) */<br>- 0xFF, 0xFF, 0xFF,<br>- [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x60, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [6.0 ns in BCD] */<br>- 0xFF, 0xFF,<br>- [SPD_REFRESH] = 0x82, /* Refresh rate/type [Self Refresh, 7.8 us] */<br>- [SPD_PRIMARY_SDRAM_WIDTH] = 64, /* SDRAM width (primary SDRAM) [64 bits] */<br>- 0xFF, 0xFF, 0xFF,<br>- [SPD_NUM_BANKS_PER_SDRAM] = 4, /* SDRAM device attributes, number of banks on SDRAM device */<br>- [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, /* SDRAM device attributes, CAS latency [3, 2.5, 2] */<br>- 0xFF, 0xFF,<br>- [SPD_MODULE_ATTRIBUTES] = 0x20, /* SDRAM module attributes [differential clk] */<br>- [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, /* SDRAM device attributes, general [Concurrent AP] */<br>- [SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, /* SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD] */<br>- 0xFF,<br>- [SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, /* SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD] */<br>- 0xFF,<br>- [SPD_tRP] = 72, /* Min. row precharge time [18 ns in units of 0.25 ns] */<br>- [SPD_tRRD] = 48, /* Min. row active to row active [12 ns in units of 0.25 ns] */<br>- [SPD_tRCD] = 72, /* Min. RAS to CAS delay [18 ns in units of 0.25 ns] */<br>- [SPD_tRAS] = 42, /* Min. RAS pulse width = active to precharge delay [42 ns] */<br>- [SPD_BANK_DENSITY] = 0x40, /* Density of each row on module [256 MB] */<br>- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,<br>- [SPD_tRFC] = 72 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [72 ns] */<br>-};<br>-<br>-static inline int spd_read_byte(unsigned int device, unsigned int address)<br>-{<br>- if (device != DIMM0)<br>- return 0xFF; /* No DIMM1, don't even try. */<br>-<br>-#if IS_ENABLED(CONFIG_DEBUG_SMBUS)<br>- if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {<br>- printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "<br>- "returns 0xff\n", address);<br>- }<br>-#endif<br>-<br>- /* Fake SPD ROM value */<br>- return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF;<br>-}<br>-<br>-#include <northbridge/amd/gx2/raminit.h><br>-#include "northbridge/amd/gx2/pll_reset.c"<br>-#include "northbridge/amd/gx2/raminit.c"<br>-#include "lib/generic_sdram.c"<br>-#include "cpu/amd/geode_gx2/cpureginit.c"<br>-#include "cpu/amd/geode_gx2/syspreinit.c"<br>-#include "cpu/amd/geode_lx/msrinit.c"<br>-<br>-void asmlinkage mainboard_romstage_entry(unsigned long bist)<br>-{<br>- static const struct mem_controller memctrl [] = {<br>- {.channel0 = {DIMM0, DIMM1}}<br>- };<br>- unsigned char temp;<br>-<br>- SystemPreInit();<br>- msr_init();<br>-<br>- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>- console_init();<br>-<br>- cs5535_early_setup();<br>- printk(BIOS_ERR, "done cs5535 early\n");<br>-<br>- /* Halt if there was a built in self test failure */<br>- report_bist_failure(bist);<br>-<br>- pll_reset();<br>- printk(BIOS_ERR, "done pll_reset\n");<br>-<br>- cpuRegInit();<br>- printk(BIOS_ERR, "done cpuRegInit\n");<br>-<br>- sdram_initialize(1, memctrl);<br>-<br>- printk(BIOS_ERR, "Done sdram_initialize\n");<br>- printk(BIOS_ERR, "Disable watchdog\n");<br>- outb( 0x87, 0x4E); //enter SuperIO configuration mode<br>- outb( 0x87, 0x4E);<br>-<br>- outb(0x20, 0x4e);<br>- temp = inb(0x4f);<br>- printk(BIOS_DEBUG, "%02x", temp);<br>- if (temp != 0x52){<br>- printk(BIOS_ERR, "CAN NOT READ SUPERIO VID\n");<br>- }<br>-<br>- outb(0x29, 0x4e);<br>- outb(0x7c, 0x4f);<br>-<br>- outb( 0x07, 0x4E); //enable logical device 9<br>- outb( 0x09, 0x4F);<br>- outb(0x30, 0x4e);<br>- outb(1, 0x4f);<br>- outb( 0xF0, 0x4E); //set GP33 as outbut in configuration register F0h Bit4 = \u20180\u2019<br>- outb( 0xC7, 0x4F);<br>- outb( 0xF1, 0x4E); //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables<br>- temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!<br>- printk(BIOS_DEBUG, "%02x:", temp);<br>- temp = temp & ~8;<br>- outb( temp, 0x4F);<br>- temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!<br>- printk(BIOS_DEBUG, "%02x\n", temp);<br>-}<br>diff --git a/src/mainboard/wyse/s50/Kconfig b/src/mainboard/wyse/s50/Kconfig<br>deleted file mode 100644<br>index 0c13056..0000000<br>--- a/src/mainboard/wyse/s50/Kconfig<br>+++ /dev/null<br>@@ -1,41 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2010 Nils Jacobs<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-if BOARD_WYSE_S50<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_AMD_GEODE_GX2<br>- select NORTHBRIDGE_AMD_GX2<br>- select SOUTHBRIDGE_AMD_CS5536<br>- select UDELAY_TSC<br>- select HAVE_PIRQ_TABLE<br>- select PIRQ_ROUTE<br>- select BOARD_ROMSIZE_KB_256<br>- select POWER_BUTTON_FORCE_DISABLE<br>- select GX2_PROCESSOR_MHZ_366<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default wyse/s50<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "s50"<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 3<br>-<br>-endif # BOARD_WYSE_S50<br>diff --git a/src/mainboard/wyse/s50/Kconfig.name b/src/mainboard/wyse/s50/Kconfig.name<br>deleted file mode 100644<br>index 470e844..0000000<br>--- a/src/mainboard/wyse/s50/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_WYSE_S50<br>- bool "S50"<br>diff --git a/src/mainboard/wyse/s50/board_info.txt b/src/mainboard/wyse/s50/board_info.txt<br>deleted file mode 100644<br>index 061101b..0000000<br>--- a/src/mainboard/wyse/s50/board_info.txt<br>+++ /dev/null<br>@@ -1,7 +0,0 @@<br>-Board name: S50<br>-Category: settop<br>-Board URL: http://au.wyse.com/products/hardware/thinclients/S50/index.asp<br>-ROM package: PLCC<br>-ROM protocol: LPC<br>-ROM socketed: y<br>-Flashrom support: y<br>diff --git a/src/mainboard/wyse/s50/cmos.layout b/src/mainboard/wyse/s50/cmos.layout<br>deleted file mode 100644<br>index b7deea8..0000000<br>--- a/src/mainboard/wyse/s50/cmos.layout<br>+++ /dev/null<br>@@ -1,46 +0,0 @@<br>-#<br>-# This file is part of the coreboot project.<br>-#<br>-# Copyright (C) 2010 Nils Jacobs<br>-#<br>-# This program is free software; you can redistribute it and/or<br>-# modify it under the terms of the GNU General Public License as<br>-# published by the Free Software Foundation; version 2 of<br>-# the License.<br>-#<br>-# This program is distributed in the hope that it will be useful,<br>-# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-# GNU General Public License for more details.<br>-#<br>-<br>-# -----------------------------------------------------------------<br>-<br>-entries<br>-<br>-0 384 r 0 reserved_memory<br>-384 1 e 4 boot_option<br>-388 4 h 0 reboot_counter<br>-#392 3 r 0 unused<br>-400 1 e 1 power_on_after_fail<br>-412 4 e 6 debug_level<br>-456 1 e 1 ECC_memory<br>-1008 16 h 0 check_sum<br>-<br>-enumerations<br>-<br>-#ID value text<br>-1 0 Disable<br>-1 1 Enable<br>-2 0 Enable<br>-2 1 Disable<br>-4 0 Fallback<br>-4 1 Normal<br>-6 6 Notice<br>-6 7 Info<br>-6 8 Debug<br>-6 9 Spew<br>-<br>-checksums<br>-<br>-checksum 392 1007 1008<br>diff --git a/src/mainboard/wyse/s50/devicetree.cb b/src/mainboard/wyse/s50/devicetree.cb<br>deleted file mode 100644<br>index 3cf1030..0000000<br>--- a/src/mainboard/wyse/s50/devicetree.cb<br>+++ /dev/null<br>@@ -1,46 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2010 Nils Jacobs<br>-##<br>-## This program is free software; you can redistribute it and/or<br>-## modify it under the terms of the GNU General Public License as<br>-## published by the Free Software Foundation; version 2 of<br>-## the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-chip northbridge/amd/gx2<br>- device domain 0 on<br>- device pci 1.0 on end # Geode GX2 Host Bridge<br>- device pci 1.1 on end # Geode GX2 Graphics Processor<br>- chip southbridge/amd/cs5536<br>- register "enable_gpio_int_route" = "0x0D0C0700"<br>- register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash<br>- register "enable_USBP4_device" = "0" #0: host, 1:device<br>- register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)<br>- register "com1_enable" = "1"<br>- register "com1_address" = "0x3F8"<br>- register "com1_irq" = "4"<br>- register "com2_enable" = "0"<br>- register "com2_address" = "0x2F8"<br>- register "com2_irq" = "3"<br>- device pci e.0 on end # Realtek 8139 LAN<br>- device pci f.0 on end # ISA Bridge<br>- device pci f.2 on end # IDE Controller<br>- device pci f.3 on end # Audio<br>- device pci f.4 on end # OHCI<br>- device pci f.5 on end # EHCI<br>- end<br>- end<br>- # APIC cluster is late CPU init.<br>- device cpu_cluster 0 on<br>- chip cpu/amd/geode_gx2<br>- device lapic 0 on end<br>- end<br>- end<br>-end<br>diff --git a/src/mainboard/wyse/s50/irq_tables.c b/src/mainboard/wyse/s50/irq_tables.c<br>deleted file mode 100644<br>index 3283745..0000000<br>--- a/src/mainboard/wyse/s50/irq_tables.c<br>+++ /dev/null<br>@@ -1,63 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2010 Nils Jacobs<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-<br>-/* Platform IRQs */<br>-#define PIRQA 11<br>-#define PIRQB 5<br>-#define PIRQC 10<br>-#define PIRQD 10<br>-<br>-/* Map */<br>-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */<br>-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */<br>-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */<br>-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */<br>-<br>-/* Link */<br>-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */<br>-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */<br>-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */<br>-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */<br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */<br>- 0x00, /* Interrupt router bus */<br>- (0x0f << 3) | 0x0, /* Interrupt router dev */<br>- 0, /* IRQs devoted exclusively to PCI usage */<br>- 0x100b, /* Vendor */<br>- 0x2b, /* Device */<br>- 0, /* Miniport */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0xdc, /* Checksum (has to be set to some value that<br>- * would give 0 after the sum of all bytes<br>- * for this structure (including checksum).<br>- */<br>- {<br>- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x00, (0x0f << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x5, 0x0},<br>- {0x00, (0x0d << 3) | 0x0, {{0x04, 0x0400}, {0x03, 0x0400}, {0x02, 0x0020}, {0x01, 0x0800}}, 0x1, 0x0},<br>- {0x00, (0x0e << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x2, 0x0},<br>- }<br>-};<br>-<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c<br>deleted file mode 100644<br>index 8fc797c..0000000<br>--- a/src/mainboard/wyse/s50/romstage.c<br>+++ /dev/null<br>@@ -1,72 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2010 Nils Jacobs<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <device/pci_def.h><br>-#include <arch/io.h><br>-#include <device/pnp_def.h><br>-#include <console/console.h><br>-#include <lib.h><br>-#include <cpu/x86/bist.h><br>-#include <cpu/x86/msr.h><br>-#include <cpu/amd/gx2def.h><br>-#include <spd.h><br>-#include <southbridge/amd/cs5536/cs5536.h><br>-<br>-static inline int spd_read_byte(unsigned int device, unsigned int address)<br>-{<br>- if (device != DIMM0)<br>- return 0xFF; /* No DIMM1, don't even try. */<br>-<br>- return smbus_read_byte(device, address);<br>-}<br>-<br>-#include <northbridge/amd/gx2/raminit.h><br>-#include "northbridge/amd/gx2/pll_reset.c"<br>-#include "northbridge/amd/gx2/raminit.c"<br>-#include "lib/generic_sdram.c"<br>-#include "cpu/amd/geode_gx2/cpureginit.c"<br>-#include "cpu/amd/geode_gx2/syspreinit.c"<br>-#include "cpu/amd/geode_lx/msrinit.c"<br>-<br>-void asmlinkage mainboard_romstage_entry(unsigned long bist)<br>-{<br>- static const struct mem_controller memctrl [] = {<br>- {.channel0 = {DIMM0, DIMM1}}<br>- };<br>-<br>- SystemPreInit();<br>-<br>- cs5536_early_setup();<br>-<br>- /* cs5536_disable_internal_uart disable them. Set them up now... */<br>- cs5536_setup_onchipuart(1);<br>-<br>- console_init();<br>-<br>- /* Halt if there was a built in self test failure */<br>- report_bist_failure(bist);<br>-<br>- pll_reset();<br>-<br>- cpuRegInit();<br>- printk(BIOS_ERR, "done cpuRegInit\n");<br>-<br>- sdram_initialize(1, memctrl);<br>- printk(BIOS_ERR, "ram setup done\n");<br>-<br>- msr_init();<br>-}<br>diff --git a/src/northbridge/amd/gx2/Kconfig b/src/northbridge/amd/gx2/Kconfig<br>deleted file mode 100644<br>index fcba106..0000000<br>--- a/src/northbridge/amd/gx2/Kconfig<br>+++ /dev/null<br>@@ -1,73 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2007-2009 coresystems GmbH<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-config NORTHBRIDGE_AMD_GX2<br>- bool<br>- select GEODE_VSA<br>- select LATE_CBMEM_INIT<br>-<br>-if NORTHBRIDGE_AMD_GX2<br>-<br>-choice<br>- prompt "Framebuffer size"<br>- default GX2_VIDEO_MB_8MB<br>-<br>-config GX2_VIDEO_MB_4MB<br>- bool "4MB"<br>-config GX2_VIDEO_MB_8MB<br>- bool "8MB"<br>-config GX2_VIDEO_MB_16MB<br>- bool "16MB"<br>-config GX2_VIDEO_MB_32MB<br>- bool "32MB"<br>-config GX2_VIDEO_MB_64MB<br>- bool "64MB"<br>-config GX2_VIDEO_MB_128MB<br>- bool "128MB"<br>-config GX2_VIDEO_MB_256MB<br>- bool "256MB"<br>-config GX2_VIDEO_MB_CMOS<br>- bool "Use CMOS option"<br>-<br>-endchoice<br>-<br>-config VIDEO_MB<br>- int<br>- default 4 if GX2_VIDEO_MB_4MB<br>- default 8 if GX2_VIDEO_MB_8MB<br>- default 16 if GX2_VIDEO_MB_16MB<br>- default 32 if GX2_VIDEO_MB_32MB<br>- default 64 if GX2_VIDEO_MB_64MB<br>- default 128 if GX2_VIDEO_MB_128MB<br>- default 256 if GX2_VIDEO_MB_256MB<br>- default -1 if GX2_VIDEO_MB_CMOS<br>-<br>-# The GX2_PROCESSOR_MHZ options let you chose the correct GX2 processor<br>-# speed in the mainboard's Kconfig file.<br>-config GX2_PROCESSOR_MHZ_300<br>- bool<br>-config GX2_PROCESSOR_MHZ_366<br>- bool<br>-config GX2_PROCESSOR_MHZ_400<br>- bool<br>-<br>-# Map the config names to an integer (MHz).<br>-config GX2_PROCESSOR_MHZ<br>- int<br>- default 300 if GX2_PROCESSOR_MHZ_300<br>- default 366 if GX2_PROCESSOR_MHZ_366<br>- default 400 if GX2_PROCESSOR_MHZ_400<br>-<br>-endif # NORTHBRIDGE_AMD_GX2<br>diff --git a/src/northbridge/amd/gx2/Makefile.inc b/src/northbridge/amd/gx2/Makefile.inc<br>deleted file mode 100644<br>index 7936acb..0000000<br>--- a/src/northbridge/amd/gx2/Makefile.inc<br>+++ /dev/null<br>@@ -1,7 +0,0 @@<br>-ifeq ($(CONFIG_NORTHBRIDGE_AMD_GX2),y)<br>-<br>-ramstage-y += northbridge.c<br>-ramstage-y += northbridgeinit.c<br>-ramstage-y += grphinit.c<br>-<br>-endif<br>diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c<br>deleted file mode 100644<br>index 5f1c88e..0000000<br>--- a/src/northbridge/amd/gx2/grphinit.c<br>+++ /dev/null<br>@@ -1,85 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007 Advanced Micro Devices, Inc.<br>- * Copyright (C) 2012 Nils Jacobs<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <cpu/amd/vr.h><br>-#include <console/console.h><br>-#include <cpu/amd/gx2def.h><br>-#include <cpu/x86/msr.h><br>-#include <stdlib.h><br>-<br>-void geodegx2_vga_msr_init(void);<br>-void graphics_init(void);<br>-<br>-struct msrinit {<br>- u32 msrnum;<br>- msr_t msr;<br>-};<br>-<br>-static const struct msrinit geodegx2_vga_msr[] = {<br>- /* Enable the GLIU Memory routing to the memory A0000-BFFFF<br>- * PDID1 : Port 4, GLIU0<br>- * PBASE : 0x000A0<br>- * PMASK : 0xFFFE0<br>- */<br>- {.msrnum = GLIU0_P2D_BM_4, {.lo = 0x0a0fffe0, .hi = 0x80000000}},<br>-};<br>-<br>-void geodegx2_vga_msr_init(void)<br>-{<br>- int i;<br>- for (i = 0; i < ARRAY_SIZE(geodegx2_vga_msr); i++)<br>- wrmsr(geodegx2_vga_msr[i].msrnum, geodegx2_vga_msr[i].msr);<br>-}<br>-<br>-<br>-/* This function mirrors the Graphics_Init routine in GeodeROM. */<br>-void graphics_init(void)<br>-{<br>- uint16_t wClassIndex, wData, res;<br>-<br>- /* SoftVG initialization */<br>- printk(BIOS_DEBUG, "Graphics init...\n");<br>-<br>- geodegx2_vga_msr_init();<br>-<br>- /* Call SoftVG with the main configuration parameters. */<br>- /* NOTE: SoftVG expects the memory size to be given in 512 KB blocks */<br>-<br>- wClassIndex = (VRC_VG << 8) + VG_CONFIG;<br>-<br>- /*<br>- * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP)<br>- * External Monochrome Card Support(12) 0, NO<br>- * Controller Priority Select(11) 1, Primary<br>- * Display Select(10:8) 0x0, CRT<br>- * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1,<br>- * defined in devicetree.cb<br>- * PLL Reference Clock Bypass(0) 0, Default<br>- */<br>-<br>- /* Video RAM has to be given in 512KB chunks<br>- * the value is read @ 7:1 (value in 7:0 looks like /2)<br>- * so we can add the real value in megabytes<br>- */<br>-<br>- wData = VG_CFG_PRIORITY | VG_CFG_DSCRT | ((CONFIG_VIDEO_MB * 2) & VG_MEM_MASK);<br>- vrWrite(wClassIndex, wData);<br>-<br>- res = vrRead(wClassIndex);<br>- printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);<br>-}<br>diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c<br>deleted file mode 100644<br>index ef3b30a..0000000<br>--- a/src/northbridge/amd/gx2/northbridge.c<br>+++ /dev/null<br>@@ -1,347 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007 Advanced Micro Devices, Inc.<br>- * Copyright (C) 2010 Nils Jacobs<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include "northbridge.h"<br>-#include <cpu/x86/msr.h><br>-#include <cpu/x86/cache.h><br>-#include <cpu/amd/vr.h><br>-#include <cpu/cpu.h><br>-#include "../../../southbridge/amd/cs5536/cs5536.h"<br>-<br>-void print_conf(void);<br>-<br>-/* Print the platform configuration - do before PCI init or it will not<br>- * work right.<br>- */<br>-void print_conf(void)<br>-{<br>-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR<br>- int i;<br>- unsigned long iol;<br>- msr_t msr;<br>-<br>- int cpu_msr_defs[] = { CPU_IM_CONFIG, CPU_DM_CONFIG0,<br>- CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,<br>- CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,<br>- GLCP_DELAY_CONTROLS, GL_END<br>- };<br>-<br>- int gliu0_msr_defs[] = { GLIU0_P2D_BM_0, GLIU0_P2D_BM_1,<br>- GLIU0_P2D_BM_2, GLIU0_P2D_BM_3, GLIU0_P2D_BM_4,<br>- GLIU0_P2D_BM_5, GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1,<br>- GLIU0_P2D_R_0, GLIU0_P2D_RO_0, GLIU0_P2D_RO_1,<br>- GLIU0_P2D_RO_2, GLIU0_P2D_SC_0, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,<br>- GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,<br>- GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,<br>- GLIU0_GLD_MSR_COH, GL_END<br>- };<br>-<br>- int gliu1_msr_defs[] = { GLIU1_P2D_BM_0, GLIU1_P2D_BM_1,<br>- GLIU1_P2D_BM_2, GLIU1_P2D_BM_3, GLIU1_P2D_BM_4,<br>- GLIU1_P2D_BM_5, GLIU1_P2D_BM_6, GLIU1_P2D_BM_7,<br>- GLIU1_P2D_BM_8, GLIU1_P2D_R_0, GLIU1_P2D_R_1,<br>- GLIU1_P2D_R_2, GLIU1_P2D_R_3, GLIU1_P2D_SC_0,<br>- GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,<br>- GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, GLIU1_IOD_SC_4,<br>- GLIU1_IOD_SC_5, GLIU1_GLD_MSR_COH, GL_END<br>- };<br>-<br>- int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,<br>- CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END<br>- };<br>-<br>- int lbar_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, GL_END<br>- };<br>-<br>- int irq_msr[] = { MDD_IRQM_YLOW, MDD_IRQM_YHIGH, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,<br>- MDD_IRQM_PRIM, GL_END<br>- };<br>-<br>- int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,<br>- GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,<br>- GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END<br>- };<br>-<br>- int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,<br>- MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,<br>- MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END<br>- };<br>-<br>- printk(BIOS_DEBUG, "---------- CPU ------------\n");<br>-<br>- for (i = 0; cpu_msr_defs[i] != GL_END; i++) {<br>- msr = rdmsr(cpu_msr_defs[i]);<br>- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",<br>- cpu_msr_defs[i], msr.hi, msr.lo);<br>- }<br>-<br>- printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");<br>-<br>- for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {<br>- msr = rdmsr(gliu0_msr_defs[i]);<br>- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",<br>- gliu0_msr_defs[i], msr.hi, msr.lo);<br>- }<br>-<br>- printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");<br>-<br>- for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {<br>- msr = rdmsr(gliu1_msr_defs[i]);<br>- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",<br>- gliu1_msr_defs[i], msr.hi, msr.lo);<br>- }<br>-<br>- printk(BIOS_DEBUG, "---------- RCONF ------------\n");<br>-<br>- for (i = 0; rconf_msr[i] != GL_END; i++) {<br>- msr = rdmsr(rconf_msr[i]);<br>- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],<br>- msr.hi, msr.lo);<br>- }<br>-<br>- printk(BIOS_DEBUG, "---------- VARIA ------------\n");<br>- msr = rdmsr(ATA_SB_IDE_CFG);<br>- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", ATA_SB_IDE_CFG, msr.hi,<br>- msr.lo);<br>-<br>- msr = rdmsr(MDD_LEG_IO);<br>- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_LEG_IO, msr.hi,<br>- msr.lo);<br>-<br>- msr = rdmsr(MDD_PIN_OPT);<br>- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_PIN_OPT, msr.hi,<br>- msr.lo);<br>-<br>- printk(BIOS_DEBUG, "---------- PCI ------------\n");<br>-<br>- for (i = 0; pci_msr[i] != GL_END; i++) {<br>- msr = rdmsr(pci_msr[i]);<br>- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],<br>- msr.hi, msr.lo);<br>- }<br>-<br>- printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");<br>-<br>- for (i = 0; dma_msr[i] != GL_END; i++) {<br>- msr = rdmsr(dma_msr[i]);<br>- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],<br>- msr.hi, msr.lo);<br>- }<br>-<br>- printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");<br>-<br>- for (i = 0; irq_msr[i] != GL_END; i++) {<br>- msr = rdmsr(irq_msr[i]);<br>- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", irq_msr[i],<br>- msr.hi, msr.lo);<br>- }<br>-<br>- printk(BIOS_DEBUG, "---------- DIVIL LBAR -----------\n");<br>-<br>- for (i = 0; lbar_msr[i] != GL_END; i++) {<br>- msr = rdmsr(lbar_msr[i]);<br>- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", lbar_msr[i],<br>- msr.hi, msr.lo);<br>- }<br>-<br>- iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);<br>- printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",<br>- GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);<br>- iol = inl(GPIOL_EVENTS_ENABLE);<br>- printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",<br>- GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);<br>- iol = inl(GPIOL_INPUT_INVERT_ENABLE);<br>- printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",<br>- GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);<br>- iol = inl(GPIO_MAPPER_X);<br>- printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,<br>- iol);<br>-#endif /* CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR */<br>-}<br>-<br>-/* todo: add a resource record. We don't do this here because this may be called when<br>- * very little of the platform is actually working.<br>- */<br>-int sizeram(void)<br>-{<br>- msr_t msr;<br>- int sizem = 0;<br>- unsigned short dimm;<br>-<br>- /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */<br>- msr = rdmsr(MC_CF07_DATA);<br>- printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);<br>-<br>- /* dimm 0 */<br>- dimm = msr.hi;<br>- /* installed? */<br>- if ((dimm & 7) != 7)<br>- sizem = (1 << ((dimm >> 12)-1)) * 8;<br>-<br>- /* dimm 1 */<br>- dimm = msr.hi >> 16;<br>- /* installed? */<br>- if ((dimm & 7) != 7)<br>- sizem += (1 << ((dimm >> 12)-1)) * 8;<br>-<br>- printk(BIOS_DEBUG, "sizeram: sizem 0x%x\n", sizem);<br>- return sizem;<br>-}<br>-<br>-static void enable_shadow(device_t dev)<br>-{<br>-<br>-}<br>-<br>-static void northbridge_init(device_t dev)<br>-{<br>- printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__);<br>-<br>- enable_shadow(dev);<br>-}<br>-<br>-static void northbridge_set_resources(struct device *dev)<br>-{<br>- uint8_t line;<br>-<br>- struct bus *bus;<br>-<br>- for (bus = dev->link_list; bus; bus = bus->next) {<br>- if (bus->children) {<br>- printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n",<br>- bus->secondary);<br>- assign_resources(bus);<br>- }<br>- }<br>-<br>- /* set a default latency timer */<br>- pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);<br>-<br>- /* set a default secondary latency timer */<br>- if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {<br>- pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);<br>- }<br>-<br>- /* zero the irq settings */<br>- line = pci_read_config8(dev, PCI_INTERRUPT_PIN);<br>- if (line) {<br>- pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);<br>- }<br>- /* set the cache line size, so far 64 bytes is good for everyone */<br>- pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);<br>-}<br>-<br>-static struct device_operations northbridge_operations = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = northbridge_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = northbridge_init,<br>- .enable = 0,<br>- .ops_pci = 0,<br>-};<br>-<br>-static const struct pci_driver northbridge_driver __pci_driver = {<br>- .ops = &northbridge_operations,<br>- .vendor = PCI_VENDOR_ID_NS,<br>- .device = PCI_DEVICE_ID_NS_GX2,<br>-};<br>-<br>-#include <cbmem.h><br>-<br>-static void pci_domain_set_resources(device_t dev)<br>-{<br>- int idx;<br>- u32 tomk;<br>- device_t mc_dev;<br>-<br>- printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);<br>-<br>- mc_dev = dev->link_list->children;<br>- if (mc_dev) {<br>- tomk = get_systop() / 1024;<br>- /* Report the memory regions<br>- All memory up to systop except 0xa0000-0xbffff */<br>- idx = 10;<br>- ram_resource(dev, idx++, 0, 640);<br>- ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */<br>-<br>- set_late_cbmem_top(tomk * 1024);<br>- }<br>-<br>- assign_resources(dev->link_list);<br>-}<br>-<br>-static void pci_domain_enable(device_t dev)<br>-{<br>- printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);<br>-<br>- /* do this here for now -- this chip really breaks our device model */<br>- northbridge_init_early();<br>- cpubug();<br>- chipsetinit();<br>- print_conf();<br>- do_vsmbios();<br>- graphics_init();<br>-}<br>-<br>-static struct device_operations pci_domain_ops = {<br>- .read_resources = pci_domain_read_resources,<br>- .set_resources = pci_domain_set_resources,<br>- .enable_resources = NULL,<br>- .scan_bus = pci_domain_scan_bus,<br>- .enable = pci_domain_enable,<br>- .ops_pci_bus = pci_bus_default_ops,<br>-};<br>-<br>-static void cpu_bus_init(device_t dev)<br>-{<br>- printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);<br>-<br>- initialize_cpus(dev->link_list);<br>-}<br>-<br>-static struct device_operations cpu_bus_ops = {<br>- .read_resources = DEVICE_NOOP,<br>- .set_resources = DEVICE_NOOP,<br>- .enable_resources = DEVICE_NOOP,<br>- .init = cpu_bus_init,<br>- .scan_bus = 0,<br>-};<br>-<br>-static void enable_dev(struct device *dev)<br>-{<br>- printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n",<br>- __func__, dev->path.type);<br>-<br>- /* Set the operations if it is a special bus type */<br>- if (dev->path.type == DEVICE_PATH_DOMAIN)<br>- dev->ops = &pci_domain_ops;<br>- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)<br>- dev->ops = &cpu_bus_ops;<br>-}<br>-<br>-struct chip_operations northbridge_amd_gx2_ops = {<br>- CHIP_NAME("AMD GX (previously GX2) Northbridge")<br>- .enable_dev = enable_dev,<br>-};<br>diff --git a/src/northbridge/amd/gx2/northbridge.h b/src/northbridge/amd/gx2/northbridge.h<br>deleted file mode 100644<br>index a4cd272..0000000<br>--- a/src/northbridge/amd/gx2/northbridge.h<br>+++ /dev/null<br>@@ -1,16 +0,0 @@<br>-#ifndef NORTHBRIDGE_AMD_GX2_H<br>-#define NORTHBRIDGE_AMD_GX2_H<br>-<br>-#include <cpu/amd/gx2def.h><br>-<br>-/* northbridge.c */<br>-unsigned int gx2_scan_root_bus(device_t root, unsigned int max);<br>-int sizeram(void);<br>-void do_vsmbios(void);<br>-void graphics_init(void);<br>-<br>-/* northbridgeinit.c */<br>-void northbridge_init_early(void);<br>-uint32_t get_systop(void);<br>-<br>-#endif /* NORTHBRIDGE_AMD_GX2_H */<br>diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c<br>deleted file mode 100644<br>index 3b02016..0000000<br>--- a/src/northbridge/amd/gx2/northbridgeinit.c<br>+++ /dev/null<br>@@ -1,673 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007 Advanced Micro Devices, Inc.<br>- * Copyright (C) 2010 Nils Jacobs<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include "northbridge.h"<br>-#include <cpu/amd/gx2def.h><br>-#include <cpu/x86/msr.h><br>-#include <cpu/x86/cache.h><br>-<br>-struct gliutable<br>-{<br>- unsigned long desc_name;<br>- unsigned short desc_type;<br>- unsigned long hi, lo;<br>-};<br>-<br>-struct gliutable gliu0table[] = {<br>- {.desc_name = GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */<br>- {.desc_name = GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */<br>- {.desc_name = GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */<br>- {.desc_name = GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */<br>- {.desc_name = GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */<br>- {.desc_name = GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},<br>- {.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},<br>-};<br>-<br>-struct gliutable gliu1table[] = {<br>- {.desc_name = GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */<br>- {.desc_name = GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */<br>- {.desc_name = GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */<br>- {.desc_name = GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */<br>- {.desc_name = GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */<br>- {.desc_name = GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},<br>- {.desc_name = GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */<br>- {.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},<br>-};<br>-<br>-struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };<br>-<br>-struct msrinit<br>-{<br>- unsigned long msrnum;<br>- msr_t msr;<br>-};<br>-<br>-struct msrinit ClockGatingDefault[] = {<br>- {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},<br>- /* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */<br>- {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}},<br>- {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},<br>- {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */<br>- {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},<br>- {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}},<br>- {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},<br>- {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},<br>- {FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* Always on */<br>- {0xffffffff, {0xffffffff, 0xffffffff}},<br>-};<br>-<br>-/* All On */<br>-struct msrinit ClockGatingAllOn[] = {<br>- {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},<br>- {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},<br>- {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},<br>- {VG_GLD_MSR_PM, {.hi = 0x00, .lo = 0x00}},<br>- {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x000000001}},<br>- {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},<br>- {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},<br>- {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},<br>- {FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}},<br>- {0xffffffff, {0xffffffff, 0xffffffff}},<br>-};<br>-<br>-/* Performance */<br>-struct msrinit ClockGatingPerformance[] = {<br>- {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */<br>- {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},<br>- {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}},<br>- {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},<br>- {0xffffffff, {0xffffffff, 0xffffffff}},<br>-};<br>-<br>-/* SET GeodeLink PRIORITY */<br>-struct msrinit GeodeLinkPriorityTable[] = {<br>- {CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}}, /* CPU Priority. */<br>- {DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}}, /* DF Priority. */<br>- {VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}}, /* VG Primary and Secondary Priority. */<br>- {GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}}, /* Graphics Priority. */<br>- {GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0027}}, /* GLPCI Priority + PID */<br>- {GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}}, /* GLCP Priority + PID */<br>- {FG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}}, /* FG PID */<br>- {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */<br>-};<br>-<br>-static void writeglmsr(struct gliutable *gl)<br>-{<br>- msr_t msr;<br>-<br>- msr.lo = gl->lo;<br>- msr.hi = gl->hi;<br>- wrmsr(gl->desc_name, msr); /* MSR - see table above */<br>- printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);<br>-}<br>-<br>-static void ShadowInit(struct gliutable *gl)<br>-{<br>- msr_t msr;<br>-<br>- msr = rdmsr(gl->desc_name);<br>-<br>- if (msr.lo == 0) {<br>- writeglmsr(gl);<br>- }<br>-}<br>-<br>-static void SysmemInit(struct gliutable *gl)<br>-{<br>- msr_t msr;<br>- int sizembytes, sizebytes;<br>-<br>- /* Figure out how much RAM is in the machine and alocate all to the<br>- * system. We will adjust for SMM now and Frame Buffer later.<br>- */<br>- sizembytes = sizeram();<br>- printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __func__, sizembytes);<br>- sizebytes = sizembytes << 20;<br>-<br>- sizebytes -= ((SMM_SIZE * 1024) + 1);<br>-<br>- /* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo<br>- The top 8 bits go into 0-7 of msr.hi. */<br>- sizebytes --;<br>- msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);<br>- sizebytes <<= 8; /* move bits 23:12 in bits 31:20. */<br>- sizebytes &= 0xfff00000;<br>- sizebytes |= 0x100; /* start at 1MB */<br>- msr.lo = sizebytes;<br>- wrmsr(gl->desc_name, msr); /* MSR - see table above */<br>- printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,<br>- gl->desc_name, msr.hi, msr.lo);<br>-}<br>-<br>-static void SMMGL0Init(struct gliutable *gl)<br>-{<br>- msr_t msr;<br>- int sizebytes = sizeram() << 20;<br>- long offset;<br>-<br>- sizebytes -= (SMM_SIZE * 1024);<br>-<br>- printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);<br>-<br>- offset = sizebytes - SMM_OFFSET;<br>- offset = (offset >> 12) & 0x000fffff;<br>- printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, SMM_OFFSET);<br>-<br>- msr.hi = offset << 8 | gl->hi;<br>- msr.hi |= SMM_OFFSET >> 24;<br>-<br>- msr.lo = (SMM_OFFSET & 0x00ffffff) << 8;<br>- msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;<br>-<br>- wrmsr(gl->desc_name, msr); /* MSR - See table above */<br>- printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);<br>-}<br>-<br>-static void SMMGL1Init(struct gliutable *gl)<br>-{<br>- msr_t msr;<br>- printk(BIOS_DEBUG, "%s:\n", __func__);<br>-<br>- msr.hi = gl->hi;<br>- /* I don't think this is needed */<br>- msr.hi &= 0xffffff00;<br>- msr.hi |= (SMM_OFFSET >> 24);<br>- msr.lo = (SMM_OFFSET & 0x00fff000) << 8;<br>- msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;<br>-<br>- wrmsr(gl->desc_name, msr); /* MSR - See table above */<br>- printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);<br>-}<br>-<br>-static void GLIUInit(struct gliutable *gl)<br>-{<br>- while (gl->desc_type != GL_END) {<br>- switch (gl->desc_type) {<br>- default:<br>- writeglmsr(gl);<br>- case SC_SHADOW: /* Check for a Shadow entry */<br>- ShadowInit(gl);<br>- break;<br>-<br>- case R_SYSMEM: /* check for a SYSMEM entry */<br>- SysmemInit(gl);<br>- break;<br>-<br>- case BMO_SMM: /* check for a SMM entry */<br>- SMMGL0Init(gl);<br>- break;<br>-<br>- case BM_SMM: /* check for a SMM entry */<br>- SMMGL1Init(gl);<br>- break;<br>- }<br>- gl++;<br>- }<br>-}<br>-<br>-/* Set up GLPCI settings for reads/write into memory.<br>- *<br>- * R0: 0-640KB,<br>- * R1: 1MB - Top of System Memory<br>- * R2: SMM Memory<br>- * R3: Framebuffer? - not set up yet<br>- * R4: ??<br>- */<br>-static void GLPCIInit(void)<br>-{<br>- struct gliutable *gl = 0;<br>- int i;<br>- msr_t msr;<br>- int msrnum;<br>-<br>- /* R0 - GLPCI settings for Conventional Memory space. */<br>- msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */<br>- msr.lo = 0; /* 0 */<br>- msr.lo |= GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;<br>- msrnum = GLPCI_RC0;<br>- wrmsr(msrnum, msr);<br>-<br>- /* R1 - GLPCI settings for SysMem space. */<br>- /* Get systop from GLIU0 SYSTOP Descriptor */<br>- for (i = 0; gliu0table[i].desc_name != GL_END; i++) {<br>- if (gliu0table[i].desc_type == R_SYSMEM) {<br>- gl = &gliu0table[i];<br>- break;<br>- }<br>- }<br>- if (gl) {<br>- unsigned long pah, pal;<br>- msrnum = gl->desc_name;<br>- msr = rdmsr(msrnum);<br>- /* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00<br>- * translates to a base of 0x00100000 and top of 0xffbf0000<br>- * base of 1M and top of around 256M<br>- */<br>- /* we have to create a page-aligned (4KB page) address for base and top<br>- * so we need a high page aligned addresss (pah) and low page aligned address (pal)<br>- * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12<br>- */<br>- pah = ((msr.hi & 0xff) << 12) | ((msr.lo >> 20) & 0xfff);<br>- /* we have the page address. Now make it a page-aligned address */<br>- pah <<= 12;<br>-<br>- pal = msr.lo << 12;<br>- msr.hi = pah;<br>- msr.lo = pal;<br>- msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;<br>- printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);<br>- msrnum = GLPCI_RC1;<br>- wrmsr(msrnum, msr);<br>- }<br>-<br>- /* R2 - GLPCI settings for SMM space. */<br>- msr.hi = ((SMM_OFFSET + (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;<br>- msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;<br>- msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;<br>- printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);<br>- msrnum = GLPCI_RC2;<br>- wrmsr(msrnum, msr);<br>-<br>- /* this is done elsewhere already, but it does no harm to do it more than once */<br>- /* write serialize memory hole to PCI. Need to unWS when something is shadowed regardless of cachablility. */<br>- msr.lo = 0x021212121; /* cache disabled and write serialized */<br>- msr.hi = 0x021212121; /* cache disabled and write serialized */<br>-<br>- msrnum = CPU_RCONF_A0_BF;<br>- wrmsr(msrnum, msr);<br>-<br>- msrnum = CPU_RCONF_C0_DF;<br>- wrmsr(msrnum, msr);<br>-<br>- msrnum = CPU_RCONF_E0_FF;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */<br>- msrnum = GLPCI_A0_BF;<br>- msr.hi = 0x35353535;<br>- msr.lo = 0x35353535;<br>- wrmsr(msrnum, msr);<br>-<br>- msrnum = GLPCI_C0_DF;<br>- msr.hi = 0x35353535;<br>- msr.lo = 0x35353535;<br>- wrmsr(msrnum, msr);<br>-<br>- msrnum = GLPCI_E0_FF;<br>- msr.hi = 0x35353535;<br>- msr.lo = 0x35353535;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Set WSREQ */<br>- msrnum = CPU_DM_CONFIG0;<br>- msr = rdmsr(msrnum);<br>- msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);<br>- msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT ; /* reduce to 1 for safe mode. */<br>- wrmsr(msrnum, msr);<br>-<br>- /* we are ignoring the 5530 case for now, and perhaps forever. */<br>-<br>- /* 553X NB Init */<br>-<br>- /* Arbiter setup */<br>- msrnum = GLPCI_ARB;<br>- msr = rdmsr(msrnum);<br>- msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;<br>- msr.lo |= GLPCI_ARB_LOWER_IIE_SET;<br>- wrmsr(msrnum, msr);<br>-<br>- msrnum = GLPCI_CTRL;<br>- msr = rdmsr(msrnum);<br>-<br>- msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */<br>- msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;<br>-<br>- msr.lo &= ~(0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);<br>- msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;<br>-<br>- msr.lo &= ~(0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);<br>- msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;<br>-<br>- msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);<br>- msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;<br>-<br>- msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);<br>- msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;<br>-<br>- msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);<br>- msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;<br>-<br>- msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);<br>- msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;<br>-<br>- msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);<br>- msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Set GLPCI Latency Timer. */<br>- msrnum = GLPCI_CTRL;<br>- msr = rdmsr(msrnum);<br>- msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone. */<br>- wrmsr(msrnum, msr);<br>-<br>- /* GLPCI_SPARE */<br>- msrnum = GLPCI_SPARE;<br>- msr = rdmsr(msrnum);<br>- msr.lo &= ~0x7;<br>- msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;<br>- wrmsr(msrnum, msr);<br>-}<br>-<br>-/* Enable Clock Gating. */<br>-static void ClockGatingInit(void)<br>-{<br>- msr_t msr;<br>- struct msrinit *gating = ClockGatingDefault;<br>- int i;<br>-<br>- for (i = 0; gating->msrnum != 0xffffffff; i++) {<br>- msr = rdmsr(gating->msrnum);<br>- msr.hi |= gating->msr.hi;<br>- msr.lo |= gating->msr.lo;<br>- wrmsr(gating->msrnum, msr); /* MSR - See the table above */<br>- gating += 1;<br>- }<br>-}<br>-<br>-static void GeodeLinkPriority(void)<br>-{<br>- msr_t msr = { 0, 0 };<br>-<br>- struct msrinit *prio = GeodeLinkPriorityTable;<br>- int i;<br>-<br>- for (i = 0; prio->msrnum != 0xffffffff; i++) {<br>- msr = rdmsr(prio->msrnum);<br>- msr.hi |= prio->msr.hi;<br>- msr.lo &= ~0xfff;<br>- msr.lo |= prio->msr.lo;<br>- wrmsr(prio->msrnum, msr); /* MSR - See the table above */<br>- prio += 1;<br>- }<br>-}<br>-<br>-/* Get the GLIU0 shadow register settings.<br>- *<br>- * If the setShadow function is used then all shadow descriptors<br>- * will stay sync'ed.<br>- */<br>-static uint64_t getShadow(void)<br>-{<br>- msr_t msr = { 0, 0 };<br>-<br>- msr = rdmsr(GLIU0_P2D_SC_0);<br>- return (((uint64_t) msr.hi) << 32) | msr.lo;<br>-}<br>-<br>-/* Set the cache RConf registers for the memory hole.<br>- *<br>- * Keeps all cache shadow descriptors sync'ed.<br>- * This is part of the PCI lockup solution.<br>- *<br>- * Entry: EDX:EAX is the shadow settings.<br>- */<br>-static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)<br>-{<br>- /* ok this is whacky bit translation time. */<br>- int bit;<br>- uint8_t shadowByte;<br>- msr_t msr = { 0, 0 };<br>- shadowByte = (uint8_t) (shadowLo >> 16);<br>-<br>- /* load up D000 settings in edx. */<br>- for (bit = 8; (bit > 4); bit--) {<br>- msr.hi <<= 8;<br>- msr.hi |= 1; /* cache disable PCI/Shadow memory */<br>- if (shadowByte && (1 << bit))<br>- msr.hi |= 0x20; /* write serialize PCI memory */<br>- }<br>-<br>- /* load up C000 settings in eax. */<br>- for (; bit; bit--) {<br>- msr.lo <<= 8;<br>- msr.lo |= 1; /* cache disable PCI/Shadow memory */<br>- if (shadowByte && (1 << bit))<br>- msr.lo |= 0x20; /* write serialize PCI memory */<br>- }<br>-<br>- wrmsr(CPU_RCONF_C0_DF, msr);<br>-<br>- shadowByte = (uint8_t) (shadowLo >> 24);<br>-<br>- /* load up F000 settings in edx. */<br>- for (bit = 8; (bit > 4); bit--) {<br>- msr.hi <<= 8;<br>- msr.hi |= 1; /* cache disable PCI/Shadow memory */<br>- if (shadowByte && (1 << bit))<br>- msr.hi |= 0x20; /* write serialize PCI memory */<br>- }<br>-<br>- /* load up E000 settings in eax. */<br>- for (; bit; bit--) {<br>- msr.lo <<= 8;<br>- msr.lo |= 1; /* cache disable PCI/Shadow memory */<br>- if (shadowByte && (1 << bit))<br>- msr.lo |= 0x20; /* write serialize PCI memory */<br>- }<br>-<br>- wrmsr(CPU_RCONF_E0_FF, msr);<br>-}<br>-<br>-/* Set the GLPCI registers for the memory hole.<br>- * Keeps all cache shadow descriptors sync'ed.<br>- * Entry: EDX:EAX is the shadow settings<br>- */<br>-static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)<br>-{<br>- msr_t msr;<br>-<br>- /* Set the Enable Register. */<br>- msr = rdmsr(GLPCI_REN);<br>- msr.lo &= 0xFFFF00FF;<br>- msr.lo |= ((shadowLo & 0xFFFF0000) >> 8);<br>- wrmsr(GLPCI_REN, msr);<br>-}<br>-<br>-/* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.<br>- * Keeps all shadow descriptors sync'ed.<br>- * Entry: EDX:EAX is the shadow settings<br>- */<br>-static void setShadow(uint64_t shadowSettings)<br>-{<br>- int i;<br>- msr_t msr;<br>- struct gliutable *pTable;<br>- uint32_t shadowLo, shadowHi;<br>-<br>- shadowLo = (uint32_t) shadowSettings;<br>- shadowHi = (uint32_t) (shadowSettings >> 32);<br>-<br>- setShadowRCONF(shadowHi, shadowLo);<br>- setShadowGLPCI(shadowHi, shadowLo);<br>-<br>- for (i = 0; gliutables[i]; i++) {<br>- for (pTable = gliutables[i]; pTable->desc_type != GL_END; pTable++) {<br>- if (pTable->desc_type == SC_SHADOW) {<br>-<br>- msr = rdmsr(pTable->desc_name);<br>- msr.lo = (uint32_t) shadowSettings;<br>- msr.hi &= 0xFFFF0000; /* maintain PDID in upper EDX */<br>- msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF;<br>- wrmsr(pTable->desc_name, msr); /* MSR - See the table above */<br>-<br>- }<br>- }<br>- }<br>-}<br>-<br>-static void rom_shadow_settings(void)<br>-{<br>- uint64_t shadowSettings = getShadow();<br>- shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; /* Disable read & writes */<br>- shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; /* Enable reads for C0000-FFFFF */<br>- setShadow(shadowSettings);<br>-}<br>-<br>-/* Set up RCONF_DEFAULT and any other RCONF registers needed.<br>- *<br>- * DEVRC_RCONF_DEFAULT:<br>- * ROMRC(63:56) = 04h ; write protect ROMBASE<br>- * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area<br>- * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.<br>- * SYSTOP(27:8) = top of system memory<br>- * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough<br>- */<br>-#define SYSMEM_RCONF_WRITETHROUGH 8<br>-#define DEVRC_RCONF_DEFAULT 0x21ul<br>-#define ROMBASE_RCONF_DEFAULT 0xFFFC0000<br>-#define ROMRC_RCONF_DEFAULT 0x25<br>-<br>-static void enable_L_cache(void)<br>-{<br>- struct gliutable *gl = 0;<br>- int i;<br>- msr_t msr;<br>- uint8_t SysMemCacheProp;<br>-<br>- /* Locate SYSMEM entry in GLIU0table */<br>- for (i = 0; gliu0table[i].desc_name != GL_END; i++) {<br>- if (gliu0table[i].desc_type == R_SYSMEM) {<br>- gl = &gliu0table[i];<br>- break;<br>- }<br>- }<br>- if (gl == 0) {<br>- post_code(0xCE); /* POST_RCONFInitError */<br>- while (1);<br>- }<br>-<br>-/* sysdescfound: */<br>- msr = rdmsr(gl->desc_name);<br>-<br>- /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the<br>- * top 8 bits go into 0-7 of edx.<br>- */<br>- msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF);<br>- msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;<br>- msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; /* 8 */<br>-<br>- /* Set Default SYSMEM region properties */<br>- msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; /* NOT writethrough == writeback 8 (or ~8) */<br>-<br>- /* Set PCI space cache properties */<br>- msr.hi = (DEVRC_RCONF_DEFAULT >> 4); /* setting is split betwwen hi and lo... */<br>- msr.lo |= (DEVRC_RCONF_DEFAULT << 28);<br>-<br>- /* Set the ROMBASE. This is usually FFFC0000h */<br>- msr.hi |= (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;<br>-<br>- /* Set ROMBASE cache properties. */<br>- msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));<br>-<br>- /* now program RCONF_DEFAULT */<br>- wrmsr(CPU_RCONF_DEFAULT, msr);<br>- printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi, msr.lo);<br>-<br>- /* RCONF_BYPASS: Cache tablewalk properties and SMM header access properties. */<br>- /* Set to match system memory cache properties. */<br>- msr = rdmsr(CPU_RCONF_DEFAULT);<br>- SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);<br>- msr = rdmsr(CPU_RCONF_BYPASS);<br>- msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;<br>- wrmsr(CPU_RCONF_BYPASS, msr);<br>- printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi, msr.lo);<br>-}<br>-<br>-static void setup_gx2_cache(void)<br>-{<br>- msr_t msr;<br>-<br>- enable_L_cache();<br>-<br>- /* Make sure all INVD instructions are treated as WBINVD. We do this<br>- * because we've found some programs which require this behavior.<br>- */<br>- msr = rdmsr(CPU_DM_CONFIG0);<br>- msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;<br>- wrmsr(CPU_DM_CONFIG0, msr);<br>-<br>- x86_enable_cache();<br>- wbinvd();<br>-}<br>-<br>-uint32_t get_systop(void)<br>-{<br>- struct gliutable *gl = 0;<br>- uint32_t systop;<br>- msr_t msr;<br>- int i;<br>-<br>- for (i = 0; gliu0table[i].desc_name != GL_END; i++) {<br>- if (gliu0table[i].desc_type == R_SYSMEM) {<br>- gl = &gliu0table[i];<br>- break;<br>- }<br>- }<br>- if (gl) {<br>- msr = rdmsr(gl->desc_name);<br>- systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8);<br>- systop += 0x1000; /* 4K */<br>- } else {<br>- systop =<br>- ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024;<br>- }<br>- return systop;<br>-}<br>-<br>-/* Core Logic initialization: Host bridge. */<br>-void northbridge_init_early(void)<br>-{<br>- int i;<br>- printk(BIOS_DEBUG, "Enter %s\n", __func__);<br>-<br>- for (i = 0; gliutables[i]; i++)<br>- GLIUInit(gliutables[i]);<br>-<br>- /* Now that the descriptor to memory is set up. */<br>- /* The memory controller needs one read to synch its lines before it can be used. */<br>- read32(zeroptr);<br>-<br>- GeodeLinkPriority();<br>-<br>- setup_gx2_cache();<br>-<br>- rom_shadow_settings();<br>-<br>- GLPCIInit();<br>-<br>- ClockGatingInit();<br>-<br>- __asm__ __volatile__("FINIT\n");<br>- printk(BIOS_DEBUG, "Exit %s\n", __func__);<br>-}<br>diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c<br>deleted file mode 100644<br>index 0bae76d..0000000<br>--- a/src/northbridge/amd/gx2/pll_reset.c<br>+++ /dev/null<br>@@ -1,195 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007 Advanced Micro Devices, Inc.<br>- * Copyright (C) 2010 Nils Jacobs<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <cpu/x86/tsc.h><br>-<br>-#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */<br>-#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */<br>-#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */<br>-<br>-/* spll_raw_clk = SYSREF * FbDIV,<br>- * GLIU Clock = spll_raw_clk / MDIV<br>- * CPU Clock = spll_raw_clk / VDIV<br>- */<br>-<br>-/* table for Feedback divisor to FbDiv register value */<br>-static const unsigned char plldiv2fbdiv[] = {<br>- 0, 0, 0, 0, 0, 0, 15, 7, 3, 1, 0, 32, 16, 40, 20, 42, /* pll div 0 - 15 */<br>- 21, 10, 37, 50, 25, 12, 38, 19, 9, 4, 34, 17, 8, 36, 18, 41, /* pll div 16 - 31 */<br>- 52, 26, 45, 54, 27, 13, 6, 35, 49, 56, 28, 46, 23, 11, 05, 02, /* pll div 32 - 47 */<br>- 33, 48, 24, 44, 22, 43, 53, 58, 29, 14, 39, 51, 57, 60, 30, 47, /* pll div 48 - 63 */<br>-};<br>-<br>-/* table for FbDiv register value to Feedback divisor */<br>-static const unsigned char fbdiv2plldiv[] = {<br>- 10, 9, 47, 8, 25, 46, 38, 7, 28, 24, 17, 45, 21, 37, 57, 6,<br>- 12, 27, 30, 23, 14, 16, 52, 44, 50, 20, 33, 36, 42, 56, 0, 0,<br>- 11, 48, 26, 39, 29, 18, 22, 58, 13, 31, 15, 53, 51, 34, 43, 0,<br>- 49, 40, 19, 59, 32, 54, 35, 0, 41, 60, 55, 0, 61, 0, 0, 0<br>-};<br>-<br>-/* FbDIV VDIV MDIV CPU/GeodeLink */<br>-/* 12 2 3 200/133 */<br>-/* 16 2 3 266/177 */<br>-/* 18 2 3 300/200 */<br>-/* 20 2 3 333/222 */<br>-/* 22 2 3 366/244 */<br>-/* 24 2 3 400/266 */<br>-/* 26 2 3 433/289 */<br>-<br>-/* PLLCHECK_COMPLETED is the "we've already done this" flag */<br>-#define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)<br>-<br>-#ifndef RSTPPL_LOWER_BYPASS_SET<br>-#define RSTPPL_LOWER_BYPASS_SET (1 << GLCP_SYS_RSTPLL_BYPASS)<br>-#endif // RSTPPL_LOWER_BYPASS_SET<br>-<br>-#define DEFAULT_MDIV 3<br>-#define DEFAULT_VDIV 2<br>-<br>-static void pll_reset(void)<br>-{<br>- msr_t msrGlcpSysRstpll;<br>- unsigned MDIV_VDIV_FBDIV;<br>- unsigned SyncBits; /* store the sync bits in up ebx */<br>- unsigned DEFAULT_FBDIV;<br>-<br>- if (CONFIG_GX2_PROCESSOR_MHZ == 400) {<br>- DEFAULT_FBDIV = 24;<br>- } else if (CONFIG_GX2_PROCESSOR_MHZ == 366) {<br>- DEFAULT_FBDIV = 22;<br>- } else if (CONFIG_GX2_PROCESSOR_MHZ == 300) {<br>- DEFAULT_FBDIV = 18;<br>- } else {<br>- post_code(POST_PLL_CPU_VER_FAIL);<br>- die("Unsupported GX2_PROCESSOR_MHZ setting!\n");<br>- }<br>-<br>- /* clear the Bypass bit */<br>-<br>- /* If the straps say we are in bypass and the syspll is not AND there are no software */<br>- /* bits set then FS2 or something set up the PLL and we should not change it. */<br>-<br>- msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);<br>- msrGlcpSysRstpll.lo &= ~RSTPPL_LOWER_BYPASS_SET;<br>- wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);<br>-<br>- /* If the "we've already been here" flag is set, don't reconfigure the pll */<br>- if (!(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED))<br>- { /* we haven't configured the PLL; do it now */<br>-<br>- /* Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the */<br>- /* correct Strap Table. */<br>- post_code(POST_PLL_INIT);<br>-<br>- /* configure for DDR */<br>- msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);<br>- wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);<br>-<br>- /* Use Manual settings */<br>- /* UseManual: */<br>- post_code(POST_PLL_MANUAL);<br>-<br>- /* DIV settings manually entered. */<br>- /* ax = VDIV, upper eax = MDIV, upper ecx = FbDIV */<br>- /* use gs and fs since we don't need them. */<br>-<br>- /* ProgramClocks: */<br>- /* ax = VDIV, upper eax = MDIV, upper ecx = FbDIV */<br>- /* move everything into ebx */<br>- /* VDIV */<br>- MDIV_VDIV_FBDIV = ((DEFAULT_VDIV - 2) << RSTPLL_UPPER_VDIV_SHIFT);<br>-<br>- /* MDIV */<br>- MDIV_VDIV_FBDIV |= ((DEFAULT_MDIV - 2) << RSTPLL_UPPER_MDIV_SHIFT);<br>-<br>- /* FbDIV */<br>- MDIV_VDIV_FBDIV |= (plldiv2fbdiv[DEFAULT_FBDIV] << RSTPLL_UPPER_FBDIV_SHIFT);<br>-<br>- /* write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values */<br>- msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);<br>- wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);<br>-<br>- msrGlcpSysRstpll.hi = MDIV_VDIV_FBDIV;<br>- wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);<br>-<br>- /* Set Reset, LockWait, and SW flag */<br>- /* DoReset: */<br>-<br>- /* CheckSemiSync proc */<br>- /* Check for Semi-Sync in GeodeLink and CPU. */<br>- /* We need to do this here since the strap settings don't account for these bits. */<br>- SyncBits = 0; /* store the sync bits in up ebx */<br>-<br>- /* Check for Bypass mode. */<br>- if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET)<br>- {<br>- /* If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will. */<br>- SyncBits |= RSTPPL_LOWER_CPU_SEMI_SYNC_SET;<br>- }<br>- else<br>- {<br>- /* CheckPCIsync: */<br>- /* If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater */<br>- /* look up the real divider... if we get a 0 we have serious problems */<br>- if (!(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] %<br>- (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)))<br>- {<br>- SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET;<br>- }<br>-<br>- /* CheckCPUSync: */<br>- /* If Vdiv/Mdiv is evenly divisible then set the CPU semi-sync. */<br>- /* CPU is always greater or equal. */<br>- if (!((((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x07) + 2) %<br>- (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_VDIV_SHIFT) & 0x0F) + 2)))<br>- {<br>- SyncBits |= RSTPPL_LOWER_CPU_SEMI_SYNC_SET;<br>- }<br>- }<br>-<br>- /* SetSync: */<br>- msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_PCI_SEMI_SYNC_SET | RSTPPL_LOWER_CPU_SEMI_SYNC_SET);<br>- msrGlcpSysRstpll.lo |= SyncBits;<br>- wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);<br>- /* CheckSemiSync endp */<br>-<br>- /* now we do the reset */<br>- /* Set hold count to 99 (063h) */<br>- msrGlcpSysRstpll.lo &= ~(0x0FF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);<br>- msrGlcpSysRstpll.lo |= (0x0DE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);<br>- msrGlcpSysRstpll.lo |= PLLCHECK_COMPLETED; // Say we are done<br>- wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);<br>-<br>- /* Don't want to use LOCKWAIT */<br>- msrGlcpSysRstpll.lo |= (RSTPPL_LOWER_PLL_RESET_SET + RSTPPL_LOWER_PD_SET);<br>- msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;<br>- wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);<br>-<br>- /* You should never get here..... The chip has reset. */<br>- post_code(POST_PLL_RESET_FAIL);<br>- die("CONFIGURING PLL FAILURE\n");<br>-<br>- } /* we haven't configured the PLL; do it now */<br>-<br>-}<br>-<br>-static unsigned int GeodeLinkSpeed(void)<br>-{<br>- unsigned geodelinkspeed;<br>- geodelinkspeed = ((CONFIG_GX2_PROCESSOR_MHZ * DEFAULT_VDIV) / DEFAULT_MDIV);<br>- return (geodelinkspeed);<br>-}<br>diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c<br>deleted file mode 100644<br>index 6e66d7d..0000000<br>--- a/src/northbridge/amd/gx2/raminit.c<br>+++ /dev/null<br>@@ -1,606 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007 Advanced Micro Devices, Inc.<br>- * Copyright (C) 2010 Nils Jacobs<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <cpu/amd/gx2def.h><br>-#include <spd.h><br>-#include <stddef.h><br>-<br>-static const unsigned char NumColAddr[] = {<br>- 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,<br>- 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,<br>-};<br>-<br>-static void __attribute__((noreturn)) hcf(void)<br>-{<br>- printk(BIOS_EMERG, "DIE\n");<br>- /* this guarantees we flush the UART fifos (if any) and also<br>- * ensures that things, in general, keep going so no debug output<br>- * is lost<br>- */<br>- while (1)<br>- printk(BIOS_EMERG, (0));<br>-}<br>-<br>-static void auto_size_dimm(unsigned int dimm)<br>-{<br>- uint32_t dimm_setting;<br>- uint16_t dimm_size;<br>- uint8_t spd_byte;<br>- msr_t msr;<br>-<br>- dimm_setting = 0;<br>-<br>- printk(BIOS_DEBUG, "Check present\n");<br>- /* Check that we have a dimm */<br>- if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {<br>- return;<br>- }<br>-<br>- printk(BIOS_DEBUG, "MODBANKS\n");<br>- /* Field: Module Banks per DIMM */<br>- /* EEPROM byte usage: (5) Number of DIMM Banks */<br>- spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);<br>- if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {<br>- printk(BIOS_EMERG, "Number of module banks not compatible\n");<br>- post_code(ERROR_BANK_SET);<br>- hcf();<br>- }<br>- dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;<br>-<br>- printk(BIOS_DEBUG, "FIELDBANKS\n");<br>- /* Field: Banks per SDRAM device */<br>- /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */<br>- spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);<br>- if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {<br>- printk(BIOS_EMERG, "Number of device banks not compatible\n");<br>- post_code(ERROR_BANK_SET);<br>- hcf();<br>- }<br>- dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;<br>-<br>- printk(BIOS_DEBUG, "SPDNUMROWS\n");<br>- /* Field: DIMM size<br>- * EEPROM byte usage:<br>- * (3) Number of Row Addresses<br>- * (4) Number of Column Addresses<br>- * (5) Number of DIMM Banks<br>- * (31) Module Bank Density<br>- * Size = Module Density * Module Banks<br>- */<br>- if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)<br>- || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {<br>- printk(BIOS_EMERG, "Asymmetric DIMM not compatible\n");<br>- post_code(ERROR_UNSUPPORTED_DIMM);<br>- hcf();<br>- }<br>-<br>- printk(BIOS_DEBUG, "SPDBANKDENSITY\n");<br>- dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);<br>- printk(BIOS_DEBUG, "DIMMSIZE\n");<br>- dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */<br>- dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */<br>-<br>- /* Module Density * Module Banks */<br>- dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */<br>- printk(BIOS_DEBUG, "BEFORT CTZ\n");<br>- dimm_size = __builtin_ctz(dimm_size);<br>- printk(BIOS_DEBUG, "TEST DIMM SIZE > 7\n");<br>- if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */<br>- printk(BIOS_EMERG, "Only support up to 512MB per DIMM\n");<br>- post_code(ERROR_DENSITY_DIMM);<br>- hcf();<br>- }<br>- dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;<br>- printk(BIOS_DEBUG, "PAGESIZE\n");<br>-<br>-/*<br>- * Field: PAGE size<br>- * EEPROM byte usage: (4) Number of Column Addresses<br>- * PageSize = 2^# Column Addresses * Data width in bytes<br>- * (should be 8bytes for a normal DIMM)<br>- *<br>- * But this really works by magic.<br>- * If ma[11:0] is the memory address pins, and pa[13:0] is the physical column<br>- * address that MC generates, here is how the MC assigns the pa onto the<br>- * ma pins:<br>- *<br>- * ma 11 10 09 08 07 06 05 04 03 02 01 00<br>- * ---------------------------------------<br>- * pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)<br>- * pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)<br>- * pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)<br>- * pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)<br>- * pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)<br>- *<br>- * (AP = autoprecharge bit)<br>- *<br>- * Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),<br>- * so lower 3 address bits are dont_cares. So from the table above,<br>- * it's easier to see what the old code is doing: if for example,<br>- * #col_addr_bits = 7(06h), it adds 3 to get 10, then does 2^10 = 1K.<br>- */<br>-<br>- spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];<br>- printk(BIOS_DEBUG, "MAXCOLADDR\n");<br>- if (spd_byte > MAX_COL_ADDR) {<br>- printk(BIOS_EMERG, "DIMM page size not compatible\n");<br>- post_code(ERROR_SET_PAGE);<br>- hcf();<br>- }<br>- printk(BIOS_DEBUG, ">11address test\n");<br>- spd_byte -= 7;<br>- if (spd_byte > 4) { /* if the value is above 4 it means > 11 col address lines */<br>- spd_byte = 7; /* which means > 16k so set to disabled */<br>- }<br>- dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k, 1 = 2k, 2 = 4k, etc */<br>-<br>- printk(BIOS_DEBUG, "RDMSR CF07\n");<br>- msr = rdmsr(MC_CF07_DATA);<br>- printk(BIOS_DEBUG, "WRMSR CF07\n");<br>- if (dimm == DIMM0) {<br>- msr.hi &= 0xFFFF0000;<br>- msr.hi |= dimm_setting;<br>- } else {<br>- msr.hi &= 0x0000FFFF;<br>- msr.hi |= dimm_setting << 16;<br>- }<br>- wrmsr(MC_CF07_DATA, msr);<br>- printk(BIOS_DEBUG, "ALL DONE\n");<br>-}<br>-<br>-static void checkDDRMax(void)<br>-{<br>- uint8_t spd_byte0, spd_byte1;<br>- uint16_t speed;<br>-<br>- /* PC133 identifier */<br>- spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);<br>- if (spd_byte0 == 0xFF) {<br>- spd_byte0 = 0;<br>- }<br>- spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);<br>- if (spd_byte1 == 0xFF) {<br>- spd_byte1 = 0;<br>- }<br>-<br>- /* Use the slowest DIMM */<br>- if (spd_byte0 < spd_byte1) {<br>- spd_byte0 = spd_byte1;<br>- }<br>-<br>- /* Turn SPD ns time into MHZ. Check what the asm does to this math. */<br>- speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));<br>-<br>- /* current speed > max speed? */<br>- if (GeodeLinkSpeed() > speed) {<br>- printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");<br>- post_code(POST_PLL_MEM_FAIL);<br>- hcf();<br>- }<br>-}<br>-<br>-const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */<br>-<br>-static void set_refresh_rate(void)<br>-{<br>- uint8_t spd_byte0, spd_byte1;<br>- uint16_t rate0, rate1;<br>- msr_t msr;<br>-<br>- spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);<br>- spd_byte0 &= 0xF;<br>- if (spd_byte0 > 5) {<br>- spd_byte0 = 5;<br>- }<br>- rate0 = REF_RATE[spd_byte0];<br>-<br>- spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);<br>- spd_byte1 &= 0xF;<br>- if (spd_byte1 > 5) {<br>- spd_byte1 = 5;<br>- }<br>- rate1 = REF_RATE[spd_byte1];<br>-<br>- /* Use the faster rate (lowest number) */<br>- if (rate0 > rate1) {<br>- rate0 = rate1;<br>- }<br>-<br>- msr = rdmsr(MC_CF07_DATA);<br>- msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)<br>- << CF07_LOWER_REF_INT_SHIFT;<br>- wrmsr(MC_CF07_DATA, msr);<br>-}<br>-<br>-const uint8_t CASDDR[] = { 5, 5, 2, 6, 0 }; /* 1(1.5), 1.5, 2, 2.5, 0 */<br>-<br>-static u8 getcasmap(u32 dimm, u16 glspeed)<br>-{<br>- u16 dimm_speed;<br>- u8 spd_byte, casmap, casmap_shift = 0;<br>-<br>- /************************** DIMM0 **********************************/<br>- casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);<br>- if (casmap != 0xFF) {<br>- /* IF -.5 timing is supported, check -.5 timing > GeodeLink */<br>- spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);<br>- if (spd_byte != 0) {<br>- /* Turn SPD ns time into MHZ. Check what the asm does to this math. */<br>- dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));<br>- if (dimm_speed >= glspeed) {<br>- casmap_shift = 1; /* -.5 is a shift of 1 */<br>- /* IF -1 timing is supported, check -1 timing > GeodeLink */<br>- spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);<br>- if (spd_byte != 0) {<br>- /* Turn SPD ns time into MHZ. Check what the asm does to this math. */<br>- dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));<br>- if (dimm_speed >= glspeed) {<br>- casmap_shift = 2; /* -1 is a shift of 2 */<br>- }<br>- } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */<br>- } else {<br>- casmap_shift = 0;<br>- }<br>- } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */<br>- /* set the casmap based on the shift to limit possible CAS settings */<br>- spd_byte = 31 - __builtin_clz((uint32_t) casmap);<br>- /* just want bits in the lower byte since we have to cast to a 32 */<br>- casmap &= 0xFF << (spd_byte - casmap_shift);<br>- } else { /* No DIMM */<br>- casmap = 0;<br>- }<br>- return casmap;<br>-}<br>-<br>-static void setCAS(void)<br>-{<br>-/*<br>- * setCAS<br>- * EEPROM byte usage: (18) SDRAM device attributes - CAS latency<br>- * EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5<br>- * EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1<br>- *<br>- * The CAS setting is based on the information provided in each DIMMs SPD.<br>- * The speed at which a DIMM can run is described relative to the slowest<br>- * CAS the DIMM supports. Each speed for the relative CAS settings is<br>- * checked that it is within the GeodeLink speed. If it isn't within the GeodeLink<br>- * speed, the CAS setting is removed from the list of good settings for<br>- * the DIMM. This is done for both DIMMs and the lists are compared to<br>- * find the lowest common CAS latency setting. If there are no CAS settings<br>- * in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.<br>- *<br>- * Entry:<br>- * Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.<br>- * Destroys: We really use everything !<br>- */<br>- uint16_t glspeed;<br>- uint8_t spd_byte, casmap0, casmap1;<br>- msr_t msr;<br>-<br>- glspeed = GeodeLinkSpeed();<br>-<br>- casmap0 = getcasmap(DIMM0, glspeed);<br>- casmap1 = getcasmap(DIMM1, glspeed);<br>-<br>- /* CAS_LAT MAP COMPARE */<br>- if (casmap0 == 0) {<br>- spd_byte = CASDDR[__builtin_ctz(casmap1)];<br>- } else if (casmap1 == 0) {<br>- spd_byte = CASDDR[__builtin_ctz(casmap0)];<br>- } else if ((casmap0 &= casmap1)) {<br>- spd_byte = CASDDR[__builtin_ctz(casmap0)];<br>- } else {<br>- printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");<br>- post_code(ERROR_DIFF_DIMMS);<br>- hcf();<br>- }<br>-<br>- msr = rdmsr(MC_CF8F_DATA);<br>- msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);<br>- msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;<br>- wrmsr(MC_CF8F_DATA, msr);<br>-}<br>-<br>-static void set_latencies(void)<br>-{<br>- uint32_t memspeed, dimm_setting;<br>- uint8_t spd_byte0, spd_byte1;<br>- msr_t msr;<br>-<br>- memspeed = GeodeLinkSpeed() / 2;<br>- dimm_setting = 0;<br>-<br>- /* MC_CF8F setup */<br>- /* tRAS */<br>- spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);<br>- if (spd_byte0 == 0xFF) {<br>- spd_byte0 = 0;<br>- }<br>- spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);<br>- if (spd_byte1 == 0xFF) {<br>- spd_byte1 = 0;<br>- }<br>- if (spd_byte0 < spd_byte1) {<br>- spd_byte0 = spd_byte1;<br>- }<br>- /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */<br>- spd_byte1 = (spd_byte0 * memspeed) / 1000;<br>- if (((spd_byte0 * memspeed) % 1000)) {<br>- ++spd_byte1;<br>- }<br>- if (spd_byte1 > 6) {<br>- --spd_byte1;<br>- }<br>- dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;<br>-<br>- /* tRP */<br>- spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);<br>- if (spd_byte0 == 0xFF) {<br>- spd_byte0 = 0;<br>- }<br>- spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);<br>- if (spd_byte1 == 0xFF) {<br>- spd_byte1 = 0;<br>- }<br>- if (spd_byte0 < spd_byte1) {<br>- spd_byte0 = spd_byte1;<br>- }<br>- /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */<br>- spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;<br>- if ((((spd_byte0 >> 2) * memspeed) % 1000)) {<br>- ++spd_byte1;<br>- }<br>- dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;<br>-<br>- /* tRCD */<br>- spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);<br>- if (spd_byte0 == 0xFF) {<br>- spd_byte0 = 0;<br>- }<br>- spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);<br>- if (spd_byte1 == 0xFF) {<br>- spd_byte1 = 0;<br>- }<br>- if (spd_byte0 < spd_byte1) {<br>- spd_byte0 = spd_byte1;<br>- }<br>- /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */<br>- spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;<br>- if ((((spd_byte0 >> 2) * memspeed) % 1000)) {<br>- ++spd_byte1;<br>- }<br>- dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;<br>-<br>- /* tRRD */<br>- spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);<br>- if (spd_byte0 == 0xFF) {<br>- spd_byte0 = 0;<br>- }<br>- spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);<br>- if (spd_byte1 == 0xFF) {<br>- spd_byte1 = 0;<br>- }<br>- if (spd_byte0 < spd_byte1) {<br>- spd_byte0 = spd_byte1;<br>- }<br>- /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */<br>- spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;<br>- if ((((spd_byte0 >> 2) * memspeed) % 1000)) {<br>- ++spd_byte1;<br>- }<br>- dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;<br>-<br>- /* tRC = tRP + tRAS */<br>- dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +<br>- ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))<br>- << CF8F_LOWER_REF2ACT_SHIFT;<br>-<br>- msr = rdmsr(MC_CF8F_DATA);<br>- msr.lo &= 0xF00000FF;<br>- msr.lo |= dimm_setting;<br>- msr.hi |= CF8F_UPPER_REORDER_DIS_SET;<br>- wrmsr(MC_CF8F_DATA, msr);<br>- printk(BIOS_DEBUG, "MSR MC_CF8F_DATA (%08x) value is %08x:%08x\n",<br>- MC_CF8F_DATA, msr.hi, msr.lo);<br>-}<br>-<br>-static void set_extended_mode_registers(void)<br>-{<br>- uint8_t spd_byte0, spd_byte1;<br>- msr_t msr;<br>- spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);<br>- if (spd_byte0 == 0xFF) {<br>- spd_byte0 = 0;<br>- }<br>- spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);<br>- if (spd_byte1 == 0xFF) {<br>- spd_byte1 = 0;<br>- }<br>- spd_byte1 &= spd_byte0;<br>-<br>- msr = rdmsr(MC_CF07_DATA);<br>- if (spd_byte1 & 1) { /* Drive Strength Control */<br>- msr.lo |= CF07_LOWER_EMR_DRV_SET;<br>- }<br>- if (spd_byte1 & 2) { /* FET Control */<br>- msr.lo |= CF07_LOWER_EMR_QFC_SET;<br>- }<br>- wrmsr(MC_CF07_DATA, msr);<br>-}<br>-<br>-static void sdram_set_registers(const struct mem_controller *ctrl)<br>-{<br>- msr_t msr;<br>- uint32_t msrnum;<br>-<br>- /* Set Refresh Staggering */<br>- msrnum = MC_CF07_DATA;<br>- msr = rdmsr(msrnum);<br>- msr.lo &= ~0xC0;<br>- msr.lo |= 0x0; /* set refresh to 4SDRAM clocks */<br>- wrmsr(msrnum, msr);<br>-}<br>-<br>-static void sdram_set_spd_registers(const struct mem_controller *ctrl)<br>-{<br>- uint8_t spd_byte;<br>-<br>- printk(BIOS_DEBUG, "sdram_set_spd_register\n");<br>- post_code(POST_MEM_SETUP); /* post_70h */<br>-<br>- spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);<br>- printk(BIOS_DEBUG, "Check DIMM 0\n");<br>- /* Check DIMM is not Register and not Buffered DIMMs. */<br>- if ((spd_byte != 0xFF) && (spd_byte & 3)) {<br>- printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n");<br>- post_code(ERROR_UNSUPPORTED_DIMM);<br>- hcf();<br>- }<br>- printk(BIOS_DEBUG, "Check DIMM 1\n");<br>- spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);<br>- if ((spd_byte != 0xFF) && (spd_byte & 3)) {<br>- printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n");<br>- post_code(ERROR_UNSUPPORTED_DIMM);<br>- hcf();<br>- }<br>-<br>- post_code(POST_MEM_SETUP2); /* post_72h */<br>- printk(BIOS_DEBUG, "Check DDR MAX\n");<br>-<br>- /* Check that the memory is not overclocked. */<br>- checkDDRMax();<br>-<br>- /* Size the DIMMS */<br>- post_code(POST_MEM_SETUP3); /* post_73h */<br>- printk(BIOS_DEBUG, "AUTOSIZE DIMM 0\n");<br>- auto_size_dimm(DIMM0);<br>- post_code(POST_MEM_SETUP4); /* post_74h */<br>- printk(BIOS_DEBUG, "AUTOSIZE DIMM 1\n");<br>- auto_size_dimm(DIMM1);<br>-<br>- /* Set CAS latency */<br>- printk(BIOS_DEBUG, "set cas latency\n");<br>- post_code(POST_MEM_SETUP5); /* post_75h */<br>- setCAS();<br>-<br>- /* Set all the other latencies here (tRAS, tRP....) */<br>- printk(BIOS_DEBUG, "set all latency\n");<br>- set_latencies();<br>-<br>- /* Set Extended Mode Registers */<br>- printk(BIOS_DEBUG, "set emrs\n");<br>- set_extended_mode_registers();<br>-<br>- printk(BIOS_DEBUG, "set ref rate\n");<br>- /* Set Memory Refresh Rate */<br>- set_refresh_rate();<br>-}<br>-<br>-/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence<br>- * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */<br>-static void sdram_enable(int controllers, const struct mem_controller *ctrl)<br>-{<br>- int i;<br>- msr_t msr;<br>-<br>- /* 2. clock gating for PMode */<br>- msr = rdmsr(MC_GLD_MSR_PM);<br>- msr.lo &= ~0x04;<br>- msr.lo |= 0x01;<br>- wrmsr(MC_GLD_MSR_PM, msr);<br>- /* undocmented bits in GX, in LX there are<br>- * 8 bits in PM1_UP_DLY */<br>- msr = rdmsr(MC_CF1017_DATA);<br>- msr.lo = 0x0101;<br>- wrmsr(MC_CF1017_DATA, msr);<br>- printk(BIOS_DEBUG, "sdram_enable step 2\n");<br>-<br>- /* 3. release CKE mask to enable CKE */<br>- msr = rdmsr(MC_CFCLK_DBUG);<br>- msr.lo &= ~(0x03 << 8);<br>- wrmsr(MC_CFCLK_DBUG, msr);<br>- printk(BIOS_DEBUG, "sdram_enable step 3\n");<br>-<br>- /* 4. set and clear REF_TST 16 times, more shouldn't hurt<br>- * why this is before EMRS and MRS ? */<br>- for (i = 0; i < 19; i++) {<br>- msr = rdmsr(MC_CF07_DATA);<br>- msr.lo |= (0x01 << 3);<br>- wrmsr(MC_CF07_DATA, msr);<br>- msr.lo &= ~(0x01 << 3);<br>- wrmsr(MC_CF07_DATA, msr);<br>- }<br>- printk(BIOS_DEBUG, "sdram_enable step 4\n");<br>-<br>- /* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */<br>- msr = rdmsr(MC_CF07_DATA);<br>- msr.lo |= ((0x01 << 28) | 0x01);<br>- wrmsr(MC_CF07_DATA, msr);<br>- msr.lo &= ~((0x01 << 28) | 0x01);<br>- wrmsr(MC_CF07_DATA, msr);<br>- printk(BIOS_DEBUG, "sdram_enable step 6\n");<br>-<br>- /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,<br>- * it is documented in LX datasheet */<br>- /* load Mode Register by set and clear PROG_DRAM */<br>- msr = rdmsr(MC_CF07_DATA);<br>- msr.lo |= ((0x01 << 27) | 0x01);<br>- wrmsr(MC_CF07_DATA, msr);<br>- msr.lo &= ~((0x01 << 27) | 0x01);<br>- wrmsr(MC_CF07_DATA, msr);<br>- printk(BIOS_DEBUG, "sdram_enable step 7\n");<br>-<br>- /* 8. load Mode Register by set and clear PROG_DRAM */<br>- msr = rdmsr(MC_CF07_DATA);<br>- msr.lo |= 0x01;<br>- wrmsr(MC_CF07_DATA, msr);<br>- msr.lo &= ~0x01;<br>- wrmsr(MC_CF07_DATA, msr);<br>- printk(BIOS_DEBUG, "sdram_enable step 8\n");<br>-<br>- /* wait 200 SDCLKs */<br>- for (i = 0; i < 200; i++)<br>- outb(0xaa, 0x80);<br>-<br>- /* load RDSYNC */<br>- msr = rdmsr(MC_CF_RDSYNC);<br>- msr.hi = 0x000ff310;<br>- /* the above setting is supposed to be good for "slow" ram. We have found that for<br>- * some dram, at some clock rates, e.g. hynix at 366/244, this will actually<br>- * cause errors. The fix is to just set it to 0x310. Tested on 3 boards<br>- * with 3 different type of dram -- Hynix, PSC, infineon.<br>- * I am leaving this comment here so that at some future time nobody is tempted<br>- * to mess with this setting -- RGM, 9/2006<br>- */<br>- msr.hi = 0x00000310;<br>- msr.lo = 0x00000000;<br>- wrmsr(MC_CF_RDSYNC, msr);<br>-<br>- /* set delay control */<br>- msr = rdmsr(GLCP_DELAY_CONTROLS);<br>- msr.hi = 0x830d415a;<br>- msr.lo = 0x8ea0ad6a;<br>- wrmsr(GLCP_DELAY_CONTROLS, msr);<br>-<br>- /* The RAM dll needs a write to lock on so generate a few dummy writes */<br>- /* Note: The descriptor needs to be enabled to point at memory */<br>- for (i = 0; i < 5; i++) {<br>- write32(zeroptr + i, i);<br>- }<br>-<br>- printk(BIOS_INFO, "RAM DLL lock\n");<br>-<br>-}<br>diff --git a/src/northbridge/amd/gx2/raminit.h b/src/northbridge/amd/gx2/raminit.h<br>deleted file mode 100644<br>index a49bf20..0000000<br>--- a/src/northbridge/amd/gx2/raminit.h<br>+++ /dev/null<br>@@ -1,12 +0,0 @@<br>-#ifndef RAMINIT_H<br>-#define RAMINIT_H<br>-<br>-#define DIMM_SOCKETS 2<br>-<br>-struct mem_controller {<br>- uint16_t channel0[DIMM_SOCKETS];<br>-};<br>-<br>-void sdram_initialize(int controllers, const struct mem_controller *ctrl);<br>-<br>-#endif /* RAMINIT_H */<br>diff --git a/src/southbridge/amd/cs5535/Kconfig b/src/southbridge/amd/cs5535/Kconfig<br>deleted file mode 100644<br>index 8fcff28..0000000<br>--- a/src/southbridge/amd/cs5535/Kconfig<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config SOUTHBRIDGE_AMD_CS5535<br>- bool<br>diff --git a/src/southbridge/amd/cs5535/Makefile.inc b/src/southbridge/amd/cs5535/Makefile.inc<br>deleted file mode 100644<br>index 3785cd4..0000000<br>--- a/src/southbridge/amd/cs5535/Makefile.inc<br>+++ /dev/null<br>@@ -1,8 +0,0 @@<br>-ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5535),y)<br>-<br>-ramstage-y += cs5535.c<br>-#ramstage-y += pci.c<br>-#ramstage-y += ide.c<br>-ramstage-y += chipsetinit.c<br>-<br>-endif<br>diff --git a/src/southbridge/amd/cs5535/chip.h b/src/southbridge/amd/cs5535/chip.h<br>deleted file mode 100644<br>index 37e5ead..0000000<br>--- a/src/southbridge/amd/cs5535/chip.h<br>+++ /dev/null<br>@@ -1,8 +0,0 @@<br>-#ifndef _SOUTHBRIDGE_AMD_CS5535<br>-#define _SOUTHBRIDGE_AMD_CS5535<br>-<br>-struct southbridge_amd_cs5535_config {<br>- int setupflash;<br>-};<br>-<br>-#endif /* _SOUTHBRIDGE_AMD_CS5535 */<br>diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c<br>deleted file mode 100644<br>index 1b7fe5d..0000000<br>--- a/src/southbridge/amd/cs5535/chipsetinit.c<br>+++ /dev/null<br>@@ -1,356 +0,0 @@<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include "chip.h"<br>-#include "northbridge/amd/gx2/northbridge.h"<br>-#include <cpu/amd/gx2def.h><br>-#include <cpu/x86/msr.h><br>-#include <cpu/x86/cache.h><br>-#include "southbridge/amd/cs5535/cs5535.h"<br>-<br>-/* the structs in this file only set msr.lo. But ... that may not always be true */<br>-<br>-struct msrinit {<br>- unsigned long msrnum;<br>- msr_t msr;<br>-};<br>-<br>-/* Master Configuration Register for Bus Masters. */<br>-static struct msrinit SB_MASTER_CONF_TABLE[] = {<br>- { USB1_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} }, /* NOTE: Must be 1st entry in table */<br>- { USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} },<br>- { ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000} },<br>- { AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} },<br>- { MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000} },<br>-/* GLPCI_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/<br>-/* GLCP_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/<br>-/* GLIU_SB_GLD_MSR_CONF, 0x0*/<br>- {0,{0,0}}<br>-};<br>-<br>-/* 5535_A3 Clock Gating*/<br>-static struct msrinit CS5535_CLOCK_GATING_TABLE[] = {<br>- { USB1_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },<br>- { USB2_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },<br>- { GLIU_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000004} },<br>- { GLPCI_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },<br>- { GLCP_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000004} },<br>- { MDD_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x050554111} },<br>- { ATA_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },<br>- { AC97_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },<br>- { 0, {.hi = 0, .lo = 0x000000000} }<br>-};<br>-<br>-#ifdef UNUSED_CODE<br>-struct acpiinit {<br>- unsigned short ioreg;<br>- unsigned long regdata;<br>- unsigned short iolen;<br>-};<br>-<br>-static struct acpiinit acpi_init_table[] = {<br>- {ACPI_BASE+0x00, 0x01000000, 4},<br>- {ACPI_BASE+0x08, 0, 4},<br>- {ACPI_BASE+0x0C, 0, 4},<br>- {ACPI_BASE+0x1C, 0, 4},<br>- {ACPI_BASE+0x18, 0x0FFFFFFFF, 4},<br>- {ACPI_BASE+0x00, 0x0000FFFF, 4},<br>-<br>- {PM_SCLK, 0x000000E00, 4},<br>- {PM_SED, 0x000004601, 4},<br>- {PM_SIDD, 0x000008C02, 4},<br>- {PM_WKD, 0x0000000A0, 4},<br>- {PM_WKXD, 0x0000000A0, 4},<br>- {0,0,0}<br>-};<br>-<br>-/*****************************************************************************<br>- *<br>- * pmChipsetInit<br>- *<br>- * Program ACPI LBAR and initialize ACPI registers.<br>- *<br>- *****************************************************************************/<br>-static void pmChipsetInit(void)<br>-{<br>- unsigned long val = 0;<br>- unsigned short port;<br>-<br>- port = (PMLogic_BASE + 0x010);<br>- val = 0x0E00 ; /* 1ms*/<br>- outl(val, port);<br>-<br>- /* PM_WKXD*/<br>- /* Make sure bits[3:0]=0000b to clear the*/<br>- /* saved Sx state*/<br>- port = (PMLogic_BASE + 0x034);<br>- val = 0x0A0 ; /* 5ms*/<br>- outl(val, port);<br>-<br>- /* PM_WKD*/<br>- port = (PMLogic_BASE + 0x030);<br>- outl(val, port);<br>-<br>- /* PM_SED*/<br>- port = (PMLogic_BASE + 0x014);<br>- val = 0x04601 ; /* 5ms*/<br>- outl(val, port);<br>-<br>- /* PM_SIDD*/<br>- port = (PMLogic_BASE + 0x020);<br>- val = 0x08C02 ; /* 10ms*/<br>- outl(val, port);<br>-<br>- /* GPIO24 OUT_AUX1 function is the external signal for 5535's<br>- * vsb_working_aux which is de-asserted when 5535 enters Standby (S3 or<br>- * S5) state. On Hawk, GPIO24 controls all voltage rails except Vmem<br>- * and Vstandby. This means GX2 will be fully de-powered if this<br>- * control de-asserts in S3/S5.<br>- */<br>-<br>- /* GPIO24 is setup in preChipsetInit for two reasons<br>- * 1. GPIO24 at reset defaults to disabled, since this signal is<br>- * vsb_work_aux on Hawk it controls the FET's for all voltage<br>- * rails except Vstandby & Vmem. BIOS needs to enable GPIO24 as<br>- * OUT_AUX1 & OUTPUT_EN early so it is driven by 5535.<br>- * 2. Non-PM builds will require GPIO24 enabled for instant-off power<br>- * button<br>- */<br>-<br>- /* GPIO11 OUT_AUX1 function is the external signal for 5535's<br>- * slp_clk_n which is asserted when 5535 enters Sleep(S1) state.<br>- * On Hawk, GPIO11 is connected to control input of external clock<br>- * generator for 14MHz, PCI, USB & LPC clocks.<br>- * Programming of GPIO11 will be done by VSA PM code. During VSA<br>- * Init. BIOS writes PM Core Virtual Register indicating if S1 Clocks<br>- * should be On or Off. This is based on a Setup item. We do not want<br>- * to leave GPIO11 enabled because of a Hawk board problem. With<br>- * GPIO11 enabled in S3, something is back-driving GPIO11 causing it<br>- * to float to 1.6-1.7V.<br>- */<br>-}<br>-#endif<br>-<br>-struct FLASH_DEVICE {<br>- unsigned char fType; /* Flash type: NOR or NAND */<br>- unsigned char fInterface; /* Flash interface: I/O or Memory */<br>- unsigned long fMask; /* Flash size/mask */<br>-};<br>-<br>-static struct FLASH_DEVICE FlashInitTable[] = {<br>- { FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K }, /* CS0, or Flash Device 0 */<br>- { FLASH_TYPE_NONE, 0, 0 }, /* CS1, or Flash Device 1 */<br>- { FLASH_TYPE_NONE, 0, 0 }, /* CS2, or Flash Device 2 */<br>- { FLASH_TYPE_NONE, 0, 0 }, /* CS3, or Flash Device 3 */<br>-};<br>-<br>-#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))<br>-<br>-static uint32_t FlashPort[] = {<br>- MDD_LBAR_FLSH0,<br>- MDD_LBAR_FLSH1,<br>- MDD_LBAR_FLSH2,<br>- MDD_LBAR_FLSH3<br>-};<br>-<br>-/***************************************************************************<br>- *<br>- * ChipsetFlashSetup<br>- *<br>- * Flash LBARs need to be setup before VSA init so the PCI BARs have<br>- * correct size info. Call this routine only if flash needs to be<br>- * configured (don't call it if you want IDE).<br>- *<br>- **************************************************************************/<br>-static void ChipsetFlashSetup(void)<br>-{<br>- msr_t msr;<br>- int i;<br>- int numEnabled = 0;<br>-<br>- printk(BIOS_DEBUG, "ChipsetFlashSetup++\n");<br>- for (i = 0; i < FlashInitTableLen; i++) {<br>- if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {<br>- printk(BIOS_DEBUG, "Enable CS%d\n", i);<br>- /* we need to configure the memory/IO mask */<br>- msr = rdmsr(FlashPort[i]);<br>- msr.hi = 0; /* start with the "enabled" bit clear */<br>- if (FlashInitTable[i].fType == FLASH_TYPE_NAND)<br>- msr.hi |= 0x00000002;<br>- else<br>- msr.hi &= ~0x00000002;<br>- if (FlashInitTable[i].fInterface == FLASH_IF_MEM)<br>- msr.hi |= 0x00000004;<br>- else<br>- msr.hi &= ~0x00000004;<br>- msr.hi |= FlashInitTable[i].fMask;<br>- printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);<br>- wrmsr(FlashPort[i], msr);<br>-<br>- /* now write-enable the device */<br>- msr = rdmsr(MDD_NORF_CNTRL);<br>- msr.lo |= (1 << i);<br>- printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);<br>- wrmsr(MDD_NORF_CNTRL, msr);<br>-<br>- /* update the number enabled */<br>- numEnabled++;<br>- }<br>- }<br>-<br>- /* enable the flash */<br>- if (0 != numEnabled) {<br>- msr = rdmsr(MDD_PIN_OPT);<br>- msr.lo &= ~1; /* PIN_OPT_IDE */<br>- printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);<br>- wrmsr(MDD_PIN_OPT, msr);<br>- }<br>-<br>- printk(BIOS_DEBUG, "ChipsetFlashSetup--\n");<br>-}<br>-<br>-<br>-<br>-/****************************************************************************<br>- *<br>- * ChipsetGeodeLinkInit<br>- *<br>- * Handle chipset specific GeodeLink settings here.<br>- * Called from GeodeLink init code.<br>- *<br>- ****************************************************************************/<br>-static void<br>-ChipsetGeodeLinkInit(void)<br>-{<br>- msr_t msr;<br>- unsigned long msrnum;<br>- unsigned long totalmem;<br>-<br>- /* SWASIF for A1 DMA */<br>- /* Set all memory to "just above systop" PCI so DMA will work */<br>-<br>- /* check A1 */<br>- msrnum = MSR_SB_GLCP + 0x17;<br>- msr = rdmsr(msrnum);<br>- if ((msr.lo&0xff) == 0x11)<br>- return;<br>-<br>- totalmem = (sizeram() << 20) - 1; // highest address<br>- totalmem >>= 12;<br>- totalmem = ~totalmem;<br>- totalmem &= 0xfffff;<br>- msr.lo = totalmem;<br>- msr.hi = 0x20000000; /* Port 1 (PCI) */<br>- msrnum = MSR_SB_GLIU + 0x20;<br>- wrmsr(msrnum, msr);<br>-}<br>-<br>-void<br>-chipsetinit(void)<br>-{<br>- device_t dev;<br>- struct southbridge_amd_cs5535_config *sb;<br>- msr_t msr;<br>- struct msrinit *csi;<br>- int i;<br>- unsigned long msrnum;<br>-<br>- dev = dev_find_device(PCI_VENDOR_ID_AMD,<br>- PCI_DEVICE_ID_NS_CS5535_ISA, 0);<br>-<br>- if (!dev) {<br>- printk(BIOS_ERR, "CS5535 not found.\n");<br>- return;<br>- }<br>-<br>- sb = (struct southbridge_amd_cs5535_config *)dev->chip_info;<br>-<br>- if (!sb) {<br>- printk(BIOS_ERR, "CS5535 configuration not found.\n");<br>- return;<br>- }<br>-<br>- post_code(P80_CHIPSET_INIT);<br>- ChipsetGeodeLinkInit();<br>-<br>-#ifdef UNUSED_CODE<br>- /* we hope NEVER to be in coreboot when S3 resumes<br>- if (! IsS3Resume()) */<br>- {<br>- struct acpiinit *aci = acpi_init_table;<br>- while (aci->ioreg){<br>- if (aci->iolen == 2) {<br>- outw(aci->regdata, aci->ioreg);<br>- inw(aci->ioreg);<br>- } else {<br>- outl(aci->regdata, aci->ioreg);<br>- inl(aci->ioreg);<br>- }<br>- }<br>-<br>- pmChipsetInit();<br>- }<br>-#endif<br>-<br>- /* Setup USB. Need more details. #118.18 */<br>- msrnum = MSR_SB_USB1 + 8;<br>- msr.lo = 0x00012090;<br>- msr.hi = 0;<br>- wrmsr(msrnum, msr);<br>- msrnum = MSR_SB_USB2 + 8;<br>- wrmsr(msrnum, msr);<br>-<br>- /* set hd IRQ */<br>- outl (GPIOL_2_SET, GPIOL_INPUT_ENABLE);<br>- outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT);<br>-<br>- /* Allow IO read and writes during a ATA DMA operation. */<br>- /* This could be done in the HD ROM but do it here for easier debugging. */<br>-<br>- msrnum = ATA_SB_GLD_MSR_ERR;<br>- msr = rdmsr(msrnum);<br>- msr.lo &= ~0x100;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Enable Post Primary IDE. */<br>- msrnum = GLPCI_SB_CTRL;<br>- msr = rdmsr(msrnum);<br>- msr.lo |= GLPCI_CRTL_PPIDE_SET;<br>- wrmsr(msrnum, msr);<br>-<br>- /* Set up Master Configuration Register */<br>- /* If 5536, use same master config settings as 5535, except for OHCI MSRs */<br>- i = 0;<br>-<br>- csi = &SB_MASTER_CONF_TABLE[i];<br>- for (; csi->msrnum; csi++){<br>- msr.lo = csi->msr.lo;<br>- msr.hi = csi->msr.hi;<br>- wrmsr(csi->msrnum, msr); // MSR - see table above<br>- }<br>-<br>- /* Flash Setup */<br>- printk(BIOS_INFO, "%sDOING ChipsetFlashSetup()!\n",<br>- sb->setupflash ? "" : "NOT ");<br>-<br>- if (sb->setupflash)<br>- ChipsetFlashSetup();<br>-<br>- /* Set up Hardware Clock Gating */<br>-<br>- /* if (getnvram(TOKEN_SB_CLK_GATE) != TVALUE_DISABLE) */<br>- {<br>- csi = CS5535_CLOCK_GATING_TABLE;<br>-<br>- for (; csi->msrnum; csi++){<br>- msr.lo = csi->msr.lo;<br>- msr.hi = csi->msr.hi;<br>- wrmsr(csi->msrnum, msr); // MSR - see table above<br>- }<br>- }<br>-}<br>diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c<br>deleted file mode 100644<br>index 2868683..0000000<br>--- a/src/southbridge/amd/cs5535/cs5535.c<br>+++ /dev/null<br>@@ -1,111 +0,0 @@<br>-<br>-#include <arch/io.h><br>-#include <arch/ioapic.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ops.h><br>-#include <device/pci_ids.h><br>-#include <console/console.h><br>-#include "cs5535.h"<br>-<br>-static void nvram_on(struct device *dev)<br>-{<br>-#if 0<br>- volatile char *flash = (volatile unsigned char *)0xFFFc0000;<br>- unsigned char id1, id2;<br>-#endif<br>- unsigned char reg;<br>-<br>- /* Enable writes to flash at top of memory */<br>- pci_write_config8(dev, 0x52, 0xee);<br>-<br>- /* Set positive decode on ROM */<br>- /* Also, there is no apparent reason to turn off the device on the */<br>- /* IDE devices */<br>-<br>- reg = pci_read_config8(dev, 0x5b);<br>- reg |= 1 << 5; /* ROM Decode */<br>- reg |= 1 << 3; /* Primary IDE decode */<br>- reg |= 1 << 4; /* Secondary IDE decode */<br>-<br>- pci_write_config8(dev, 0x5b, reg);<br>-<br>-#if 0 // just to test if the flash is accessible!<br>- *(flash + 0x555) = 0xaa;<br>- *(flash + 0x2aa) = 0x55;<br>- *(flash + 0x555) = 0x90;<br>-<br>- id1 = *(volatile unsigned char *) flash;<br>- id2 = *(volatile unsigned char *) (flash + 1);<br>-<br>- *flash = 0xf0;<br>-<br>- printk(BIOS_DEBUG, "Flash device: MFGID %02x, DEVID %02x\n", id1, id2);<br>-#endif<br>-}<br>-<br>-<br>-static void southbridge_init(struct device *dev)<br>-{<br>- printk(BIOS_SPEW, "cs5535: %s\n", __func__);<br>- nvram_on(dev);<br>-}<br>-<br>-/*<br>-static void dump_south(struct device *dev)<br>-{<br>- int i, j;<br>-<br>- for (i = 0; i < 256; i+=16) {<br>- printk(BIOS_DEBUG, "0x%02x: ", i);<br>- for (j = 0; j < 16; j++)<br>- printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j));<br>- printk(BIOS_DEBUG, "\n");<br>- }<br>-}<br>-*/<br>-<br>-static void southbridge_enable(struct device *dev)<br>-{<br>- printk(BIOS_SPEW, "%s: dev is %p\n", __func__, dev);<br>-}<br>-<br>-static void cs5535_read_resources(device_t dev)<br>-{<br>- struct resource *res;<br>-<br>- pci_dev_read_resources(dev);<br>-<br>- res = new_resource(dev, 1);<br>- res->base = 0x0UL;<br>- res->size = 0x1000UL;<br>- res->limit = 0xffffUL;<br>- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-<br>- res = new_resource(dev, 3); /* IOAPIC */<br>- res->base = IO_APIC_ADDR;<br>- res->size = 0x00001000;<br>- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-}<br>-<br>-static struct device_operations southbridge_ops = {<br>- .read_resources = cs5535_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = southbridge_init,<br>- .enable = southbridge_enable,<br>-};<br>-<br>-static const struct pci_driver cs5535_pci_driver __pci_driver = {<br>- .ops = &southbridge_ops,<br>- .vendor = PCI_VENDOR_ID_NS,<br>- .device = PCI_DEVICE_ID_NS_CS5535<br>-};<br>-<br>-struct chip_operations southbridge_amd_cs5535_ops = {<br>- CHIP_NAME("AMD Geode CS5535 Southbridge")<br>- /* This is only called when this device is listed in the<br>- * static device tree.<br>- */<br>- .enable_dev = southbridge_enable,<br>-};<br>diff --git a/src/southbridge/amd/cs5535/cs5535.h b/src/southbridge/amd/cs5535/cs5535.h<br>deleted file mode 100644<br>index 2bb9a6e..0000000<br>--- a/src/southbridge/amd/cs5535/cs5535.h<br>+++ /dev/null<br>@@ -1,121 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2010 Nils Jacobs<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef _CS5535_H<br>-#define _CS5535_H<br>-<br>-/* SouthBridge Equates */<br>-#define CS5535_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */<br>-#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */<br>-#define MSR_SB ((CS5535_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */<br>-#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */<br>-<br>-#define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */<br>-#define SMBUS_IO_BASE 0x6000<br>-#define GPIO_IO_BASE 0x6100<br>-#define MFGPT_IO_BASE 0x6200<br>-#define ACPI_IO_BASE 0x9C00<br>-#define PMS_IO_BASE 0x9D00<br>-<br>-/* Cs5536 as follows. */<br>-/* SB_GLIU */<br>-/* port0 - GLIU */<br>-/* port1 - GLPCI */<br>-/* port2 - USB Controller #2 */<br>-/* port3 - ATA-5 Controller */<br>-/* port4 - MDD */<br>-/* port5 - AC97 */<br>-/* port6 - USB Controller #1 */<br>-/* port7 - GLCP */<br>-<br>-#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */<br>-#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */<br>-#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */<br>-#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */<br>-#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */<br>-#define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */<br>-#define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */<br>-#define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */<br>-<br>-/* GLIU */<br>-#define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04)<br>-<br>-/* USB1 */<br>-#define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01)<br>-#define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04)<br>-<br>-/* USB2 */<br>-#define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01)<br>-#define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04)<br>-<br>-/* ATA */<br>-#define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01)<br>-#define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03)<br>-#define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04)<br>-#define ATA_SB_IDE_CFG (MSR_SB_ATA + 0x10)<br>-<br>-/* AC97 */<br>-#define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01)<br>-#define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04)<br>-<br>-/* GLPCI */<br>-#define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04)<br>-#define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10)<br>-#define GLPCI_CRTL_PPIDE_SET (1 << 17)<br>-<br>-/* GLCP */<br>-#define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04)<br>-<br>-/* MDD */<br>-#define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01)<br>-#define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04)<br>-#define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B)<br>-#define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C)<br>-#define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D)<br>-#define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E)<br>-#define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F)<br>-#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x10)<br>-#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x11)<br>-#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x12)<br>-#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x13)<br>-#define MDD_PIN_OPT (MSR_SB_MDD + 0x15)<br>-#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x18)<br>-<br>-/* GPIO */<br>-#define GPIOL_2_SET (1 << 2)<br>-<br>-/* GPIO LOW Bank Bit Registers */<br>-#define GPIOL_INPUT_ENABLE (0x20)<br>-#define GPIOL_IN_AUX1_SELECT (0x34)<br>-<br>-/* FLASH device macros */<br>-#define FLASH_TYPE_NONE 0 /* No flash device installed */<br>-#define FLASH_TYPE_NAND 1 /* NAND device */<br>-<br>-#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */<br>-<br>-/* Flash Memory Mask values */<br>-#define FLASH_MEM_4K 0xFFFFF000<br>-<br>-#if !defined(__ASSEMBLER__)<br>-#if defined(__PRE_RAM__)<br>-void cs5535_disable_internal_uart(void);<br>-#else<br>-void chipsetinit(void);<br>-#endif<br>-#endif<br>-<br>-#endif /* _CS5535_H */<br>diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c<br>deleted file mode 100644<br>index 1030aa0..0000000<br>--- a/src/southbridge/amd/cs5535/early_setup.c<br>+++ /dev/null<br>@@ -1,145 +0,0 @@<br>-/*<br>- *<br>- * cs5535_early_setup.c: Early chipset initialization for CS5535 companion device<br>- *<br>- *<br>- * This file implements the initialization sequence documented in section 4.2 of<br>- * AMD Geode GX Processor CS5535 Companion Device GoedeROM Porting Guide.<br>- *<br>- */<br>-<br>-/**<br>- * @brief Setup PCI IDSEL for CS5535<br>- *<br>- *<br>- */<br>-<br>-static void cs5535_setup_extmsr(void)<br>-{<br>- msr_t msr;<br>-<br>- /* forward MSR access to CS5535_GLINK_PORT_NUM to CS5535_DEV_NUM */<br>- msr.hi = msr.lo = 0x00000000;<br>-#if CS5535_GLINK_PORT_NUM <= 4<br>- msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8);<br>-#else<br>- msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8);<br>-#endif<br>- wrmsr(0x5000201e, msr);<br>-}<br>-<br>-static void cs5535_setup_idsel(void)<br>-{<br>- /* write IDSEL to the write once register at address 0x0000 */<br>- outl(0x1 << (CS5535_DEV_NUM + 10), 0);<br>-}<br>-<br>-static void cs5535_usb_swapsif(void)<br>-{<br>- msr_t msr;<br>-<br>- msr = rdmsr(0x51600005);<br>- //USB Serial short detect bit.<br>- if (msr.hi & 0x10) {<br>- /* We need to preserve bits 32,33,35 and not clear any BIST error, but clear the<br>- * SERSHRT error bit */<br>- msr.hi &= 0xFFFFFFFB;<br>- wrmsr(0x51600005, msr);<br>- }<br>-}<br>-<br>-static void cs5535_setup_iobase(void)<br>-{<br>- msr_t msr;<br>- /* setup LBAR for SMBus controller */<br>- msr.hi = 0x0000f001;<br>- msr.lo = SMBUS_IO_BASE;<br>- wrmsr(MDD_LBAR_SMB, msr);<br>-<br>- /* setup LBAR for GPIO */<br>- msr.hi = 0x0000f001;<br>- msr.lo = GPIO_IO_BASE;<br>- wrmsr(MDD_LBAR_GPIO, msr);<br>-<br>- /* setup LBAR for MFGPT */<br>- msr.hi = 0x0000f001;<br>- msr.lo = MFGPT_IO_BASE;<br>- wrmsr(MDD_LBAR_MFGPT, msr);<br>-<br>- /* setup LBAR for ACPI */<br>- msr.hi = 0x0000f001;<br>- msr.lo = ACPI_IO_BASE;<br>- wrmsr(MDD_LBAR_ACPI, msr);<br>-<br>- /* setup LBAR for PM Support */<br>- msr.hi = 0x0000f001;<br>- msr.lo = PMS_IO_BASE;<br>- wrmsr(MDD_LBAR_PMS, msr);<br>-}<br>-<br>-static void cs5535_setup_gpio(void)<br>-{<br>- uint32_t val;<br>-<br>- /* setup GPIO pins 14/15 for SDA/SCL */<br>- val = (1<<14 | 1<<15);<br>- /* Output Enable */<br>- outl(0x3fffc000, 0x6100 + 0x04);<br>- //outl(val, 0x6100 + 0x04);<br>- /* Output AUX1 */<br>- outl(0x3fffc000, 0x6100 + 0x10);<br>- //outl(val, 0x6100 + 0x10);<br>- /* Input Enable */<br>- //outl(0x0f5af0a5, 0x6100 + 0x20);<br>- outl(0x3fffc000, 0x6100 + 0x20);<br>- //outl(val, 0x6100 + 0x20);<br>- /* Input AUX1 */<br>- //outl(0x3ffbc004, 0x6100 + 0x34);<br>- outl(0x3fffc000, 0x6100 + 0x34);<br>- //outl(val, 0x6100 + 0x34);<br>-}<br>-<br>-void cs5535_disable_internal_uart(void)<br>-{<br>-}<br>-<br>-static void cs5535_setup_cis_mode(void)<br>-{<br>- msr_t msr;<br>-<br>- /* Setup CPU serial SouthBridge interface to mode C. */<br>- msr = rdmsr(GLPCI_SB_CTRL);<br>- msr.lo &= ~0x18;<br>- msr.lo |= 0x10;<br>- wrmsr(GLPCI_SB_CTRL, msr);<br>-}<br>-<br>-static void dummy(void)<br>-{<br>-}<br>-<br>-static void cs5535_early_setup(void)<br>-{<br>- msr_t msr;<br>-<br>- cs5535_setup_extmsr();<br>-<br>- msr = rdmsr(GLCP_SYS_RSTPLL);<br>- if (msr.lo & (0x3f << 26)) {<br>- /* PLL is already set and we are reboot from PLL reset */<br>- printk(BIOS_DEBUG, "reboot from BIOS reset\n");<br>- return;<br>- }<br>- printk(BIOS_DEBUG, "Setup idsel\n");<br>- cs5535_setup_idsel();<br>- printk(BIOS_DEBUG, "Setup iobase\n");<br>- cs5535_usb_swapsif();<br>- cs5535_setup_iobase();<br>- printk(BIOS_DEBUG, "Setup gpio\n");<br>- cs5535_setup_gpio();<br>- printk(BIOS_DEBUG, "Setup cis_mode\n");<br>- cs5535_setup_cis_mode();<br>- printk(BIOS_DEBUG, "Setup smbus\n");<br>- cs5535_enable_smbus();<br>- dummy();<br>-}<br>diff --git a/src/southbridge/amd/cs5535/early_smbus.c b/src/southbridge/amd/cs5535/early_smbus.c<br>deleted file mode 100644<br>index 25b6951..0000000<br>--- a/src/southbridge/amd/cs5535/early_smbus.c<br>+++ /dev/null<br>@@ -1,22 +0,0 @@<br>-#include "smbus.h"<br>-<br>-#define SMBUS_IO_BASE 0x6000<br>-<br>-/* initialization for SMBus Controller */<br>-static void cs5535_enable_smbus(void)<br>-{<br>- unsigned char val;<br>-<br>- /* reset SMBUS controller */<br>- outb(0, SMBUS_IO_BASE + SMB_CTRL2);<br>-<br>- /* Set SCL freq and enable SMB controller */<br>- val = inb(SMBUS_IO_BASE + SMB_CTRL2);<br>- val |= ((0x20 << 1) | SMB_CTRL2_ENABLE);<br>- outb(val, SMBUS_IO_BASE + SMB_CTRL2);<br>-<br>- /* Setup SMBus host controller address to 0xEF */<br>- val = inb(SMBUS_IO_BASE + SMB_ADD);<br>- val |= (0xEF | SMB_ADD_SAEN);<br>- outb(val, SMBUS_IO_BASE + SMB_ADD);<br>-}<br>diff --git a/src/southbridge/amd/cs5535/ide.c b/src/southbridge/amd/cs5535/ide.c<br>deleted file mode 100644<br>index b997ca2..0000000<br>--- a/src/southbridge/amd/cs5535/ide.c<br>+++ /dev/null<br>@@ -1,30 +0,0 @@<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include "cs5535.h"<br>-<br>-static void ide_init(struct device *dev)<br>-{<br>- printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__);<br>-}<br>-<br>-static void ide_enable(struct device *dev)<br>-{<br>- printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__);<br>-}<br>-<br>-static struct device_operations ide_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = ide_init,<br>- .enable = ide_enable,<br>-};<br>-<br>-static const struct pci_driver ide_driver __pci_driver = {<br>- .ops = &ide_ops,<br>- .vendor = PCI_VENDOR_ID_NS,<br>- .device = PCI_DEVICE_ID_NS_CS5535_IDE,<br>-};<br>diff --git a/src/southbridge/amd/cs5535/smbus.h b/src/southbridge/amd/cs5535/smbus.h<br>deleted file mode 100644<br>index db35f6e..0000000<br>--- a/src/southbridge/amd/cs5535/smbus.h<br>+++ /dev/null<br>@@ -1,46 +0,0 @@<br>-//#include <device/smbus_def.h><br>-#define SMBUS_ERROR -1<br>-#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2<br>-#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3<br>-<br>-#define SMB_SDA 0x00<br>-#define SMB_STS 0x01<br>-#define SMB_CTRL_STS 0x02<br>-#define SMB_CTRL1 0x03<br>-#define SMB_ADD 0x04<br>-#define SMB_CTRL2 0x05<br>-#define SMB_CTRL3 0x06<br>-<br>-#define SMB_STS_SLVSTP (0x01 << 7)<br>-#define SMB_STS_SDAST (0x01 << 6)<br>-#define SMB_STS_BER (0x01 << 5)<br>-#define SMB_STS_NEGACK (0x01 << 4)<br>-#define SMB_STS_STASTR (0x01 << 3)<br>-#define SMB_STS_NMATCH (0x01 << 2)<br>-#define SMB_STS_MASTER (0x01 << 1)<br>-#define SMB_STS_XMIT (0x01 << 0)<br>-<br>-#define SMB_CSTS_TGSCL (0x01 << 5)<br>-#define SMB_CSTS_TSDA (0x01 << 4)<br>-#define SMB_CSTS_GCMTCH (0x01 << 3)<br>-#define SMB_CSTS_MATCH (0x01 << 2)<br>-#define SMB_CSTS_BB (0x01 << 1)<br>-#define SMB_CSTS_BUSY (0x01 << 0)<br>-<br>-#define SMB_CTRL1_STASTRE (0x01 << 7)<br>-#define SMB_CTRL1_NMINTE (0x01 << 6)<br>-#define SMB_CTRL1_GCMEN (0x01 << 5)<br>-#define SMB_CTRL1_ACK (0x01 << 4)<br>-#define SMB_CTRL1_RSVD (0x01 << 3)<br>-#define SMB_CTRL1_INTEN (0x01 << 2)<br>-#define SMB_CTRL1_STOP (0x01 << 1)<br>-#define SMB_CTRL1_START (0x01 << 0)<br>-<br>-#define SMB_ADD_SAEN (0x01 << 7)<br>-<br>-#define SMB_CTRL2_ENABLE 0x01<br>-<br>-#define SMBUS_TIMEOUT (100*1000*10)<br>-#define SMBUS_STATUS_MASK 0xfbff<br>-<br>-#define SMBUS_IO_BASE 0x6000<br></pre><p>To view, visit <a href="https://review.coreboot.org/22025">change 22025</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22025"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c </div>
<div style="display:none"> Gerrit-Change-Number: 22025 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>