<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22031">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT<br><br>All boards and chips that are still using LATE_CBMEM_INIT are being<br>removed as previously discussed.<br><br>If these boards and chips are updated to not use LATE_CBMEM_INIT, they<br>can be restored to the active codebase from the 4.8 branch.<br><br>chips:<br>northbridge/intel/i3100<br>southbridge/intel/i3100<br>superio/intel/i3100<br>cpu/intel/socket_mPGA479M<br>cpu/intel/socket_mPGA479M<br><br>Mainboards:<br>mainboard/intel/truxton<br>mainboard/intel/mtarvon<br>mainboard/intel/truxton<br><br>Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb<br>Signed-off-by: Martin Roth <gaumless@gmail.com><br>---<br>M src/cpu/intel/Makefile.inc<br>D src/cpu/intel/ep80579/Kconfig<br>D src/cpu/intel/ep80579/Makefile.inc<br>D src/cpu/intel/ep80579/ep80579.c<br>D src/cpu/intel/ep80579/ep80579_init.c<br>D src/cpu/intel/socket_mPGA479M/Kconfig<br>D src/cpu/intel/socket_mPGA479M/Makefile.inc<br>D src/mainboard/intel/eagleheights/Kconfig<br>D src/mainboard/intel/eagleheights/Kconfig.name<br>D src/mainboard/intel/eagleheights/Makefile.inc<br>D src/mainboard/intel/eagleheights/acpi_tables.c<br>D src/mainboard/intel/eagleheights/board_info.txt<br>D src/mainboard/intel/eagleheights/cmos.layout<br>D src/mainboard/intel/eagleheights/cstates.c<br>D src/mainboard/intel/eagleheights/debug.c<br>D src/mainboard/intel/eagleheights/devicetree.cb<br>D src/mainboard/intel/eagleheights/dsdt.asl<br>D src/mainboard/intel/eagleheights/fadt.c<br>D src/mainboard/intel/eagleheights/ioapic.h<br>D src/mainboard/intel/eagleheights/irq_tables.c<br>D src/mainboard/intel/eagleheights/mptable.c<br>D src/mainboard/intel/eagleheights/romstage.c<br>D src/mainboard/intel/mtarvon/Kconfig<br>D src/mainboard/intel/mtarvon/Kconfig.name<br>D src/mainboard/intel/mtarvon/board_info.txt<br>D src/mainboard/intel/mtarvon/devicetree.cb<br>D src/mainboard/intel/mtarvon/irq_tables.c<br>D src/mainboard/intel/mtarvon/mptable.c<br>D src/mainboard/intel/mtarvon/romstage.c<br>D src/mainboard/intel/truxton/Kconfig<br>D src/mainboard/intel/truxton/Kconfig.name<br>D src/mainboard/intel/truxton/Makefile.inc<br>D src/mainboard/intel/truxton/board_info.txt<br>D src/mainboard/intel/truxton/devicetree.cb<br>D src/mainboard/intel/truxton/irq_tables.c<br>D src/mainboard/intel/truxton/mptable.c<br>D src/mainboard/intel/truxton/romstage.c<br>D src/northbridge/intel/i3100/Kconfig<br>D src/northbridge/intel/i3100/Makefile.inc<br>D src/northbridge/intel/i3100/chip.h<br>D src/northbridge/intel/i3100/ep80579.h<br>D src/northbridge/intel/i3100/i3100.h<br>D src/northbridge/intel/i3100/memory_initialized.c<br>D src/northbridge/intel/i3100/northbridge.c<br>D src/northbridge/intel/i3100/pciexp_porta.c<br>D src/northbridge/intel/i3100/pciexp_porta_ep80579.c<br>D src/northbridge/intel/i3100/raminit.c<br>D src/northbridge/intel/i3100/raminit.h<br>D src/northbridge/intel/i3100/raminit_ep80579.c<br>D src/northbridge/intel/i3100/raminit_ep80579.h<br>D src/northbridge/intel/i3100/reset_test.c<br>D src/southbridge/intel/i3100/Kconfig<br>D src/southbridge/intel/i3100/Makefile.inc<br>D src/southbridge/intel/i3100/chip.h<br>D src/southbridge/intel/i3100/early_lpc.c<br>D src/southbridge/intel/i3100/early_smbus.c<br>D src/southbridge/intel/i3100/ehci.c<br>D src/southbridge/intel/i3100/i3100.c<br>D src/southbridge/intel/i3100/i3100.h<br>D src/southbridge/intel/i3100/ioapic.c<br>D src/southbridge/intel/i3100/lpc.c<br>D src/southbridge/intel/i3100/pci.c<br>D src/southbridge/intel/i3100/pciexp_portb.c<br>D src/southbridge/intel/i3100/reset.c<br>D src/southbridge/intel/i3100/sata.c<br>D src/southbridge/intel/i3100/smbus.c<br>D src/southbridge/intel/i3100/uhci.c<br>D src/superio/intel/i3100/Kconfig<br>D src/superio/intel/i3100/Makefile.inc<br>D src/superio/intel/i3100/early_serial.c<br>D src/superio/intel/i3100/i3100.h<br>D src/superio/intel/i3100/superio.c<br>72 files changed, 0 insertions(+), 7,119 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/22031/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc<br>index 3c94a71..37fac8e 100644<br>--- a/src/cpu/intel/Makefile.inc<br>+++ b/src/cpu/intel/Makefile.inc<br>@@ -7,14 +7,12 @@<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284<br>-subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN<br>-subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B<br>diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig<br>deleted file mode 100644<br>index dc19ae1..0000000<br>--- a/src/cpu/intel/ep80579/Kconfig<br>+++ /dev/null<br>@@ -1,23 +0,0 @@<br>-config CPU_INTEL_EP80579<br>- bool<br>- select ARCH_BOOTBLOCK_X86_32<br>- select ARCH_VERSTAGE_X86_32<br>- select ARCH_ROMSTAGE_X86_32<br>- select ARCH_RAMSTAGE_X86_32<br>- select SSE<br>- select SUPPORT_CPU_UCODE_IN_CBFS<br>-<br>-if CPU_INTEL_EP80579<br>-<br>-# These are just dummy values to keep build happy.<br>-# This CPU does not have tested cache_as_ram.inc.<br>-<br>-config DCACHE_RAM_BASE<br>- hex<br>- default 0xfefc0000<br>-<br>-config DCACHE_RAM_SIZE<br>- hex<br>- default 0x8000<br>-<br>-endif<br>diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc<br>deleted file mode 100644<br>index 1af9188..0000000<br>--- a/src/cpu/intel/ep80579/Makefile.inc<br>+++ /dev/null<br>@@ -1,8 +0,0 @@<br>-ramstage-y += ep80579.c<br>-ramstage-y += ep80579_init.c<br>-subdirs-y += ../../x86/tsc<br>-subdirs-y += ../../x86/mtrr<br>-subdirs-y += ../../x86/lapic<br>-subdirs-y += ../../x86/cache<br>-subdirs-y += ../../x86/smm<br>-subdirs-y += ../microcode<br>diff --git a/src/cpu/intel/ep80579/ep80579.c b/src/cpu/intel/ep80579/ep80579.c<br>deleted file mode 100644<br>index 044cb4f..0000000<br>--- a/src/cpu/intel/ep80579/ep80579.c<br>+++ /dev/null<br>@@ -1,20 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <device/device.h><br>-<br>-struct chip_operations cpu_intel_ep80579_ops = {<br>- CHIP_NAME("EP80579 CPU")<br>-};<br>diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c<br>deleted file mode 100644<br>index 78860b4..0000000<br>--- a/src/cpu/intel/ep80579/ep80579_init.c<br>+++ /dev/null<br>@@ -1,53 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <string.h><br>-#include <cpu/cpu.h><br>-#include <cpu/x86/mtrr.h><br>-#include <cpu/x86/msr.h><br>-#include <cpu/x86/lapic.h><br>-#include <cpu/intel/microcode.h><br>-#include <cpu/x86/cache.h><br>-#include <cpu/x86/mtrr.h><br>-<br>-static void ep80579_init(struct device *dev)<br>-{<br>- /* Turn on caching if we haven't already */<br>- x86_enable_cache();<br>- x86_setup_mtrrs();<br>- x86_mtrr_check();<br>-<br>- /* Update the microcode */<br>- intel_update_microcode_from_cbfs();<br>-<br>- /* Enable the local CPU APICs */<br>- setup_lapic();<br>-};<br>-<br>-static struct device_operations cpu_dev_ops = {<br>- .init = ep80579_init,<br>-};<br>-<br>-static struct cpu_device_id cpu_table[] = {<br>- { X86_VENDOR_INTEL, 0x10650 }, /* EP80579 */<br>- { 0, 0 },<br>-};<br>-<br>-static const struct cpu_driver driver __cpu_driver = {<br>- .ops = &cpu_dev_ops,<br>- .id_table = cpu_table,<br>-};<br>diff --git a/src/cpu/intel/socket_mPGA479M/Kconfig b/src/cpu/intel/socket_mPGA479M/Kconfig<br>deleted file mode 100644<br>index ba6f7ea..0000000<br>--- a/src/cpu/intel/socket_mPGA479M/Kconfig<br>+++ /dev/null<br>@@ -1,20 +0,0 @@<br>-config CPU_INTEL_SOCKET_MPGA479M<br>- bool<br>- select CPU_INTEL_MODEL_69X<br>- select CPU_INTEL_MODEL_6BX<br>- select CPU_INTEL_MODEL_6DX<br>- select CPU_INTEL_MODEL_F2X<br>- select MMX<br>- select SSE<br>-<br>-if CPU_INTEL_SOCKET_MPGA479M<br>-<br>-config DCACHE_RAM_BASE<br>- hex<br>- default 0xc8000<br>-<br>-config DCACHE_RAM_SIZE<br>- hex<br>- default 0x08000<br>-<br>-endif<br>diff --git a/src/cpu/intel/socket_mPGA479M/Makefile.inc b/src/cpu/intel/socket_mPGA479M/Makefile.inc<br>deleted file mode 100644<br>index c35ca46..0000000<br>--- a/src/cpu/intel/socket_mPGA479M/Makefile.inc<br>+++ /dev/null<br>@@ -1,13 +0,0 @@<br>-subdirs-y += ../model_69x<br>-subdirs-y += ../model_6dx<br>-subdirs-y += ../model_f2x<br>-subdirs-y += ../../x86/tsc<br>-subdirs-y += ../../x86/mtrr<br>-subdirs-y += ../../x86/lapic<br>-subdirs-y += ../../x86/cache<br>-subdirs-y += ../../x86/smm<br>-subdirs-y += ../microcode<br>-subdirs-y += ../hyperthreading<br>-<br>-cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc<br>-romstage-y += ../car/romstage_legacy.c<br>diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig<br>deleted file mode 100644<br>index 9671fff..0000000<br>--- a/src/mainboard/intel/eagleheights/Kconfig<br>+++ /dev/null<br>@@ -1,37 +0,0 @@<br>-if BOARD_INTEL_EAGLEHEIGHTS<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_INTEL_SOCKET_BGA956<br>- select NORTHBRIDGE_INTEL_I3100<br>- select SOUTHBRIDGE_INTEL_I3100<br>- select SUPERIO_INTEL_I3100<br>- select SUPERIO_SMSC_SMSCSUPERIO<br>- select HAVE_OPTION_TABLE<br>- select HAVE_HARD_RESET<br>- select HAVE_PIRQ_TABLE<br>- select HAVE_MP_TABLE<br>- select HAVE_ACPI_TABLES<br>- select BOARD_ROMSIZE_KB_1024<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default intel/eagleheights<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "EagleHeights"<br>-<br>-config MMCONF_BASE_ADDRESS<br>- hex<br>- default 0xe0000000<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 9<br>-<br>-config MAX_CPUS<br>- int<br>- default 4<br>-<br>-endif # BOARD_INTEL_EAGLEHEIGHTS<br>diff --git a/src/mainboard/intel/eagleheights/Kconfig.name b/src/mainboard/intel/eagleheights/Kconfig.name<br>deleted file mode 100644<br>index 95be5cb..0000000<br>--- a/src/mainboard/intel/eagleheights/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_INTEL_EAGLEHEIGHTS<br>- bool "EagleHeights"<br>diff --git a/src/mainboard/intel/eagleheights/Makefile.inc b/src/mainboard/intel/eagleheights/Makefile.inc<br>deleted file mode 100644<br>index f9621db..0000000<br>--- a/src/mainboard/intel/eagleheights/Makefile.inc<br>+++ /dev/null<br>@@ -1 +0,0 @@<br>-ramstage-y += cstates.c<br>diff --git a/src/mainboard/intel/eagleheights/acpi_tables.c b/src/mainboard/intel/eagleheights/acpi_tables.c<br>deleted file mode 100644<br>index cd914da..0000000<br>--- a/src/mainboard/intel/eagleheights/acpi_tables.c<br>+++ /dev/null<br>@@ -1,64 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2008 coresystems GmbH<br>- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <string.h><br>-#include <console/console.h><br>-#include <arch/acpi.h><br>-#include <arch/ioapic.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include "ioapic.h"<br>-<br>-#define IO_APIC0 2<br>-#define IO_APIC1 3<br>-<br>-unsigned long acpi_fill_madt(unsigned long current)<br>-{<br>- unsigned int irq_start = 0;<br>- device_t dev = 0;<br>- unsigned char bus_isa;<br>-<br>- /* Local Apic */<br>- current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 1, 0);<br>- // This one is for the second core... Will it hurt?<br>- current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 2, 1);<br>-<br>- /* IOAPIC */<br>- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC0, IO_APIC_ADDR, irq_start);<br>- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;<br>- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC1, IO_APIC_ADDR + 0x10000, irq_start);<br>- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;<br>-<br>- dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));<br>-<br>- if (dev) {<br>- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);<br>- bus_isa++;<br>- } else {<br>- printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");<br>- bus_isa = 7;<br>- }<br>-<br>- /* Map ISA IRQ 0 to IRQ 2 */<br>- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, bus_isa, 0, 2, 0);<br>-<br>- /* IRQ9 differs from ISA standard - ours is active high, level-triggered */<br>- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000d);<br>-<br>- return current;<br>-}<br>diff --git a/src/mainboard/intel/eagleheights/board_info.txt b/src/mainboard/intel/eagleheights/board_info.txt<br>deleted file mode 100644<br>index b351b8e..0000000<br>--- a/src/mainboard/intel/eagleheights/board_info.txt<br>+++ /dev/null<br>@@ -1 +0,0 @@<br>-Category: eval<br>diff --git a/src/mainboard/intel/eagleheights/cmos.layout b/src/mainboard/intel/eagleheights/cmos.layout<br>deleted file mode 100644<br>index eace7e7..0000000<br>--- a/src/mainboard/intel/eagleheights/cmos.layout<br>+++ /dev/null<br>@@ -1,96 +0,0 @@<br>-#<br>-# This file is part of the coreboot project.<br>-#<br>-# Copyright (C) 2007-2008 coresystems GmbH<br>-#<br>-# This program is free software; you can redistribute it and/or<br>-# modify it under the terms of the GNU General Public License as<br>-# published by the Free Software Foundation; version 2 of<br>-# the License.<br>-#<br>-# This program is distributed in the hope that it will be useful,<br>-# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-# GNU General Public License for more details.<br>-#<br>-<br>-# -----------------------------------------------------------------<br>-entries<br>-<br>-# -----------------------------------------------------------------<br>-# Status Register A<br>-# -----------------------------------------------------------------<br>-# Status Register B<br>-# -----------------------------------------------------------------<br>-# Status Register C<br>-#96 4 r 0 status_c_rsvd<br>-#100 1 r 0 uf_flag<br>-#101 1 r 0 af_flag<br>-#102 1 r 0 pf_flag<br>-#103 1 r 0 irqf_flag<br>-# -----------------------------------------------------------------<br>-# Status Register D<br>-#104 7 r 0 status_d_rsvd<br>-#111 1 r 0 valid_cmos_ram<br>-# -----------------------------------------------------------------<br>-# Diagnostic Status Register<br>-#112 8 r 0 diag_rsvd1<br>-<br>-# -----------------------------------------------------------------<br>-0 120 r 0 reserved_memory<br>-#120 264 r 0 unused<br>-<br>-# -----------------------------------------------------------------<br>-# RTC_BOOT_BYTE (coreboot hardcoded)<br>-384 1 e 4 boot_option<br>-388 4 h 0 reboot_counter<br>-#390 2 r 0 unused?<br>-<br>-# -----------------------------------------------------------------<br>-# coreboot config options: console<br>-#392 3 r 0 unused<br>-395 4 e 6 debug_level<br>-#399 1 r 0 unused<br>-<br>-# coreboot config options: cpu<br>-400 1 e 2 hyper_threading<br>-#401 7 r 0 unused<br>-<br>-# coreboot config options: southbridge<br>-408 1 e 1 nmi<br>-409 1 e 1 power_on_after_fail<br>-#410 6 r 0 unused<br>-<br>-# coreboot config options: bootloader<br>-416 512 s 0 boot_devices<br>-#928 80 r 0 unused<br>-<br>-# coreboot config options: check sums<br>-984 16 h 0 check_sum<br>-#1000 24 r 0 amd_reserved<br>-<br>-# -----------------------------------------------------------------<br>-<br>-enumerations<br>-<br>-#ID value text<br>-1 0 Disable<br>-1 1 Enable<br>-2 0 Enable<br>-2 1 Disable<br>-4 0 Fallback<br>-4 1 Normal<br>-6 1 Emergency<br>-6 2 Alert<br>-6 3 Critical<br>-6 4 Error<br>-6 5 Warning<br>-6 6 Notice<br>-6 7 Info<br>-6 8 Debug<br>-6 9 Spew<br>-<br>-# -----------------------------------------------------------------<br>-checksums<br>-<br>-checksum 392 983 984<br>diff --git a/src/mainboard/intel/eagleheights/cstates.c b/src/mainboard/intel/eagleheights/cstates.c<br>deleted file mode 100644<br>index f683756..0000000<br>--- a/src/mainboard/intel/eagleheights/cstates.c<br>+++ /dev/null<br>@@ -1,20 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <device/device.h><br>-#include <arch/x86/include/arch/acpigen.h><br>-<br>-int get_cst_entries(acpi_cstate_t **entries)<br>-{<br>- return 0;<br>-}<br>diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c<br>deleted file mode 100644<br>index dd97837..0000000<br>--- a/src/mainboard/intel/eagleheights/debug.c<br>+++ /dev/null<br>@@ -1,188 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2008 coresystems GmbH<br>- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <spd.h><br>-<br>-static void print_reg(unsigned char index)<br>-{<br>- unsigned char data;<br>-<br>- outb(index, 0x2e);<br>- data = inb(0x2f);<br>- printk(BIOS_DEBUG, "0x%02x: 0x%02x\n", index, data);<br>- return;<br>-}<br>-<br>-static inline void xbus_en(void)<br>-{<br>- /* select the XBUS function in the SIO */<br>- outb(0x07, 0x2e);<br>- outb(0x0f, 0x2f);<br>- outb(0x30, 0x2e);<br>- outb(0x01, 0x2f);<br>- return;<br>-}<br>-<br>-static void setup_func(unsigned char func)<br>-{<br>- /* select the function in the SIO */<br>- outb(0x07, 0x2e);<br>- outb(func, 0x2f);<br>- /* print out the regs */<br>- print_reg(0x30);<br>- print_reg(0x60);<br>- print_reg(0x61);<br>- print_reg(0x62);<br>- print_reg(0x63);<br>- print_reg(0x70);<br>- print_reg(0x71);<br>- print_reg(0x74);<br>- print_reg(0x75);<br>- return;<br>-}<br>-<br>-static inline void siodump(void)<br>-{<br>- int i;<br>- unsigned char data;<br>-<br>- printk(BIOS_DEBUG, "\n*** SERVER I/O REGISTERS ***\n");<br>- for (i = 0x10; i <= 0x2d; i++) {<br>- print_reg((unsigned char)i);<br>- }<br>-#if 0<br>- printk(BIOS_DEBUG, "\n*** XBUS REGISTERS ***\n");<br>- setup_func(0x0f);<br>- for (i = 0xf0; i <= 0xff; i++) {<br>- print_reg((unsigned char)i);<br>- }<br>-<br>- printk(BIOS_DEBUG, "\n*** SERIAL 1 CONFIG REGISTERS ***\n");<br>- setup_func(0x03);<br>- print_reg(0xf0);<br>-<br>- printk(BIOS_DEBUG, "\n*** SERIAL 2 CONFIG REGISTERS ***\n");<br>- setup_func(0x02);<br>- print_reg(0xf0);<br>-<br>-#endif<br>- printk(BIOS_DEBUG, "\n*** GPIO REGISTERS ***\n");<br>- setup_func(0x07);<br>- for (i = 0xf0; i <= 0xf8; i++) {<br>- print_reg((unsigned char)i);<br>- }<br>- printk(BIOS_DEBUG, "\n*** GPIO VALUES ***\n");<br>- data = inb(0x68a);<br>- printk(BIOS_DEBUG, "\nGPDO 4: 0x%02x", data);<br>- data = inb(0x68b);<br>- printk(BIOS_DEBUG, "\nGPDI 4: 0x%02x\n", data);<br>-<br>-#if 0<br>-<br>- printk(BIOS_DEBUG, "\n*** WATCHDOG TIMER REGISTERS ***\n");<br>- setup_func(0x0a);<br>- print_reg(0xf0);<br>-<br>- printk(BIOS_DEBUG, "\n*** FAN CONTROL REGISTERS ***\n");<br>- setup_func(0x09);<br>- print_reg(0xf0);<br>- print_reg(0xf1);<br>-<br>- printk(BIOS_DEBUG, "\n*** RTC REGISTERS ***\n");<br>- setup_func(0x10);<br>- print_reg(0xf0);<br>- print_reg(0xf1);<br>- print_reg(0xf3);<br>- print_reg(0xf6);<br>- print_reg(0xf7);<br>- print_reg(0xfe);<br>- print_reg(0xff);<br>-<br>- printk(BIOS_DEBUG, "\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");<br>- setup_func(0x14);<br>- print_reg(0xf0);<br>-#endif<br>- return;<br>-}<br>-<br>-static inline void dump_bar14(unsigned dev)<br>-{<br>- int i;<br>- unsigned long bar;<br>-<br>- printk(BIOS_DEBUG, "BAR 14 Dump\n");<br>-<br>- bar = pci_read_config32(dev, 0x14);<br>- for(i = 0; i <= 0x300; i+=4) {<br>-#if 0<br>- unsigned char val;<br>- if ((i & 0x0f) == 0)<br>- printk(BIOS_DEBUG, "%02x:", i);<br>- val = pci_read_config8(dev, i);<br>-#endif<br>- if((i%4)==0)<br>- printk(BIOS_DEBUG, "\n%04x ", i);<br>- printk(BIOS_DEBUG, "%08x ", read32(bar + i));<br>- }<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-static inline void dump_spd_registers(void)<br>-{<br>- unsigned device;<br>- device = DIMM0;<br>- while(device <= DIMM7) {<br>- int status = 0;<br>- int i;<br>- printk(BIOS_DEBUG, "\ndimm %02x", device);<br>-<br>- for(i = 0; (i < 256); i++) {<br>- if ((i % 16) == 0)<br>- printk(BIOS_DEBUG, "\n%02x: ", i);<br>- status = smbus_read_byte(device, i);<br>- if (status < 0) {<br>- printk(BIOS_DEBUG, "bad device: %d\n", -status);<br>- break;<br>- }<br>- printk(BIOS_DEBUG, "%02x ", status);<br>- }<br>- device++;<br>- printk(BIOS_DEBUG, "\n");<br>- }<br>-}<br>-<br>-static inline void dump_ipmi_registers(void)<br>-{<br>- unsigned device;<br>- device = 0x42;<br>- while(device <= 0x42) {<br>- int status = 0;<br>- int i;<br>- printk(BIOS_DEBUG, "\nipmi %02x", device);<br>-<br>- for(i = 0; (i < 8); i++) {<br>- status = smbus_read_byte(device, 2);<br>- if (status < 0) {<br>- printk(BIOS_DEBUG, "bad device: %d\n", -status);<br>- break;<br>- }<br>- printk(BIOS_DEBUG, "%02x ", status);<br>- }<br>- device++;<br>- printk(BIOS_DEBUG, "\n");<br>- }<br>-}<br>diff --git a/src/mainboard/intel/eagleheights/devicetree.cb b/src/mainboard/intel/eagleheights/devicetree.cb<br>deleted file mode 100644<br>index 8d1549a..0000000<br>--- a/src/mainboard/intel/eagleheights/devicetree.cb<br>+++ /dev/null<br>@@ -1,72 +0,0 @@<br>-chip northbridge/intel/i3100<br>- device domain 0 on<br>- device pci 00.0 on end # IMCH<br>- device pci 00.1 on end # IMCH error status<br>- device pci 01.0 on end # IMCH EDMA engine<br>- device pci 02.0 on end # PCIe port A/A0<br>- device pci 03.0 on end # PCIe port A1<br>- chip southbridge/intel/i3100<br>- # PIRQ line -> legacy IRQ mappings<br>- register "pirq_a_d" = "0x8b808a8a"<br>- register "pirq_e_h" = "0x85808080"<br>-<br>- device pci 1c.0 on end # PCIe port B0<br>- device pci 1c.1 off end # PCIe port B1<br>- device pci 1c.2 off end # PCIe port B2<br>- device pci 1c.3 off end # PCIe port B3<br>- device pci 1d.0 on end # USB (UHCI) 1<br>- device pci 1d.1 on end # USB (UHCI) 2<br>- device pci 1d.7 on end # USB (EHCI)<br>- device pci 1e.0 on end # PCI bridge<br>- device pci 1f.0 on # LPC bridge<br>- chip superio/intel/i3100<br>- device pnp 4e.4 on # Com1<br>- io 0x60 = 0x3f8<br>- irq 0x70 = 4<br>- end<br>- device pnp 4e.5 on # Com2<br>- io 0x60 = 0x2f8<br>- irq 0x70 = 3<br>- end<br>- end<br>- chip superio/smsc/smscsuperio<br>- device pnp 2e.0 off # Floppy<br>- io 0x60 = 0x3f0<br>- irq 0x70 = 6<br>- drq 0x74 = 2<br>- end<br>- device pnp 2e.2 off # Serial Port 4<br>- io 0x60 = 0x2e8<br>- irq 0x70 = 3<br>- end<br>- device pnp 2e.3 on # Parallel Port<br>- io 0x60 = 0x378<br>- irq 0x70 = 7<br>- drq 0x74 = 2<br>- end<br>- device pnp 2e.4 off # Serial Port 3<br>- io 0x60 = 0x3e8<br>- irq 0x70 = 4<br>- end<br>- device pnp 2e.7 on # PS/2 Keyboard / Mouse<br>- io 0x60 = 0x60<br>- io 0x62 = 0x64<br>- irq 0x70 = 1 # PS/2 keyboard interrupt<br>- irq 0x72 = 12 # PS/2 mouse interrupt<br>- end<br>- device pnp 2e.a off # Runtime registers<br>- io 0x60 = 0x600<br>- end<br>- end<br>- end<br>- device pci 1f.2 on end # SATA<br>- device pci 1f.3 on end # SMBus<br>- device pci 1f.4 on end # Performance counters<br>- end<br>- end<br>- device cpu_cluster 0 on<br>- chip cpu/intel/socket_BGA956<br>- device lapic 0 on end<br>- end<br>- end<br>-end<br>diff --git a/src/mainboard/intel/eagleheights/dsdt.asl b/src/mainboard/intel/eagleheights/dsdt.asl<br>deleted file mode 100644<br>index 4c98e54..0000000<br>--- a/src/mainboard/intel/eagleheights/dsdt.asl<br>+++ /dev/null<br>@@ -1,1041 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001)<br>-{<br>- Scope (\_PR)<br>- {<br>- Processor (CPU1, 0x01, 0x00000810, 0x06)<br>- {<br>- OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)<br>- Name (NCPU, 0x80)<br>- Name (TYPE, 0x80000000)<br>- Name (HNDL, 0x80000000)<br>- Name (CFGD, 0x80000000)<br>- Name (TBLD, 0x80)<br>- Method (_PDC, 1, NotSerialized)<br>- {<br>- }<br>- }<br>- }<br>-<br>- Scope (\_PR)<br>- {<br>- Processor (CPU2, 0x02, 0x00000000, 0x00)<br>- {<br>- OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)<br>- Name (NCPU, 0x80)<br>- Name (TYPE, 0x80000000)<br>- Name (HNDL, 0x80000000)<br>- Name (CFGD, 0x80000000)<br>- Name (TBLD, 0x80)<br>- Method (_PDC, 1, NotSerialized)<br>- {<br>- }<br>- }<br>- }<br>-<br>- /* For now only define 2 power states:<br>- * - S0 which is fully on<br>- * - S5 which is soft off<br>- * Any others would involve declaring the wake up methods.<br>- */<br>- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })<br>- Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })<br>-<br>- Name (PICM, 0x00)<br>- Method (_PIC, 1, NotSerialized)<br>- {<br>- Store (Arg0, PICM)<br>- }<br>-<br>- /* System bus */<br>- Scope (\_SB)<br>- {<br>- /* Routing PCI0 */<br>- Name (PR00, Package (0x0E)<br>- {<br>- Package (0x04){0x0001FFFF,0x00,LNKA,0x00}, /* EDMA INTA# */<br>- Package (0x04){0x0002FFFF,0x00,LNKA,0x00}, /* PCIe port A */<br>- Package (0x04){0x0002FFFF,0x01,LNKB,0x00},<br>- Package (0x04){0x0002FFFF,0x02,LNKC,0x00},<br>- Package (0x04){0x0002FFFF,0x03,LNKD,0x00},<br>- Package (0x04){0x0003FFFF,0x00,LNKA,0x00}, /* PCIe port A1 */<br>- Package (0x04){0x0003FFFF,0x01,LNKB,0x00},<br>- Package (0x04){0x0003FFFF,0x02,LNKC,0x00},<br>- Package (0x04){0x0003FFFF,0x03,LNKD,0x00},<br>- Package (0x04){0x001CFFFF,0x00,LNKE,0x00}, /* PCIe port B */<br>- Package (0x04){0x001DFFFF,0x00,LNKH,0x00}, /* UHCI/EHCI INTA# */<br>- Package (0x04){0x001DFFFF,0x01,LNKD,0x00}, /* UHCI INTB# */<br>- Package (0x04){0x001FFFFF,0x01,LNKD,0x00}, /* SATA/SMBUS INTB# */<br>- Package (0x04){0x001FFFFF,0x03,LNKA,0x00} /* CHAP INTD# */<br>- })<br>- Name (AR00, Package (0x0E)<br>- {<br>- Package (0x04){0x0001FFFF,0x00,0x00,0x10}, /* EDMA INTA# */<br>- Package (0x04){0x0002FFFF,0x00,0x00,0x10}, /* PCIe port A0 */<br>- Package (0x04){0x0002FFFF,0x01,0x00,0x11},<br>- Package (0x04){0x0002FFFF,0x02,0x00,0x12},<br>- Package (0x04){0x0002FFFF,0x03,0x00,0x13},<br>- Package (0x04){0x0003FFFF,0x00,0x00,0x10}, /* PCIe port A1 */<br>- Package (0x04){0x0003FFFF,0x01,0x00,0x11},<br>- Package (0x04){0x0003FFFF,0x02,0x00,0x12},<br>- Package (0x04){0x0003FFFF,0x03,0x00,0x13},<br>- Package (0x04){0x001CFFFF,0x00,0x00,0x14}, /* PCIe port B */<br>- Package (0x04){0x001DFFFF,0x00,0x00,0x17}, /* UHCI/EHCI INTA# */<br>- Package (0x04){0x001DFFFF,0x01,0x00,0x13}, /* UHCI INTB# */<br>- Package (0x04){0x001FFFFF,0x01,0x00,0x13}, /* SATA/SMBUS INTB# */<br>- Package (0x04){0x001FFFFF,0x0D,0x00,0x10} /* CHAP INTD# */<br>- })<br>- /* Routing PCIe Port A */<br>- Name (PR0A, Package (0x04)<br>- {<br>- Package (0x04){0xFFFF,0x00,LNKA,0x00},<br>- Package (0x04){0xFFFF,0x01,LNKB,0x00},<br>- Package (0x04){0xFFFF,0x02,LNKC,0x00},<br>- Package (0x04){0xFFFF,0x03,LNKD,0x00}<br>- })<br>- Name (AR0A, Package (0x04)<br>- {<br>- Package (0x04){0xFFFF,0x00,0x00,0x10},<br>- Package (0x04){0xFFFF,0x01,0x00,0x11},<br>- Package (0x04){0xFFFF,0x02,0x00,0x12},<br>- Package (0x04){0xFFFF,0x03,0x00,0x13}<br>- })<br>- /* Routing PCIe Port B */<br>- Name (PR0B, Package (0x04)<br>- {<br>- Package (0x04){0xFFFF,0x00,LNKA,0x00},<br>- Package (0x04){0xFFFF,0x01,LNKB,0x00},<br>- Package (0x04){0xFFFF,0x02,LNKC,0x00},<br>- Package (0x04){0xFFFF,0x03,LNKD,0x00}<br>- })<br>- Name (AR0B, Package (0x04)<br>- {<br>- Package (0x04){0xFFFF,0x00,0x00,0x10},<br>- Package (0x04){0xFFFF,0x01,0x00,0x11},<br>- Package (0x04){0xFFFF,0x02,0x00,0x12},<br>- Package (0x04){0xFFFF,0x03,0x00,0x13}<br>- })<br>- /* Routing Bus PCI */<br>- Name (PR01, Package (0x04)<br>- {<br>- Package (0x04){0x0000FFFF,0x00,LNKA,0x00},<br>- Package (0x04){0x0000FFFF,0x01,LNKB,0x00},<br>- Package (0x04){0x0000FFFF,0x02,LNKC,0x00},<br>- Package (0x04){0x0000FFFF,0x03,LNKD,0x00},<br>- })<br>- Name (AR01, Package (0x04)<br>- {<br>- Package (0x04){0x0000FFFF,0x00,0x00,0x10},<br>- Package (0x04){0x0000FFFF,0x01,0x00,0x11},<br>- Package (0x04){0x0000FFFF,0x02,0x00,0x12},<br>- Package (0x04){0x0000FFFF,0x03,0x00,0x13},<br>- })<br>-<br>- Name (PRSA, ResourceTemplate ()<br>- {<br>- IRQ (Level, ActiveLow, Shared, )<br>- {3,4,5,6,7,10,11,12,14,15}<br>- })<br>- Alias (PRSA, PRSB)<br>- Alias (PRSA, PRSC)<br>- Alias (PRSA, PRSD)<br>- Alias (PRSA, PRSE)<br>- Alias (PRSA, PRSF)<br>- Alias (PRSA, PRSG)<br>- Alias (PRSA, PRSH)<br>-<br>- Device (PCI0)<br>- {<br>- Name (_HID, EisaId ("PNP0A08"))<br>- Name (_CID, EisaId ("PNP0A03"))<br>- Name (_ADR, 0x00)<br>- Name (_SEG, 0x00)<br>- Name (_UID, 0x00)<br>- Name (_BBN, 0x00)<br>-<br>- Name (SUPP, 0) /* PCI _OSC Support Field Value */<br>- Name (CTRL, 0) /* PCI _OSC Control Field Value */<br>-<br>- Method (_OSC, 4)<br>- {<br>- /* Check for PCI/PCI-X/PCIe GUID */<br>- If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))<br>- {<br>- /* Let OS control everything */<br>- Return (Arg3)<br>- }<br>- Else<br>- {<br>- /* Unrecognized UUID, so set bit 2 of Arg3 to 1 */<br>- CreateDWordField (Arg3, 0, CDW1)<br>- Or (CDW1, 4, CDW1)<br>- Return (Arg3)<br>- }<br>- } /* End _OSC */<br>-<br>- Method (_PRT, 0, NotSerialized)<br>- {<br>- If (PICM)<br>- {<br>- Return (AR00)<br>- }<br>-<br>- Return (PR00)<br>- }<br>-<br>- /* PCI Express Port A */<br>- Device (EPA0)<br>- {<br>- Name (_ADR, 0x00020000)<br>- Method (_PRT, 0, NotSerialized)<br>- {<br>- If (PICM)<br>- {<br>- Return (AR0A)<br>- }<br>-<br>- Return (PR0A)<br>- }<br>- }<br>-<br>- /* PCI Express Port A1 */<br>- Device (EPA1)<br>- {<br>- Name (_ADR, 0x00030000)<br>- Method (_PRT, 0, NotSerialized)<br>- {<br>- If (PICM)<br>- {<br>- Return (AR0A)<br>- }<br>-<br>- Return (PR0A)<br>- }<br>- }<br>-<br>- /* PCI Express Port B0 */<br>- Device (EPB0)<br>- {<br>- Name (_ADR, 0x001C0000)<br>- Method (_PRT, 0, NotSerialized)<br>- {<br>- If (PICM)<br>- {<br>- Return (AR0B)<br>- }<br>-<br>- Return (PR0B)<br>- }<br>- }<br>-<br>- /* PCI Bridge */<br>- Device (P0P1)<br>- {<br>- Name (_ADR, 0x001E0000)<br>-<br>- Method (_PRT, 0, NotSerialized)<br>- {<br>- If (PICM)<br>- {<br>- Return (AR01)<br>- }<br>-<br>- Return (PR01)<br>- }<br>- }<br>-<br>- /* LPC I/F Bridge */<br>- Device (ISA) {<br>- Name (_ADR, 0x001F0000)<br>-<br>- /* MMCONF */<br>- Device (^PCIE)<br>- {<br>- Name (_HID, EisaId ("PNP0C02"))<br>- Name (_UID, 0x11)<br>- Name (CRS, ResourceTemplate ()<br>- {<br>- Memory32Fixed (ReadOnly,<br>- 0xE0000000, // Address Base<br>- 0x10000000, // Address Length<br>- _Y10)<br>- })<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._BAS, BAS1)<br>- CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._LEN, LEN1)<br>- Store (0xE0000000, BAS1)<br>- Store (0x10000000, LEN1)<br>- Return (CRS)<br>- }<br>- }<br>-<br>- /* PIC */<br>- Device (PIC)<br>- {<br>- Name (_HID, EisaId ("PNP0000"))<br>- Name (_CRS, ResourceTemplate()<br>- {<br>- IO (Decode16,<br>- 0x0020,<br>- 0x0020,<br>- 0x00,<br>- 0x02,<br>- )<br>- IO (Decode16,<br>- 0x00A0,<br>- 0x00A0,<br>- 0x00,<br>- 0x02,<br>- )<br>- IRQNoFlags ()<br>- {2}<br>- })<br>- }<br>-<br>- /* Real time clock */<br>- Device (RTC0)<br>- {<br>- Name (_HID, EisaId ("PNP0B00"))<br>- Name (_CRS, ResourceTemplate ()<br>- {<br>- IO (Decode16,<br>- 0x0070,<br>- 0x0070,<br>- 0x00,<br>- 0x02)<br>- IRQNoFlags ()<br>- {8}<br>- })<br>- }<br>-<br>- Device (UAR1)<br>- {<br>- Name (_UID, 0x01)<br>- Name (_HID, EisaId ("PNP0501"))<br>-<br>- Method (_PRS, 0, NotSerialized)<br>- {<br>- Return (CMPR)<br>- }<br>-<br>- Name (CMPR, ResourceTemplate ()<br>- {<br>- StartDependentFn (0x00, 0x00)<br>- {<br>- IO (Decode16,0x03F8,0x03F8,0x01,0x08)<br>- IRQNoFlags () {4}<br>- DMA (Compatibility, NotBusMaster, Transfer8) {}<br>- }<br>- StartDependentFnNoPri ()<br>- {<br>- IO (Decode16,0x03F8,0x03F8,0x01,0x08)<br>- IRQNoFlags () {3,4,5,6,7,10,11,12}<br>- DMA (Compatibility, NotBusMaster, Transfer8) {}<br>- }<br>- StartDependentFnNoPri ()<br>- {<br>- IO (Decode16,0x02F8,0x02F8,0x01,0x08)<br>- IRQNoFlags () {3,4,5,6,7,10,11,12}<br>- DMA (Compatibility, NotBusMaster, Transfer8) {}<br>- }<br>- StartDependentFnNoPri ()<br>- {<br>- IO (Decode16,0x03E8,0x03E8,0x01,0x08)<br>- IRQNoFlags () {3,4,5,6,7,10,11,12}<br>- DMA (Compatibility, NotBusMaster, Transfer8) {}<br>- }<br>- StartDependentFnNoPri ()<br>- {<br>- IO (Decode16,0x02E8,0x02E8,0x01,0x08)<br>- IRQNoFlags () {3,4,5,6,7,10,11,12}<br>- DMA (Compatibility, NotBusMaster, Transfer8) {}<br>- }<br>- EndDependentFn ()<br>- })<br>- }<br>-<br>- /* PS/2 keyboard (seems to be important for WinXP install) */<br>- Device (KBD)<br>- {<br>- Name (_HID, EisaId ("PNP0303"))<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- Return (0x0f)<br>- }<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- Name (TMP, ResourceTemplate () {<br>- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)<br>- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)<br>- IRQNoFlags () {1}<br>- })<br>- Return (TMP)<br>- }<br>- }<br>-<br>- /* PS/2 mouse */<br>- Device (MOU)<br>- {<br>- Name (_HID, EisaId ("PNP0F13"))<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- Return (0x0f)<br>- }<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- Name (TMP, ResourceTemplate () {<br>- IRQNoFlags () {12}<br>- })<br>- Return (TMP)<br>- }<br>- }<br>-<br>- /* COM ports of SIO */<br>- Device(SIO) {<br>- Name (_ADR, 0x4E)<br>- OperationRegion (PT4E, SystemIO, 0x4E, 0x02)<br>- Field (PT4E, ByteAcc, NoLock, Preserve)<br>- {<br>- PO4E, 8,<br>- PO4F, 8<br>- }<br>-<br>- IndexField (PO4E, PO4F, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset (0x07),<br>- ILDN, 8,<br>- Offset (0x28),<br>- SIUI, 8,<br>- SIUC, 8,<br>- Offset (0x30),<br>- IACT, 8,<br>- Offset (0x60),<br>- IIOH, 8,<br>- IIOL, 8,<br>- Offset (0x70),<br>- IINT, 8<br>- }<br>-<br>- Method (IENF, 0, NotSerialized)<br>- {<br>- Store (0x80, PO4E)<br>- Store (0x86, PO4E)<br>- }<br>-<br>- Method (IEXF, 0, NotSerialized)<br>- {<br>- Store (0x68, PO4E)<br>- Store (0x08, PO4E)<br>- }<br>-<br>- Device (COM1)<br>- {<br>- Name (_UID, 0x03)<br>- Name (_HID, EisaId ("PNP0501"))<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- IENF ()<br>- Store (0x04, ILDN)<br>- Store (IACT, Local0)<br>- IEXF ()<br>- If (LEqual (Local0, 0xFF))<br>- {<br>- Return (0x00)<br>- }<br>-<br>- If (LEqual (Local0, One))<br>- {<br>- Return (0x0F)<br>- }<br>- Else<br>- {<br>- Return (0x0D)<br>- }<br>- }<br>-<br>- Method (_DIS, 0, NotSerialized)<br>- {<br>- IENF ()<br>- Store (0x04, ILDN)<br>- Store (Zero, IACT)<br>- IEXF ()<br>- }<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- Name (BFU1, ResourceTemplate ()<br>- {<br>- IO (Decode16,<br>- 0x03F8, // Range Minimum<br>- 0x03F8, // Range Maximum<br>- 0x08, // Alignment<br>- 0x08, // Length<br>- _Y03)<br>- IRQNoFlags (_Y04)<br>- {5}<br>- })<br>- CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MIN, IMIN)<br>- CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MAX, IMAX)<br>- CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y04._INT, IRQ0)<br>- IENF ()<br>- Store (0x04, ILDN)<br>- Store (IIOH, Local0)<br>- ShiftLeft (Local0, 0x08, Local1)<br>- Store (IIOL, Local0)<br>- Add (Local1, Local0, Local0)<br>- Store (Local0, IMIN)<br>- Store (Local0, IMAX)<br>- Store (IINT, Local0)<br>- IEXF ()<br>- Store (0x01, Local1)<br>- ShiftLeft (Local1, Local0, IRQ0)<br>- Return (BFU1)<br>- }<br>-<br>- Name (_PRS, ResourceTemplate ()<br>- {<br>- StartDependentFnNoPri ()<br>- {<br>- IO (Decode16,<br>- 0x03F8, // Range Minimum<br>- 0x03F8, // Range Maximum<br>- 0x08, // Alignment<br>- 0x08, // Length<br>- )<br>- IRQNoFlags ()<br>- {5}<br>- }<br>- StartDependentFnNoPri ()<br>- {<br>- IO (Decode16,<br>- 0x02F8, // Range Minimum<br>- 0x02F8, // Range Maximum<br>- 0x08, // Alignment<br>- 0x08, // Length<br>- )<br>- IRQNoFlags ()<br>- {9}<br>- }<br>- EndDependentFn ()<br>- })<br>- Method (_SRS, 1, NotSerialized)<br>- {<br>- CreateByteField (Arg0, 0x02, IOLO)<br>- CreateByteField (Arg0, 0x03, IOHI)<br>- CreateWordField (Arg0, 0x09, IRQ0)<br>- IENF ()<br>- Store (0x04, ILDN)<br>- Store (Zero, IACT)<br>- Store (IOLO, IIOL)<br>- Store (IOHI, IIOH)<br>- FindSetRightBit (IRQ0, Local0)<br>- If (LGreater (Local0, 0x00))<br>- {<br>- Decrement (Local0)<br>- }<br>-<br>- Store (Local0, IINT)<br>- Store (One, IACT)<br>- IEXF ()<br>- }<br>- } /* COM1 */<br>-<br>- Device (COM2)<br>- {<br>- Name (_UID, 0x04)<br>- Name (_HID, EisaId ("PNP0501"))<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- IENF ()<br>- Store (0x05, ILDN)<br>- Store (IACT, Local0)<br>- IEXF ()<br>- If (LEqual (Local0, 0xFF))<br>- {<br>- Return (0x00)<br>- }<br>-<br>- If (LEqual (Local0, One))<br>- {<br>- Return (0x0F)<br>- }<br>- Else<br>- {<br>- Return (0x0D)<br>- }<br>- }<br>-<br>- Method (_DIS, 0, NotSerialized)<br>- {<br>- IENF ()<br>- Store (0x05, ILDN)<br>- Store (Zero, IACT)<br>- IEXF ()<br>- }<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- Name (BFU1, ResourceTemplate ()<br>- {<br>- IO (Decode16,<br>- 0x03F8, // Range Minimum<br>- 0x03F8, // Range Maximum<br>- 0x08, // Alignment<br>- 0x08, // Length<br>- _Y05)<br>- IRQNoFlags (_Y06)<br>- {9}<br>- })<br>- CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MIN, IMIN)<br>- CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MAX, IMAX)<br>- CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y06._INT, IRQ0)<br>- IENF ()<br>- Store (0x05, ILDN)<br>- Store (IIOH, Local0)<br>- ShiftLeft (Local0, 0x08, Local1)<br>- Store (IIOL, Local0)<br>- Add (Local1, Local0, Local0)<br>- Store (Local0, IMIN)<br>- Store (Local0, IMAX)<br>- Store (IINT, Local0)<br>- IEXF ()<br>- Store (0x01, Local1)<br>- ShiftLeft (Local1, Local0, IRQ0)<br>- Return (BFU1)<br>- }<br>-<br>- Name (_PRS, ResourceTemplate ()<br>- {<br>- StartDependentFnNoPri ()<br>- {<br>- IO (Decode16,<br>- 0x03F8, // Range Minimum<br>- 0x03F8, // Range Maximum<br>- 0x08, // Alignment<br>- 0x08, // Length<br>- )<br>- IRQNoFlags ()<br>- {5}<br>- }<br>- StartDependentFnNoPri ()<br>- {<br>- IO (Decode16,<br>- 0x02F8, // Range Minimum<br>- 0x02F8, // Range Maximum<br>- 0x08, // Alignment<br>- 0x08, // Length<br>- )<br>- IRQNoFlags ()<br>- {9}<br>- }<br>- EndDependentFn ()<br>- })<br>- Method (_SRS, 1, NotSerialized)<br>- {<br>- CreateByteField (Arg0, 0x02, IOLO)<br>- CreateByteField (Arg0, 0x03, IOHI)<br>- CreateWordField (Arg0, 0x09, IRQ0)<br>- IENF ()<br>- Store (0x05, ILDN)<br>- Store (Zero, IACT)<br>- Store (IOLO, IIOL)<br>- Store (IOHI, IIOH)<br>- FindSetRightBit (IRQ0, Local0)<br>- If (LGreater (Local0, 0x00))<br>- {<br>- Decrement (Local0)<br>- }<br>-<br>- Store (Local0, IINT)<br>- Store (One, IACT)<br>- IEXF ()<br>- }<br>- } /* COM2 */<br>- } /* Device SIO */<br>- } /* Device ISA */<br>- } /* Device PCI 0*/<br>- } /* Scope SB */<br>-<br>- OperationRegion (_SB.PCI0.ISA.PIX0, PCI_Config, 0x60, 0x0C)<br>- Field (\_SB.PCI0.ISA.PIX0, ByteAcc, NoLock, Preserve)<br>- {<br>- PIRA, 8,<br>- PIRB, 8,<br>- PIRC, 8,<br>- PIRD, 8,<br>- Offset (0x08),<br>- PIRE, 8,<br>- PIRF, 8,<br>- PIRG, 8,<br>- PIRH, 8<br>- }<br>-<br>- Scope (_SB)<br>- {<br>- Name (BUFA, ResourceTemplate ()<br>- {<br>- IRQ (Level, ActiveLow, Shared, _Y1C)<br>- {15}<br>- })<br>- CreateWordField (BUFA, \_SB._Y1C._INT, IRA0)<br>- Device (LNKA)<br>- {<br>- Name (_HID, EisaId ("PNP0C0F"))<br>- Name (_UID, 0x01)<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- And (PIRA, 0x80, Local0)<br>- If (Local0)<br>- {<br>- Return (0x09)<br>- }<br>- Else<br>- {<br>- Return (0x0B)<br>- }<br>- }<br>-<br>- Method (_PRS, 0, NotSerialized)<br>- {<br>- Return (PRSA)<br>- }<br>-<br>- Method (_DIS, 0, NotSerialized)<br>- {<br>- Or (PIRA, 0x80, PIRA)<br>- }<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- And (PIRA, 0x0F, Local0)<br>- ShiftLeft (0x01, Local0, IRA0)<br>- Return (BUFA)<br>- }<br>-<br>- Method (_SRS, 1, NotSerialized)<br>- {<br>- CreateWordField (Arg0, 0x01, IRA)<br>- FindSetRightBit (IRA, Local0)<br>- Decrement (Local0)<br>- Store (Local0, PIRA)<br>- }<br>- }<br>-<br>- Device (LNKB)<br>- {<br>- Name (_HID, EisaId ("PNP0C0F"))<br>- Name (_UID, 0x02)<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- And (PIRB, 0x80, Local0)<br>- If (Local0)<br>- {<br>- Return (0x09)<br>- }<br>- Else<br>- {<br>- Return (0x0B)<br>- }<br>- }<br>-<br>- Method (_PRS, 0, NotSerialized)<br>- {<br>- Return (PRSB)<br>- }<br>-<br>- Method (_DIS, 0, NotSerialized)<br>- {<br>- Or (PIRB, 0x80, PIRB)<br>- }<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- And (PIRB, 0x0F, Local0)<br>- ShiftLeft (0x01, Local0, IRA0)<br>- Return (BUFA)<br>- }<br>-<br>- Method (_SRS, 1, NotSerialized)<br>- {<br>- CreateWordField (Arg0, 0x01, IRA)<br>- FindSetRightBit (IRA, Local0)<br>- Decrement (Local0)<br>- Store (Local0, PIRB)<br>- }<br>- }<br>-<br>- Device (LNKC)<br>- {<br>- Name (_HID, EisaId ("PNP0C0F"))<br>- Name (_UID, 0x03)<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- And (PIRC, 0x80, Local0)<br>- If (Local0)<br>- {<br>- Return (0x09)<br>- }<br>- Else<br>- {<br>- Return (0x0B)<br>- }<br>- }<br>-<br>- Method (_PRS, 0, NotSerialized)<br>- {<br>- Return (PRSC)<br>- }<br>-<br>- Method (_DIS, 0, NotSerialized)<br>- {<br>- Or (PIRC, 0x80, PIRC)<br>- }<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- And (PIRC, 0x0F, Local0)<br>- ShiftLeft (0x01, Local0, IRA0)<br>- Return (BUFA)<br>- }<br>-<br>- Method (_SRS, 1, NotSerialized)<br>- {<br>- CreateWordField (Arg0, 0x01, IRA)<br>- FindSetRightBit (IRA, Local0)<br>- Decrement (Local0)<br>- Store (Local0, PIRC)<br>- }<br>- }<br>-<br>- Device (LNKD)<br>- {<br>- Name (_HID, EisaId ("PNP0C0F"))<br>- Name (_UID, 0x04)<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- And (PIRD, 0x80, Local0)<br>- If (Local0)<br>- {<br>- Return (0x09)<br>- }<br>- Else<br>- {<br>- Return (0x0B)<br>- }<br>- }<br>-<br>- Method (_PRS, 0, NotSerialized)<br>- {<br>- Return (PRSD)<br>- }<br>-<br>- Method (_DIS, 0, NotSerialized)<br>- {<br>- Or (PIRD, 0x80, PIRD)<br>- }<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- And (PIRD, 0x0F, Local0)<br>- ShiftLeft (0x01, Local0, IRA0)<br>- Return (BUFA)<br>- }<br>-<br>- Method (_SRS, 1, NotSerialized)<br>- {<br>- CreateWordField (Arg0, 0x01, IRA)<br>- FindSetRightBit (IRA, Local0)<br>- Decrement (Local0)<br>- Store (Local0, PIRD)<br>- }<br>- }<br>-<br>- Device (LNKE)<br>- {<br>- Name (_HID, EisaId ("PNP0C0F"))<br>- Name (_UID, 0x05)<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- And (PIRE, 0x80, Local0)<br>- If (Local0)<br>- {<br>- Return (0x09)<br>- }<br>- Else<br>- {<br>- Return (0x0B)<br>- }<br>- }<br>-<br>- Method (_PRS, 0, NotSerialized)<br>- {<br>- Return (PRSE)<br>- }<br>-<br>- Method (_DIS, 0, NotSerialized)<br>- {<br>- Or (PIRE, 0x80, PIRE)<br>- }<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- And (PIRE, 0x0F, Local0)<br>- ShiftLeft (0x01, Local0, IRA0)<br>- Return (BUFA)<br>- }<br>-<br>- Method (_SRS, 1, NotSerialized)<br>- {<br>- CreateWordField (Arg0, 0x01, IRA)<br>- FindSetRightBit (IRA, Local0)<br>- Decrement (Local0)<br>- Store (Local0, PIRE)<br>- }<br>- }<br>-<br>- Device (LNKF)<br>- {<br>- Name (_HID, EisaId ("PNP0C0F"))<br>- Name (_UID, 0x06)<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- And (PIRF, 0x80, Local0)<br>- If (Local0)<br>- {<br>- Return (0x09)<br>- }<br>- Else<br>- {<br>- Return (0x0B)<br>- }<br>- }<br>-<br>- Method (_PRS, 0, NotSerialized)<br>- {<br>- Return (PRSF)<br>- }<br>-<br>- Method (_DIS, 0, NotSerialized)<br>- {<br>- Or (PIRF, 0x80, PIRF)<br>- }<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- And (PIRF, 0x0F, Local0)<br>- ShiftLeft (0x01, Local0, IRA0)<br>- Return (BUFA)<br>- }<br>-<br>- Method (_SRS, 1, NotSerialized)<br>- {<br>- CreateWordField (Arg0, 0x01, IRA)<br>- FindSetRightBit (IRA, Local0)<br>- Decrement (Local0)<br>- Store (Local0, PIRF)<br>- }<br>- }<br>-<br>- Device (LNKG)<br>- {<br>- Name (_HID, EisaId ("PNP0C0F"))<br>- Name (_UID, 0x07)<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- And (PIRG, 0x80, Local0)<br>- If (Local0)<br>- {<br>- Return (0x09)<br>- }<br>- Else<br>- {<br>- Return (0x0B)<br>- }<br>- }<br>-<br>- Method (_PRS, 0, NotSerialized)<br>- {<br>- Return (PRSG)<br>- }<br>-<br>- Method (_DIS, 0, NotSerialized)<br>- {<br>- Or (PIRG, 0x80, PIRG)<br>- }<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- And (PIRG, 0x0F, Local0)<br>- ShiftLeft (0x01, Local0, IRA0)<br>- Return (BUFA)<br>- }<br>-<br>- Method (_SRS, 1, NotSerialized)<br>- {<br>- CreateWordField (Arg0, 0x01, IRA)<br>- FindSetRightBit (IRA, Local0)<br>- Decrement (Local0)<br>- Store (Local0, PIRG)<br>- }<br>- }<br>-<br>- Device (LNKH)<br>- {<br>- Name (_HID, EisaId ("PNP0C0F"))<br>- Name (_UID, 0x08)<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- And (PIRH, 0x80, Local0)<br>- If (Local0)<br>- {<br>- Return (0x09)<br>- }<br>- Else<br>- {<br>- Return (0x0B)<br>- }<br>- }<br>-<br>- Method (_PRS, 0, NotSerialized)<br>- {<br>- Return (PRSH)<br>- }<br>-<br>- Method (_DIS, 0, NotSerialized)<br>- {<br>- Or (PIRH, 0x80, PIRH)<br>- }<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- And (PIRH, 0x0F, Local0)<br>- ShiftLeft (0x01, Local0, IRA0)<br>- Return (BUFA)<br>- }<br>-<br>- Method (_SRS, 1, NotSerialized)<br>- {<br>- CreateWordField (Arg0, 0x01, IRA)<br>- FindSetRightBit (IRA, Local0)<br>- Decrement (Local0)<br>- Store (Local0, PIRH)<br>- }<br>- }<br>- }<br>-}<br>diff --git a/src/mainboard/intel/eagleheights/fadt.c b/src/mainboard/intel/eagleheights/fadt.c<br>deleted file mode 100644<br>index eaea7f7..0000000<br>--- a/src/mainboard/intel/eagleheights/fadt.c<br>+++ /dev/null<br>@@ -1,177 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2008 coresystems GmbH<br>- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <string.h><br>-#include <device/pci.h><br>-#include <arch/acpi.h><br>-#include <cpu/x86/smm.h><br>-<br>-#define ACPI_PM1_STS (pmbase + 0x00)<br>-#define ACPI_PM1_EN (pmbase + 0x02)<br>-#define ACPI_PM1_CNT (pmbase + 0x04)<br>-#define ACPI_PM1_TMR (pmbase + 0x08)<br>-#define ACPI_PROC_CNT (pmbase + 0x10)<br>-#define ACPI_LV2 (pmbase + 0x14)<br>-#define ACPI_GPE0_STS (pmbase + 0x28)<br>-#define ACPI_GPE0_EN (pmbase + 0x2C)<br>-#define ACPI_SMI_EN (pmbase + 0x30)<br>-#define ACPI_SMI_STS (pmbase + 0x34)<br>-#define ACPI_ALT_GP_SMI_EN (pmbase + 0x38)<br>-#define ACPI_ALT_GP_SMI_STS (pmbase + 0x3A)<br>-#define ACPI_MON_SMI (pmbase + 0x40)<br>-#define ACPI_DEVACT_STS (pmbase + 0x44)<br>-#define ACPI_DEVTRAP_EN (pmbase + 0x48)<br>-#define ACPI_BUS_ADDR_TRACK (pmbase + 0x4C)<br>-#define ACPI_BUS_CYC_TRACK (pmbase + 0x4E)<br>-<br>-#define ACPI_PM1a_EVT_BLK ACPI_PM1_STS<br>-#define ACPI_PM1a_CNT_BLK ACPI_PM1_CNT<br>-#define ACPI_PM_TMR_BLK ACPI_PM1_TMR<br>-#define ACPI_P_BLK ACPI_PROC_CNT<br>-#define ACPI_GPE0_BLK ACPI_GPE0_STS<br>-<br>-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)<br>-{<br>- acpi_header_t *header = &(fadt->header);<br>- u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;<br>-<br>- memset((void *) fadt, 0, sizeof(acpi_fadt_t));<br>- memcpy(header->signature, "FACP", 4);<br>- header->length = 244;<br>- header->revision = 3;<br>- memcpy(header->oem_id, OEM_ID, 6);<br>- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);<br>- memcpy(header->asl_compiler_id, ASLC, 4);<br>- header->asl_compiler_revision = 0;<br>-<br>- fadt->firmware_ctrl = (unsigned long) facs;<br>- fadt->dsdt = (unsigned long) dsdt;<br>- fadt->preferred_pm_profile = 7; /* Performance Server */<br>- fadt->sci_int = 0x9;<br>-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br>- fadt->smi_cmd = APM_CNT;<br>-#else<br>- fadt->smi_cmd = 0x00;<br>-#endif<br>- fadt->acpi_enable = APM_CNT_ACPI_ENABLE;<br>- fadt->acpi_disable = APM_CNT_ACPI_DISABLE;<br>- fadt->s4bios_req = 0x0;<br>- fadt->pstate_cnt = 0xe2;<br>-<br>- fadt->pm1a_evt_blk = pmbase;<br>- fadt->pm1b_evt_blk = 0x0;<br>- fadt->pm1a_cnt_blk = pmbase + 0x4;<br>- fadt->pm1b_cnt_blk = 0x0;<br>- fadt->pm2_cnt_blk = 0x0;<br>- fadt->pm_tmr_blk = pmbase + 0x8;<br>- fadt->gpe0_blk = pmbase + 0x28;<br>- fadt->gpe1_blk = 0x0;<br>-<br>- fadt->pm1_evt_len = 0x4;<br>- fadt->pm1_cnt_len = 0x2;<br>- fadt->pm2_cnt_len = 0x0;<br>- fadt->pm_tmr_len = 0x4;<br>- fadt->gpe0_blk_len = 0x8;<br>- fadt->gpe1_blk_len = 0x0;<br>- fadt->gpe1_base = 0x0;<br>- fadt->cst_cnt = 0xe3;<br>- fadt->p_lvl2_lat = 0x65;<br>- fadt->p_lvl3_lat = 0x3e9;<br>- fadt->flush_size = 0x400;<br>- fadt->flush_stride = 0x10;<br>- fadt->duty_offset = 0x1;<br>- fadt->duty_width = 0x3;<br>- fadt->day_alrm = 0xd;<br>- fadt->mon_alrm = 0x00;<br>- fadt->century = 0x00;<br>- fadt->iapc_boot_arch = 0x03;<br>- fadt->flags = 0xa5;<br>-<br>- fadt->reset_reg.space_id = 1;<br>- fadt->reset_reg.bit_width = 8;<br>- fadt->reset_reg.bit_offset = 0;<br>- fadt->reset_reg.resv = 0;<br>- fadt->reset_reg.addrl = 0xcf9;<br>- fadt->reset_reg.addrh = 0;<br>- fadt->reset_value = 6;<br>- fadt->res3 = 0;<br>- fadt->res4 = 0;<br>- fadt->res5 = 0;<br>- fadt->x_firmware_ctl_l = (u32)facs;<br>- fadt->x_firmware_ctl_h = 0;<br>- fadt->x_dsdt_l = (u32)dsdt;<br>- fadt->x_dsdt_h = 0;<br>-<br>- fadt->x_pm1a_evt_blk.space_id = 1;<br>- fadt->x_pm1a_evt_blk.bit_width = 32;<br>- fadt->x_pm1a_evt_blk.bit_offset = 0;<br>- fadt->x_pm1a_evt_blk.resv = 0;<br>- fadt->x_pm1a_evt_blk.addrl = pmbase;<br>- fadt->x_pm1a_evt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm1b_evt_blk.space_id = 1;<br>- fadt->x_pm1b_evt_blk.bit_width = 32;<br>- fadt->x_pm1b_evt_blk.bit_offset = 0;<br>- fadt->x_pm1b_evt_blk.resv = 0;<br>- fadt->x_pm1b_evt_blk.addrl = 0x0;<br>- fadt->x_pm1b_evt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm1a_cnt_blk.space_id = 1;<br>- fadt->x_pm1a_cnt_blk.bit_width = 16;<br>- fadt->x_pm1a_cnt_blk.bit_offset = 0;<br>- fadt->x_pm1a_cnt_blk.resv = 0;<br>- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;<br>- fadt->x_pm1a_cnt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm1b_cnt_blk.space_id = 1;<br>- fadt->x_pm1b_cnt_blk.bit_width = 0;<br>- fadt->x_pm1b_cnt_blk.bit_offset = 0;<br>- fadt->x_pm1b_cnt_blk.resv = 0;<br>- fadt->x_pm1b_cnt_blk.addrl = 0x0;<br>- fadt->x_pm1b_cnt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm2_cnt_blk.space_id = 1;<br>- fadt->x_pm2_cnt_blk.bit_width = 0;<br>- fadt->x_pm2_cnt_blk.bit_offset = 0;<br>- fadt->x_pm2_cnt_blk.resv = 0;<br>- fadt->x_pm2_cnt_blk.addrl = 0x0;<br>- fadt->x_pm2_cnt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm_tmr_blk.space_id = 1;<br>- fadt->x_pm_tmr_blk.bit_width = 32;<br>- fadt->x_pm_tmr_blk.bit_offset = 0;<br>- fadt->x_pm_tmr_blk.resv = 0;<br>- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;<br>- fadt->x_pm_tmr_blk.addrh = 0x0;<br>-<br>- fadt->x_gpe0_blk.space_id = 1;<br>- fadt->x_gpe0_blk.bit_width = 64;<br>- fadt->x_gpe0_blk.bit_offset = 0;<br>- fadt->x_gpe0_blk.resv = 0;<br>- fadt->x_gpe0_blk.addrl = pmbase + 0x28;<br>- fadt->x_gpe0_blk.addrh = 0x0;<br>-<br>- fadt->x_gpe1_blk.space_id = 1;<br>- fadt->x_gpe1_blk.bit_width = 32;<br>- fadt->x_gpe1_blk.bit_offset = 0;<br>- fadt->x_gpe1_blk.resv = 0;<br>- fadt->x_gpe1_blk.addrl = 0x0;<br>- fadt->x_gpe1_blk.addrh = 0x0;<br>-<br>- header->checksum =<br>- acpi_checksum((void *) fadt, header->length);<br>-}<br>diff --git a/src/mainboard/intel/eagleheights/ioapic.h b/src/mainboard/intel/eagleheights/ioapic.h<br>deleted file mode 100644<br>index 82618f6..0000000<br>--- a/src/mainboard/intel/eagleheights/ioapic.h<br>+++ /dev/null<br>@@ -1,15 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#define IOAPIC_I3100 2<br>-#define INTEL_IOAPIC_NUM_INTERRUPTS 24<br>diff --git a/src/mainboard/intel/eagleheights/irq_tables.c b/src/mainboard/intel/eagleheights/irq_tables.c<br>deleted file mode 100644<br>index 0267d62..0000000<br>--- a/src/mainboard/intel/eagleheights/irq_tables.c<br>+++ /dev/null<br>@@ -1,51 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */<br>- 0x00, /* Interrupt router bus */<br>- (0x1f << 3) | 0x0, /* Interrupt router dev */<br>- 0, /* IRQs devoted exclusively to PCI usage */<br>- 0x8086, /* Vendor */<br>- 0x2670, /* Device */<br>- 0, /* Miniport */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0x4b, /* Checksum (has to be set to some value that<br>- * would give 0 after the sum of all bytes<br>- * for this structure (including checksum).<br>- */<br>- {<br>- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},<br>- {0x00, (0x03 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},<br>- {0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- {0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},<br>- {0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0},<br>- {0x01, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x1, 0x0},<br>- {0x01, (0x01 << 3) | 0x0, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},<br>- }<br>-};<br>-<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c<br>deleted file mode 100644<br>index dae3879..0000000<br>--- a/src/mainboard/intel/eagleheights/mptable.c<br>+++ /dev/null<br>@@ -1,225 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2008 coresystems GmbH<br>- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <arch/ioapic.h><br>-#include <arch/smp/mpspec.h><br>-#include <device/pci.h><br>-#include <string.h><br>-#include <stdint.h><br>-<br>-// Generate MP-table IRQ numbers for PCI devices.<br>-#define IO_APIC0 2<br>-<br>-#define INT_A 0<br>-#define INT_B 1<br>-#define INT_C 2<br>-#define INT_D 3<br>-#define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine)<br>-<br>-#define PIRQ_A 16<br>-#define PIRQ_B 17<br>-#define PIRQ_C 18<br>-#define PIRQ_D 19<br>-#define PIRQ_E 20<br>-#define PIRQ_F 21<br>-#define PIRQ_G 22<br>-#define PIRQ_H 23<br>-<br>-// RCBA<br>-#define RCBA 0xF0<br>-<br>-#define RCBA_D31IP 0x3100<br>-#define RCBA_D30IP 0x3104<br>-#define RCBA_D29IP 0x3108<br>-#define RCBA_D28IP 0x310C<br>-#define RCBA_D31IR 0x3140<br>-#define RCBA_D30IR 0x3142<br>-#define RCBA_D29IR 0x3144<br>-#define RCBA_D28IR 0x3146<br>-<br>-static void *smp_write_config_table(void *v)<br>-{<br>- struct mp_config_table *mc;<br>- unsigned char bus_chipset, bus_pci;<br>- unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b;<br>- int bus_isa, i;<br>- uint32_t pin, route;<br>- device_t dev;<br>- struct resource *res;<br>- u8 *rcba;<br>-<br>- dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));<br>- res = find_resource(dev, RCBA);<br>- if (!res) {<br>- return NULL;<br>- }<br>- rcba = res2mmio(res, 0, 0);<br>-<br>- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);<br>-<br>- mptable_init(mc, LOCAL_APIC_ADDR);<br>-<br>- smp_write_processors(mc);<br>-<br>- /* Get bus numbers */<br>- bus_chipset = 0;<br>-<br>- /* PCI */<br>- dev = dev_find_slot(0, PCI_DEVFN(0x1E,0));<br>- if (dev) {<br>- bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS);<br>- } else {<br>- printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");<br>- bus_pci = 6;<br>- }<br>-<br>- dev = dev_find_slot(0, PCI_DEVFN(2,0));<br>- if(dev) {<br>- bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS);<br>- } else {<br>- printk(BIOS_DEBUG, "ERROR - could not find PCIe Port A 0:2.0, using defaults\n");<br>- bus_pcie_a = 1;<br>- }<br>-<br>- dev = dev_find_slot(0, PCI_DEVFN(3,0));<br>- if(dev) {<br>- bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS);<br>- } else {<br>- printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");<br>- bus_pcie_a1 = 2;<br>- }<br>-<br>- dev = dev_find_slot(0, PCI_DEVFN(0x1C,0));<br>- if(dev) {<br>- bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS);<br>- } else {<br>- printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");<br>- bus_pcie_b = 3;<br>- }<br>-<br>- mptable_write_buses(mc, NULL, &bus_isa);<br>-<br>- /*I/O APICs: APIC ID Version State Address*/<br>- smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);<br>-<br>- mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);<br>-<br>- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/<br>- mptable_lintsrc(mc, bus_isa);<br>-<br>- /* Internal PCI device for i3100 */<br>-<br>- /* EDMA<br>- */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(1, INT_A), IO_APIC0, PIRQ_A);<br>-<br>- /* PCIe Port A<br>- */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(2, INT_A), IO_APIC0, PIRQ_A);<br>-<br>- /* PCIe Port A1<br>- */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(3, INT_A), IO_APIC0, PIRQ_A);<br>-<br>- /* PCIe Port B<br>- */<br>- for(i = 0; i < 4; i++) {<br>- pin = (read32(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;<br>- if(pin > 0) {<br>- pin -= 1;<br>- route = PIRQ_A + ((read16(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);<br>- }<br>- }<br>-<br>- /* USB 1.1 : device 29, function 0, 1<br>- */<br>- for(i = 0; i < 2; i++) {<br>- pin = (read32(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;<br>- if(pin > 0) {<br>- pin -= 1;<br>- route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);<br>- }<br>- }<br>-<br>- /* USB 2.0 : device 29, function 7<br>- */<br>- pin = (read32(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;<br>- if(pin > 0) {<br>- pin -= 1;<br>- route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);<br>- }<br>-<br>- /* SATA : device 31 function 2<br>- * SMBus : device 31 function 3<br>- * Performance counters : device 31 function 4<br>- */<br>- for(i = 2; i < 5; i++) {<br>- pin = (read32(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;<br>- if(pin > 0) {<br>- pin -= 1;<br>- route = PIRQ_A + ((read16(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);<br>- }<br>- }<br>-<br>- /* SLOTS */<br>-<br>- /* PCIe 4x slot A<br>- */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);<br>-<br>- /* PCIe 4x slot A1<br>- */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);<br>-<br>- /* PCIe 4x slot B<br>- */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);<br>-<br>- /* PCI slot<br>- */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);<br>-<br>- /* There is no extension information... */<br>-<br>- /* Compute the checksums */<br>- return mptable_finalize(mc);<br>-}<br>-<br>-unsigned long write_smp_table(unsigned long addr)<br>-{<br>- void *v;<br>- v = smp_write_floating_table(addr, 0);<br>- return (unsigned long)smp_write_config_table(v);<br>-}<br>diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c<br>deleted file mode 100644<br>index c254f17..0000000<br>--- a/src/mainboard/intel/eagleheights/romstage.c<br>+++ /dev/null<br>@@ -1,188 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2008 coresystems GmbH<br>- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <stdlib.h><br>-#include <device/pci_def.h><br>-#include <device/pci_ids.h><br>-#include <arch/io.h><br>-#include <device/pnp_def.h><br>-#include <cpu/x86/lapic.h><br>-#include <pc80/mc146818rtc.h><br>-#include <console/console.h><br>-#include <delay.h><br>-#include <cpu/x86/bist.h><br>-#include <cpu/intel/romstage.h><br>-#include <cpu/intel/speedstep.h><br>-#include "southbridge/intel/i3100/early_smbus.c"<br>-#include "southbridge/intel/i3100/early_lpc.c"<br>-#include "southbridge/intel/i3100/reset.c"<br>-#include <superio/intel/i3100/i3100.h><br>-#include <superio/smsc/smscsuperio/smscsuperio.h><br>-#include <northbridge/intel/i3100/i3100.h><br>-#include <southbridge/intel/i3100/i3100.h><br>-#include "lib/debug.c" // XXX<br>-<br>-#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)<br>-#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)<br>-<br>-#define RCBA_RPC 0x0224 /* 32 bit */<br>-<br>-#define RCBA_TCTL 0x3000 /* 8 bit */<br>-<br>-#define RCBA_D31IP 0x3100 /* 32 bit */<br>-#define RCBA_D30IP 0x3104 /* 32 bit */<br>-#define RCBA_D29IP 0x3108 /* 32 bit */<br>-#define RCBA_D28IP 0x310C /* 32 bit */<br>-#define RCBA_D31IR 0x3140 /* 16 bit */<br>-#define RCBA_D30IR 0x3142 /* 16 bit */<br>-#define RCBA_D29IR 0x3144 /* 16 bit */<br>-#define RCBA_D28IR 0x3146 /* 16 bit */<br>-<br>-#define RCBA_RTC 0x3400 /* 32 bit */<br>-#define RCBA_HPTC 0x3404 /* 32 bit */<br>-#define RCBA_GCS 0x3410 /* 32 bit */<br>-#define RCBA_BUC 0x3414 /* 8 bit */<br>-#define RCBA_FD 0x3418 /* 32 bit */<br>-#define RCBA_PRC 0x341C /* 32 bit */<br>-<br>-static inline int spd_read_byte(u16 device, u8 address)<br>-{<br>- return smbus_read_byte(device, address);<br>-}<br>-<br>-#include <northbridge/intel/i3100/raminit.h><br>-#include "northbridge/intel/i3100/memory_initialized.c"<br>-#include "northbridge/intel/i3100/raminit.c"<br>-#include "lib/generic_sdram.c"<br>-#include "northbridge/intel/i3100/reset_test.c"<br>-#include <spd.h><br>-<br>-#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)<br>-<br>-static void early_config(void)<br>-{<br>- u32 gcs, rpc, fd;<br>-<br>- /* Enable RCBA */<br>- pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);<br>-<br>- /* Disable watchdog */<br>- gcs = read32(DEFAULT_RCBA + RCBA_GCS);<br>- gcs |= (1 << 5); /* No reset */<br>- write32(DEFAULT_RCBA + RCBA_GCS, gcs);<br>-<br>- /* Configure PCIe port B as 4x */<br>- rpc = read32(DEFAULT_RCBA + RCBA_RPC);<br>- rpc |= (3 << 0);<br>- write32(DEFAULT_RCBA + RCBA_RPC, rpc);<br>-<br>- /* Disable Modem, Audio, PCIe ports 2/3/4 */<br>- fd = read32(DEFAULT_RCBA + RCBA_FD);<br>- fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);<br>- write32(DEFAULT_RCBA + RCBA_FD, fd);<br>-<br>- /* Enable HPET */<br>- write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));<br>-<br>- /* Improve interrupt routing<br>- * D31:F2 SATA INTB# -> PIRQD<br>- * D31:F3 SMBUS INTB# -> PIRQD<br>- * D31:F4 CHAP INTD# -> PIRQA<br>- * D29:F0 USB1#1 INTA# -> PIRQH<br>- * D29:F1 USB1#2 INTB# -> PIRQD<br>- * D29:F7 USB2 INTA# -> PIRQH<br>- * D28:F0 PCIe Port 1 INTA# -> PIRQE<br>- */<br>-<br>- write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230);<br>- write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210);<br>- write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237);<br>- write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214);<br>-<br>- /* Setup sata mode */<br>- pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));<br>-}<br>-<br>-void mainboard_romstage_entry(unsigned long bist)<br>-{<br>- /* int boot_mode = 0; */<br>-<br>- static const struct mem_controller mch[] = {<br>- {<br>- .node_id = 0,<br>- .f0 = PCI_DEV(0, 0x00, 0),<br>- .f1 = PCI_DEV(0, 0x00, 1),<br>- .f2 = PCI_DEV(0, 0x00, 2),<br>- .f3 = PCI_DEV(0, 0x00, 3),<br>- .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },<br>- .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },<br>- }<br>- };<br>-<br>- if (bist == 0)<br>- enable_lapic();<br>-<br>- /* Setup the console */<br>- i3100_enable_superio();<br>- i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>- i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);<br>-<br>- console_init();<br>-<br>- /* Halt if there was a built in self test failure */<br>- report_bist_failure(bist);<br>-<br>- /* Perform early board specific init */<br>- early_config();<br>-<br>- /* Prevent the TCO timer from rebooting us */<br>- i3100_halt_tco_timer();<br>-<br>- /* Enable SPD ROMs and DDR-II DRAM */<br>- enable_smbus();<br>-<br>- /* Enable SpeedStep and automatic thermal throttling */<br>- {<br>- msr_t msr;<br>- u16 perf;<br>-<br>- msr = rdmsr(IA32_MISC_ENABLES);<br>- msr.lo |= (1 << 3) | (1 << 16);<br>- wrmsr(IA32_MISC_ENABLES, msr);<br>-<br>- /* Set CPU frequency/voltage to maximum */<br>-<br>- /* Read performance status register and keep<br>- * bits 47:32, where BUS_RATIO_MAX and VID_MAX<br>- * are encoded<br>- */<br>- msr = rdmsr(IA32_PERF_STS);<br>- perf = msr.hi & 0x0000ffff;<br>-<br>- /* Write VID_MAX & BUS_RATIO_MAX to<br>- * performance control register<br>- */<br>- msr = rdmsr(IA32_PERF_CTL);<br>- msr.lo &= 0xffff0000;<br>- msr.lo |= perf;<br>- wrmsr(IA32_PERF_CTL, msr);<br>- }<br>-<br>- /* Initialize memory */<br>- sdram_initialize(ARRAY_SIZE(mch), mch);<br>-}<br>diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig<br>deleted file mode 100644<br>index 11c2626..0000000<br>--- a/src/mainboard/intel/mtarvon/Kconfig<br>+++ /dev/null<br>@@ -1,29 +0,0 @@<br>-if BOARD_INTEL_MTARVON<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_INTEL_SOCKET_MPGA479M<br>- select NORTHBRIDGE_INTEL_I3100<br>- select SOUTHBRIDGE_INTEL_I3100<br>- select SUPERIO_INTEL_I3100<br>- select HAVE_PIRQ_TABLE<br>- select HAVE_MP_TABLE<br>- select BOARD_ROMSIZE_KB_2048<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default intel/mtarvon<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "3100 devkit (Mt. Arvon)"<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 1<br>-<br>-config MAX_CPUS<br>- int<br>- default 4<br>-<br>-endif # BOARD_INTEL_MTARVON<br>diff --git a/src/mainboard/intel/mtarvon/Kconfig.name b/src/mainboard/intel/mtarvon/Kconfig.name<br>deleted file mode 100644<br>index 30b547e..0000000<br>--- a/src/mainboard/intel/mtarvon/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_INTEL_MTARVON<br>- bool "3100 devkit (Mt. Arvon)"<br>diff --git a/src/mainboard/intel/mtarvon/board_info.txt b/src/mainboard/intel/mtarvon/board_info.txt<br>deleted file mode 100644<br>index b351b8e..0000000<br>--- a/src/mainboard/intel/mtarvon/board_info.txt<br>+++ /dev/null<br>@@ -1 +0,0 @@<br>-Category: eval<br>diff --git a/src/mainboard/intel/mtarvon/devicetree.cb b/src/mainboard/intel/mtarvon/devicetree.cb<br>deleted file mode 100644<br>index c1ff1d5..0000000<br>--- a/src/mainboard/intel/mtarvon/devicetree.cb<br>+++ /dev/null<br>@@ -1,45 +0,0 @@<br>-chip northbridge/intel/i3100<br>- device domain 0 on<br>- subsystemid 0x8086 0x2680 inherit<br>- device pci 00.0 on end # IMCH<br>- device pci 00.1 on end # IMCH error status<br>- device pci 01.0 on end # IMCH EDMA engine<br>- device pci 02.0 on end # PCIe port A/A0<br>- device pci 03.0 on end # PCIe port A1<br>- chip southbridge/intel/i3100<br>- # PIRQ line -> legacy IRQ mappings<br>- register "pirq_a_d" = "0x0b070a05"<br>- register "pirq_e_h" = "0x0a808080"<br>-<br>- device pci 1c.0 on end # PCIe port B0<br>- device pci 1c.1 on end # PCIe port B1<br>- device pci 1c.2 on end # PCIe port B2<br>- device pci 1c.3 on end # PCIe port B3<br>- device pci 1d.0 on end # USB (UHCI) 1<br>- device pci 1d.1 on end # USB (UHCI) 2<br>- device pci 1d.7 on end # USB (EHCI)<br>- device pci 1e.0 on end # PCI bridge<br>- device pci 1e.2 on end # audio<br>- device pci 1e.3 on end # modem<br>- device pci 1f.0 on # LPC bridge<br>- chip superio/intel/i3100<br>- device pnp 4e.4 on # Com1<br>- io 0x60 = 0x3f8<br>- irq 0x70 = 4<br>- end<br>- device pnp 4e.5 on # Com2<br>- io 0x60 = 0x2f8<br>- irq 0x70 = 3<br>- end<br>- end<br>- end<br>- device pci 1f.2 on end # SATA<br>- device pci 1f.3 on end # SMBus<br>- end<br>- end<br>- device cpu_cluster 0 on<br>- chip cpu/intel/socket_mPGA479M<br>- device lapic 0 on end<br>- end<br>- end<br>-end<br>diff --git a/src/mainboard/intel/mtarvon/irq_tables.c b/src/mainboard/intel/mtarvon/irq_tables.c<br>deleted file mode 100644<br>index 958b2d3..0000000<br>--- a/src/mainboard/intel/mtarvon/irq_tables.c<br>+++ /dev/null<br>@@ -1,39 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */<br>- 0x00, /* u8 Bus 0 */<br>- (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */<br>- 0x0000, /* u16 reserve IRQ for PCI */<br>- 0x8086, /* u16 Vendor */<br>- 0x2670, /* Device ID */<br>- 0x00000000, /* u32 miniport_data */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0x49, /* u8 checksum - mod 256 checksum must give zero */<br>- { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},<br>- }<br>-};<br>-<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c<br>deleted file mode 100644<br>index ee9d1c2..0000000<br>--- a/src/mainboard/intel/mtarvon/mptable.c<br>+++ /dev/null<br>@@ -1,107 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* This code is based on src/mainboard/intel/jarrell/mptable.c */<br>-<br>-#include <console/console.h><br>-#include <arch/smp/mpspec.h><br>-#include <arch/ioapic.h><br>-#include <device/pci.h><br>-#include <string.h><br>-#include <stdint.h><br>-<br>-static void *smp_write_config_table(void *v)<br>-{<br>- struct mp_config_table *mc;<br>- int bus_isa;<br>- u8 bus_pci = 6;<br>- u8 bus_pcie_a = 1;<br>-<br>- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);<br>-<br>- mptable_init(mc, LOCAL_APIC_ADDR);<br>-<br>- smp_write_processors(mc);<br>-<br>- mptable_write_buses(mc, NULL, &bus_isa);<br>-<br>- /* IOAPIC handling */<br>- smp_write_ioapic(mc, 0x01, 0x20, VIO_APIC_VADDR);<br>-<br>- mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);<br>-<br>- /* Standard local interrupt assignments */<br>- mptable_lintsrc(mc, bus_isa);<br>-<br>- /* Internal PCI devices */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x01 << 2)|0, 0x01, 0x10); /* DMA controller */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x02 << 2)|0, 0x01, 0x10); /* PCIe port A */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x03 << 2)|0, 0x01, 0x10); /* PCIe port A1 */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x1c << 2)|0, 0x01, 0x10); /* PCIe port B0 */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x1c << 2)|1, 0x01, 0x11); /* PCIe port B1 */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x1c << 2)|2, 0x01, 0x12); /* PCIe port B2 */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x1c << 2)|3, 0x01, 0x13); /* PCIe port B3 */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x1d << 2)|0, 0x01, 0x10); /* UHCI0/EHCI */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x1d << 2)|1, 0x01, 0x11); /* UHCI1 */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x1e << 2)|0, 0x01, 0x10); /* Audio */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x1e << 2)|1, 0x01, 0x11); /* Modem */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x1f << 2)|1, 0x01, 0x11); /* SATA/SMBus */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x1f << 2)|3, 0x01, 0x13); /* ? */<br>-<br>- /* PCI slot */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- bus_pci, 0x00, 0x01, 0x10);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- bus_pci, 0x01, 0x01, 0x11);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- bus_pci, 0x02, 0x01, 0x12);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- bus_pci, 0x03, 0x01, 0x13);<br>-<br>- /* PCIe port A slot */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- bus_pcie_a, 0x00, 0x01, 0x10);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- bus_pcie_a, 0x01, 0x01, 0x11);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- bus_pcie_a, 0x02, 0x01, 0x12);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- bus_pcie_a, 0x03, 0x01, 0x13);<br>-<br>- /* There is no extension information... */<br>-<br>- /* Compute the checksums */<br>- return mptable_finalize(mc);<br>-}<br>-<br>-unsigned long write_smp_table(unsigned long addr)<br>-{<br>- void *v;<br>- v = smp_write_floating_table(addr, 0);<br>- return (unsigned long)smp_write_config_table(v);<br>-}<br>diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c<br>deleted file mode 100644<br>index cb3e870..0000000<br>--- a/src/mainboard/intel/mtarvon/romstage.c<br>+++ /dev/null<br>@@ -1,114 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <stdlib.h><br>-#include <device/pci_def.h><br>-#include <device/pci_ids.h><br>-#include <arch/io.h><br>-#include <device/pnp_def.h><br>-#include <cpu/x86/lapic.h><br>-#include <pc80/mc146818rtc.h><br>-#include <console/console.h><br>-#include "southbridge/intel/i3100/early_smbus.c"<br>-#include "southbridge/intel/i3100/early_lpc.c"<br>-#include <northbridge/intel/i3100/raminit.h><br>-#include <superio/intel/i3100/i3100.h><br>-#include "northbridge/intel/i3100/memory_initialized.c"<br>-#include <cpu/x86/bist.h><br>-#include <cpu/intel/romstage.h><br>-#include <spd.h><br>-<br>-#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0)<br>-#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)<br>-<br>-#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)<br>-<br>-static inline int spd_read_byte(u16 device, u8 address)<br>-{<br>- return smbus_read_byte(device, address);<br>-}<br>-<br>-#include "northbridge/intel/i3100/raminit.c"<br>-#include "lib/generic_sdram.c"<br>-#if 0 /* skip_romstage doesn't compile with gcc */<br>-#include "arch/x86/lib/stages.c"<br>-#endif<br>-<br>-void mainboard_romstage_entry(unsigned long bist)<br>-{<br>- msr_t msr;<br>- u16 perf;<br>- static const struct mem_controller mch[] = {<br>- {<br>- .node_id = 0,<br>- .f0 = PCI_DEV(0, 0x00, 0),<br>- .f1 = PCI_DEV(0, 0x00, 1),<br>- .f2 = PCI_DEV(0, 0x00, 2),<br>- .f3 = PCI_DEV(0, 0x00, 3),<br>- .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },<br>- .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },<br>- }<br>- };<br>-<br>- if (bist == 0) {<br>-#if 0 /* skip_romstage doesn't compile with gcc */<br>- /* Skip this if there was a built in self test failure */<br>- if (memory_initialized()) {<br>- skip_romstage();<br>- }<br>-#endif<br>- }<br>-<br>- /* Set up the console */<br>- i3100_enable_superio();<br>- i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>- i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);<br>-<br>- console_init();<br>-<br>- /* Prevent the TCO timer from rebooting us */<br>- i3100_halt_tco_timer();<br>-<br>- /* Halt if there was a built in self test failure */<br>- report_bist_failure(bist);<br>-<br>- /* print_pci_devices(); */<br>- enable_smbus();<br>- /* dump_spd_registers(); */<br>-<br>- /* Enable SpeedStep and automatic thermal throttling */<br>- /* FIXME: move to Pentium M init code */<br>- msr = rdmsr(0x1a0);<br>- msr.lo |= (1 << 3) | (1 << 16);<br>- wrmsr(0x1a0, msr);<br>- msr = rdmsr(0x19d);<br>- msr.lo |= (1 << 16);<br>- wrmsr(0x19d, msr);<br>-<br>- /* Set CPU frequency/voltage to maximum */<br>- /* FIXME: move to Pentium M init code */<br>- msr = rdmsr(0x198);<br>- perf = msr.hi & 0xffff;<br>- msr = rdmsr(0x199);<br>- msr.lo &= 0xffff0000;<br>- msr.lo |= perf;<br>- wrmsr(0x199, msr);<br>-<br>- sdram_initialize(ARRAY_SIZE(mch), mch);<br>- /* dump_pci_devices(); */<br>- /* dump_pci_device(PCI_DEV(0, 0x00, 0)); */<br>- /* dump_bar14(PCI_DEV(0, 0x00, 0)); */<br>-}<br>diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig<br>deleted file mode 100644<br>index cd8e478..0000000<br>--- a/src/mainboard/intel/truxton/Kconfig<br>+++ /dev/null<br>@@ -1,31 +0,0 @@<br>-if BOARD_INTEL_TRUXTON<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_INTEL_EP80579<br>- select NORTHBRIDGE_INTEL_I3100<br>- select SOUTHBRIDGE_INTEL_I3100<br>- select SUPERIO_INTEL_I3100<br>- select SUPERIO_SMSC_SMSCSUPERIO<br>- select HAVE_HARD_RESET<br>- select HAVE_PIRQ_TABLE<br>- select HAVE_MP_TABLE<br>- select BOARD_ROMSIZE_KB_2048<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default intel/truxton<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "Truxton"<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 1<br>-<br>-config MAX_CPUS<br>- int<br>- default 4<br>-<br>-endif # BOARD_INTEL_TRUXTON<br>diff --git a/src/mainboard/intel/truxton/Kconfig.name b/src/mainboard/intel/truxton/Kconfig.name<br>deleted file mode 100644<br>index f91b445..0000000<br>--- a/src/mainboard/intel/truxton/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_INTEL_TRUXTON<br>- bool "EP80579 devkit (Truxton)"<br>diff --git a/src/mainboard/intel/truxton/Makefile.inc b/src/mainboard/intel/truxton/Makefile.inc<br>deleted file mode 100644<br>index 6ef4fc9..0000000<br>--- a/src/mainboard/intel/truxton/Makefile.inc<br>+++ /dev/null<br>@@ -1 +0,0 @@<br>-ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2<br>diff --git a/src/mainboard/intel/truxton/board_info.txt b/src/mainboard/intel/truxton/board_info.txt<br>deleted file mode 100644<br>index 5ae0fde..0000000<br>--- a/src/mainboard/intel/truxton/board_info.txt<br>+++ /dev/null<br>@@ -1,3 +0,0 @@<br>-Board name: EP80579 devkit (Truxton)<br>-Category: eval<br>-Release year: 2009<br>diff --git a/src/mainboard/intel/truxton/devicetree.cb b/src/mainboard/intel/truxton/devicetree.cb<br>deleted file mode 100644<br>index 05fb05e..0000000<br>--- a/src/mainboard/intel/truxton/devicetree.cb<br>+++ /dev/null<br>@@ -1,55 +0,0 @@<br>-chip northbridge/intel/i3100<br>- device domain 0 on<br>- subsystemid 0x8086 0x2680 inherit<br>- device pci 00.0 on end # IMCH<br>- device pci 00.1 on end # IMCH error status<br>- device pci 01.0 on end # IMCH EDMA engine<br>- device pci 02.0 on end # PCIe port A/A0<br>- device pci 03.0 on end # PCIe port A1<br>- device pci 04.0 on end # ?<br>- device pci 08.0 off end # must be off to boot<br>- device pci 0d.0 off end # must be off to boot<br>- device pci 0d.1 off end # must be off to boot<br>- chip southbridge/intel/i3100<br>- # PIRQ line -> legacy IRQ mappings<br>- register "pirq_a_d" = "0x0b070a05"<br>- register "pirq_e_h" = "0x0a808080"<br>-<br>- device pci 1d.0 on end # USB (UHCI)<br>- device pci 1d.7 on end # USB (EHCI)<br>- device pci 1f.0 on # LPC bridge<br>- chip superio/intel/i3100<br>- device pnp 4e.4 on # Com1<br>- io 0x60 = 0x3f8<br>- irq 0x70 = 4<br>- end<br>- device pnp 4e.5 on # Com2<br>- io 0x60 = 0x2f8<br>- irq 0x70 = 3<br>- end<br>- end<br>- chip superio/smsc/smscsuperio<br>- device pnp 2e.0 off end<br>- device pnp 2e.3 off end<br>- device pnp 2e.4 off end<br>- device pnp 2e.5 off end<br>- device pnp 2e.7 on # PS/2 keyboard / mouse<br>- io 0x60 = 0x60<br>- io 0x62 = 0x64<br>- irq 0x70 = 1 # PS/2 keyboard interrupt<br>- irq 0x72 = 12 # PS/2 mouse interrupt<br>- end<br>- device pnp 2e.a off end<br>- end<br>- end<br>- device pci 1f.2 on end # SATA<br>- device pci 1f.3 on end # SMBus<br>- device pci 1f.4 on end # ?<br>- end<br>- end<br>- device cpu_cluster 0 on<br>- chip cpu/intel/ep80579<br>- device lapic 0 on end<br>- end<br>- end<br>-end<br>diff --git a/src/mainboard/intel/truxton/irq_tables.c b/src/mainboard/intel/truxton/irq_tables.c<br>deleted file mode 100644<br>index c34809f..0000000<br>--- a/src/mainboard/intel/truxton/irq_tables.c<br>+++ /dev/null<br>@@ -1,39 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */<br>- 0x00, /* u8 Bus 0 */<br>- (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */<br>- 0x0000, /* u16 reserve IRQ for PCI */<br>- 0x8086, /* u16 Vendor */<br>- 0x5031, /* Device ID */<br>- 0x00000000, /* u32 miniport_data */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0x5e, /* u8 checksum - mod 256 checksum must give zero */<br>- { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},<br>- }<br>-};<br>-<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c<br>deleted file mode 100644<br>index ca934b3..0000000<br>--- a/src/mainboard/intel/truxton/mptable.c<br>+++ /dev/null<br>@@ -1,135 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <arch/smp/mpspec.h><br>-#include <arch/ioapic.h><br>-#include <device/pci.h><br>-#include <string.h><br>-#include <stdint.h><br>-<br>-static void *smp_write_config_table(void *v)<br>-{<br>- struct mp_config_table *mc;<br>- int bus_isa;<br>- u8 bus_pea0 = 0;<br>- u8 bus_pea1 = 0;<br>- u8 bus_aioc;<br>- device_t dev;<br>-<br>- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);<br>-<br>- mptable_init(mc, LOCAL_APIC_ADDR);<br>-<br>- smp_write_processors(mc);<br>-<br>- /* AIOC bridge */<br>- dev = dev_find_slot(0, PCI_DEVFN(0x04,0));<br>- if (dev) {<br>- bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);<br>- }<br>- else {<br>- printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");<br>- bus_aioc = 0;<br>- }<br>- /* PCIe A0 */<br>- dev = dev_find_slot(0, PCI_DEVFN(0x02,0));<br>- if (dev) {<br>- bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);<br>- }<br>- else {<br>- printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n");<br>- bus_pea0 = 0;<br>- }<br>- /* PCIe A1 */<br>- dev = dev_find_slot(0, PCI_DEVFN(0x03,0));<br>- if (dev) {<br>- bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);<br>- }<br>- else {<br>- printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n");<br>- bus_pea1 = 0;<br>- }<br>-<br>- mptable_write_buses(mc, NULL, &bus_isa);<br>-<br>- /* IOAPIC handling */<br>- smp_write_ioapic(mc, 0x8, 0x20, VIO_APIC_VADDR);<br>-<br>- mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);<br>-<br>- /* Standard local interrupt assignments */<br>- mptable_lintsrc(mc, bus_isa);<br>-<br>- /* IMCH/IICH PCI devices */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x01 << 2)|0, 0x8, 0x10); /* DMA controller */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x02 << 2)|0, 0x8, 0x10); /* PCIe port A bridge */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x03 << 2)|0, 0x8, 0x10); /* PCIe port A1 bridge */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x04 << 2)|0, 0x8, 0x10); /* AIOC PCI bridge */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x1d << 2)|0, 0x8, 0x10); /* UHCI/EHCI */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,<br>- 0, (0x1f << 2)|1, 0x8, 0x11); /* SATA/SMBus */<br>-<br>- if (bus_pea0) {<br>- /* PCIe slot 0 */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,<br>- bus_pea0, (0 << 2)|0, 0x8, 0x10);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,<br>- bus_pea0, (0 << 2)|1, 0x8, 0x11);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,<br>- bus_pea0, (0 << 2)|2, 0x8, 0x12);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,<br>- bus_pea0, (0 << 2)|3, 0x8, 0x13);<br>- }<br>-<br>- if (bus_pea1) {<br>- /* PCIe slots 1-4 */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,<br>- bus_pea1, (0 << 2)|0, 0x8, 0x10);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,<br>- bus_pea1, (0 << 2)|1, 0x8, 0x11);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,<br>- bus_pea1, (0 << 2)|2, 0x8, 0x12);<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,<br>- bus_pea1, (0 << 2)|3, 0x8, 0x13);<br>- }<br>-<br>- if (bus_aioc) {<br>- /* AIOC PCI devices */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,<br>- bus_aioc, (0 << 2)|0, 0x8, 0x10); /* GbE0 */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,<br>- bus_aioc, (1 << 2)|0, 0x8, 0x11); /* GbE1 */<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,<br>- bus_aioc, (2 << 2)|0, 0x8, 0x12); /* GbE2 */<br>- }<br>-<br>- /* There is no extension information... */<br>-<br>- /* Compute the checksums */<br>- return mptable_finalize(mc);<br>-}<br>-<br>-unsigned long write_smp_table(unsigned long addr)<br>-{<br>- void *v;<br>- v = smp_write_floating_table(addr, 0);<br>- return (unsigned long)smp_write_config_table(v);<br>-}<br>diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c<br>deleted file mode 100644<br>index 4b64210..0000000<br>--- a/src/mainboard/intel/truxton/romstage.c<br>+++ /dev/null<br>@@ -1,86 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <stdlib.h><br>-#include <device/pci_def.h><br>-#include <device/pci_ids.h><br>-#include <arch/io.h><br>-#include <device/pnp_def.h><br>-#include <cpu/x86/lapic.h><br>-#include <pc80/mc146818rtc.h><br>-#include <console/console.h><br>-#include "southbridge/intel/i3100/early_smbus.c"<br>-#include "southbridge/intel/i3100/early_lpc.c"<br>-#include <northbridge/intel/i3100/raminit_ep80579.h><br>-#include <superio/intel/i3100/i3100.h><br>-#include "lib/debug.c" // XXX<br>-#include <cpu/x86/bist.h><br>-#include <cpu/intel/romstage.h><br>-#include <spd.h><br>-<br>-#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)<br>-<br>-static inline int spd_read_byte(u16 device, u8 address)<br>-{<br>- return smbus_read_byte(device, address);<br>-}<br>-<br>-#include "northbridge/intel/i3100/raminit_ep80579.c"<br>-#include "lib/generic_sdram.c"<br>-<br>-#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)<br>-<br>-void mainboard_romstage_entry(unsigned long bist)<br>-{<br>- static const struct mem_controller mch[] = {<br>- {<br>- .node_id = 0,<br>- .f0 = PCI_DEV(0, 0x00, 0),<br>- .channel0 = { DIMM2, DIMM3 },<br>- }<br>- };<br>-<br>- if (bist == 0) {<br>- /* Skip this if there was a built in self test failure */<br>- if (memory_initialized())<br>- return;<br>- }<br>-<br>- /* Set up the console */<br>- i3100_enable_superio();<br>- i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>- i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);<br>-<br>- console_init();<br>-<br>- /* Prevent the TCO timer from rebooting us */<br>- i3100_halt_tco_timer();<br>-<br>- /* Halt if there was a built in self test failure */<br>- report_bist_failure(bist);<br>-<br>-#ifdef TRUXTON_DEBUG<br>- print_pci_devices();<br>-#endif<br>- enable_smbus();<br>-<br>- sdram_initialize(ARRAY_SIZE(mch), mch);<br>- dump_pci_devices();<br>- dump_pci_device(PCI_DEV(0, 0x00, 0));<br>-#ifdef TRUXTON_DEBUG<br>- dump_bar14(PCI_DEV(0, 0x00, 0));<br>-#endif<br>-}<br>diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig<br>deleted file mode 100644<br>index 7d4f4e5..0000000<br>--- a/src/northbridge/intel/i3100/Kconfig<br>+++ /dev/null<br>@@ -1,12 +0,0 @@<br>-config NORTHBRIDGE_INTEL_I3100<br>- bool<br>- select NO_MMCONF_SUPPORT<br>- select LATE_CBMEM_INIT<br>- select UDELAY_IO<br>-<br>-if NORTHBRIDGE_INTEL_I3100<br>-config DIMM_MAP_LOGICAL<br>- hex<br>- default 0x1248<br>-<br>-endif<br>diff --git a/src/northbridge/intel/i3100/Makefile.inc b/src/northbridge/intel/i3100/Makefile.inc<br>deleted file mode 100644<br>index 16291bf..0000000<br>--- a/src/northbridge/intel/i3100/Makefile.inc<br>+++ /dev/null<br>@@ -1,7 +0,0 @@<br>-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I3100),y)<br>-<br>-ramstage-y += northbridge.c<br>-ramstage-y += pciexp_porta.c<br>-ramstage-y += pciexp_porta_ep80579.c<br>-<br>-endif<br>diff --git a/src/northbridge/intel/i3100/chip.h b/src/northbridge/intel/i3100/chip.h<br>deleted file mode 100644<br>index 5da7431..0000000<br>--- a/src/northbridge/intel/i3100/chip.h<br>+++ /dev/null<br>@@ -1,25 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef NORTHBRIDGE_INTEL_I3100_CHIP_H<br>-#define NORTHBRIDGE_INTEL_I3100_CHIP_H<br>-<br>-struct northbridge_intel_i3100_config<br>-{<br>- /* Interrupt line connect */<br>- u16 intrline;<br>-};<br>-<br>-#endif /* NORTHBRIDGE_INTEL_I3100_CHIP_H */<br>diff --git a/src/northbridge/intel/i3100/ep80579.h b/src/northbridge/intel/i3100/ep80579.h<br>deleted file mode 100644<br>index 60c319f..0000000<br>--- a/src/northbridge/intel/i3100/ep80579.h<br>+++ /dev/null<br>@@ -1,59 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef NORTHBRIDGE_INTEL_I3100_EP80579_H<br>-#define NORTHBRIDGE_INTEL_I3100_EP80579_H<br>-<br>-#define SMRBASE 0x14<br>-#define MCHCFG0 0x50<br>-#define FDHC 0x58<br>-#define PAM 0x59<br>-#define DRB 0x60<br>-#define DRT1 0x64<br>-#define DRA 0x70<br>-#define DRT0 0x78<br>-#define DRC 0x7c<br>-#define ECCDIAG 0x84<br>-#define SDRC 0x88<br>-#define CKDIS 0x8c<br>-#define CKEDIS 0x8d<br>-#define DEVPRES 0x9c<br>-#define DEVPRES_D0F0 (1 << 0)<br>-#define DEVPRES_D1F0 (1 << 1)<br>-#define DEVPRES_D2F0 (1 << 2)<br>-#define DEVPRES_D3F0 (1 << 3)<br>-#define DEVPRES_D4F0 (1 << 4)<br>-#define DEVPRES_D10F0 (1 << 5)<br>-#define EXSMRC 0x9d<br>-#define SMRAM 0x9e<br>-#define EXSMRAMC 0x9f<br>-#define DDR2ODTC 0xb0<br>-#define TOLM 0xc4<br>-#define REMAPBASE 0xc6<br>-#define REMAPLIMIT 0xc8<br>-#define REMAPOFFSET 0xca<br>-#define TOM 0xcc<br>-#define HECBASE 0xce<br>-#define DEVPRES1 0xf4<br>-<br>-#define DCALCSR 0x040<br>-#define DCALADDR 0x044<br>-#define DCALDATA 0x048<br>-#define MBCSR 0x140<br>-#define MBADDR 0x144<br>-#define MBDATA 0x148<br>-#define DDRIOMC2 0x268<br>-<br>-#endif<br>diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h<br>deleted file mode 100644<br>index b501e0b..0000000<br>--- a/src/northbridge/intel/i3100/i3100.h<br>+++ /dev/null<br>@@ -1,68 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef __I3100_H__<br>-#define __I3100_H__<br>-<br>-#define IURBASE 0X14<br>-#define MCHCFG0 0X50<br>-#define MCHSCRB 0X52<br>-#define FDHC 0X58<br>-#define PAM 0X59<br>-#define DRB 0X60<br>-#define DRA 0X70<br>-#define DRT 0X78<br>-#define DRC 0X7C<br>-#define DRM 0X80<br>-#define DRORC 0X82<br>-#define ECCDIAG 0X84<br>-#define SDRC 0X88<br>-#define CKDIS 0X8C<br>-#define CKEDIS 0X8D<br>-#define DDRCSR 0X9A<br>-#define DEVPRES 0X9C<br>-#define DEVPRES_D0F0 (1 << 0)<br>-#define DEVPRES_D1F0 (1 << 1)<br>-#define DEVPRES_D2F0 (1 << 2)<br>-#define DEVPRES_D3F0 (1 << 3)<br>-#define DEVPRES_D4F0 (1 << 4)<br>-#define DEVPRES_D5F0 (1 << 5)<br>-#define DEVPRES_D6F0 (1 << 6)<br>-#define DEVPRES_D7F0 (1 << 7)<br>-#define ESMRC 0X9D<br>-#define SMRC 0X9E<br>-#define EXSMRC 0X9F<br>-#define DDR2ODTC 0XB0<br>-#define TOLM 0XC4<br>-#define REMAPBASE 0XC6<br>-#define REMAPLIMIT 0XC8<br>-#define REMAPOFFSET 0XCA<br>-#define TOM 0XCC<br>-#define EXPECBASE 0XCE<br>-#define DEVPRES1 0XF4<br>-#define DEVPRES1_D0F1 (1 << 5)<br>-#define DEVPRES1_D8F0 (1 << 1)<br>-#define MSCFG 0XF6<br>-<br>-/* DRC */<br>-#define DRC_NOECC_MODE (0 << 20)<br>-#define DRC_72BIT_ECC (1 << 20)<br>-<br>-#define RCBA 0xF0<br>-#define DEFAULT_RCBA ((u8 *)0xFEA00000)<br>-<br>-int bios_reset_detected(void);<br>-<br>-#endif<br>diff --git a/src/northbridge/intel/i3100/memory_initialized.c b/src/northbridge/intel/i3100/memory_initialized.c<br>deleted file mode 100644<br>index 6af7b9b..0000000<br>--- a/src/northbridge/intel/i3100/memory_initialized.c<br>+++ /dev/null<br>@@ -1,24 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include "i3100.h"<br>-#define NB_DEV PCI_DEV(0, 0, 0)<br>-<br>-static inline int memory_initialized(void)<br>-{<br>- u32 drc;<br>- drc = pci_read_config32(NB_DEV, DRC);<br>- return (drc & (1<<29));<br>-}<br>diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c<br>deleted file mode 100644<br>index f05eea0..0000000<br>--- a/src/northbridge/intel/i3100/northbridge.c<br>+++ /dev/null<br>@@ -1,220 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-/* This code is based on src/northbridge/intel/e7520/northbridge.c */<br>-<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include <cbmem.h><br>-#include <cpu/cpu.h><br>-#include "chip.h"<br>-#include "i3100.h"<br>-#include <arch/acpi.h><br>-<br>-<br>-static void pci_domain_set_resources(device_t dev)<br>-{<br>- device_t mc_dev;<br>- u32 pci_tolm;<br>-<br>- pci_tolm = find_pci_tolm(dev->link_list);<br>-<br>-#if 1<br>- printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);<br>-#endif<br>- /* FIXME Me temporary hack */<br>- if (pci_tolm > 0xe0000000)<br>- pci_tolm = 0xe0000000;<br>- /* Ensure pci_tolm is 128M aligned */<br>- pci_tolm &= 0xf8000000;<br>- mc_dev = dev->link_list->children;<br>- if (mc_dev) {<br>- /* Figure out which areas are/should be occupied by RAM.<br>- * This is all computed in kilobytes and converted to/from<br>- * the memory controller right at the edges.<br>- * Having different variables in different units is<br>- * too confusing to get right. Kilobytes are good up to<br>- * 4 Terabytes of RAM...<br>- */<br>- u16 tolm_r, remapbase_r, remaplimit_r, remapoffset_r;<br>- u32 tomk, tolmk;<br>- u32 remapbasek, remaplimitk, remapoffsetk;<br>-<br>- /* Get the Top of Memory address, units are 128M */<br>- tomk = ((u32)pci_read_config16(mc_dev, TOM)) << 17;<br>- /* Compute the Top of Low Memory */<br>- tolmk = (pci_tolm & 0xf8000000) >> 10;<br>-<br>- if (tolmk >= tomk) {<br>- /* The PCI hole does not overlap memory<br>- * we won't use the remap window.<br>- */<br>- tolmk = tomk;<br>- remapbasek = 0x3ff << 16;<br>- remaplimitk = 0 << 16;<br>- remapoffsetk = 0 << 16;<br>- }<br>- else {<br>- /* The PCI memory hole overlaps memory<br>- * setup the remap window.<br>- */<br>- /* Find the bottom of the remap window<br>- * is it above 4G?<br>- */<br>- remapbasek = 4*1024*1024;<br>- if (tomk > remapbasek) {<br>- remapbasek = tomk;<br>- }<br>- /* Find the limit of the remap window */<br>- remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));<br>- /* Find the offset of the remap window from tolm */<br>- remapoffsetk = remapbasek - tolmk;<br>- }<br>- /* Write the RAM configuration registers,<br>- * preserving the reserved bits.<br>- */<br>- tolm_r = pci_read_config16(mc_dev, 0xc4);<br>- tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);<br>- pci_write_config16(mc_dev, 0xc4, tolm_r);<br>-<br>- remapbase_r = pci_read_config16(mc_dev, 0xc6);<br>- remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);<br>- pci_write_config16(mc_dev, 0xc6, remapbase_r);<br>-<br>- remaplimit_r = pci_read_config16(mc_dev, 0xc8);<br>- remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);<br>- pci_write_config16(mc_dev, 0xc8, remaplimit_r);<br>-<br>- remapoffset_r = pci_read_config16(mc_dev, 0xca);<br>- remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);<br>- pci_write_config16(mc_dev, 0xca, remapoffset_r);<br>-<br>- /* Report the memory regions */<br>- ram_resource(dev, 3, 0, 640);<br>- ram_resource(dev, 4, 768, (tolmk - 768));<br>- if (tomk > 4*1024*1024) {<br>- ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);<br>- }<br>- if (remaplimitk >= remapbasek) {<br>- ram_resource(dev, 6, remapbasek,<br>- (remaplimitk + 64*1024) - remapbasek);<br>- }<br>-<br>- set_late_cbmem_top(tolmk * 1024);<br>- }<br>- assign_resources(dev->link_list);<br>-}<br>-<br>-static struct device_operations pci_domain_ops = {<br>- .read_resources = pci_domain_read_resources,<br>- .set_resources = pci_domain_set_resources,<br>- .enable_resources = NULL,<br>- .init = NULL,<br>- .scan_bus = pci_domain_scan_bus,<br>- .ops_pci_bus = pci_bus_default_ops,<br>-};<br>-<br>-static void mc_read_resources(device_t dev)<br>-{<br>- pci_dev_read_resources(dev);<br>-<br>- mmconf_resource(dev, EXPECBASE);<br>-}<br>-<br>-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>-}<br>-<br>-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)<br>-<br>-unsigned long acpi_fill_mcfg(unsigned long current)<br>-{<br>- device_t dev;<br>- u64 mmcfg;<br>-<br>- dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_MC, 0); // 0:0x13.0<br>- if (!dev)<br>- return current;<br>-<br>- // MMCFG not supported or not enabled.<br>- mmcfg = ((u64) pci_read_config16(dev, 0xce)) << 16;<br>- if (!mmcfg)<br>- return current;<br>-<br>- current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,<br>- mmcfg, 0x0, 0x0, 0xff);<br>-<br>- return current;<br>-}<br>-<br>-#endif<br>-<br>-static struct pci_operations intel_pci_ops = {<br>- .set_subsystem = intel_set_subsystem,<br>-};<br>-<br>-static struct device_operations mc_ops = {<br>- .read_resources = mc_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = 0,<br>- .scan_bus = 0,<br>- .ops_pci = &intel_pci_ops,<br>-};<br>-<br>-static const struct pci_driver mc_driver __pci_driver = {<br>- .ops = &mc_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_MC,<br>-};<br>-<br>-static void cpu_bus_init(device_t dev)<br>-{<br>- initialize_cpus(dev->link_list);<br>-}<br>-<br>-static struct device_operations cpu_bus_ops = {<br>- .read_resources = DEVICE_NOOP,<br>- .set_resources = DEVICE_NOOP,<br>- .enable_resources = DEVICE_NOOP,<br>- .init = cpu_bus_init,<br>- .scan_bus = 0,<br>-};<br>-<br>-<br>-static void enable_dev(device_t dev)<br>-{<br>- /* Set the operations if it is a special bus type */<br>- if (dev->path.type == DEVICE_PATH_DOMAIN) {<br>- dev->ops = &pci_domain_ops;<br>- }<br>- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {<br>- dev->ops = &cpu_bus_ops;<br>- }<br>-}<br>-<br>-struct chip_operations northbridge_intel_i3100_ops = {<br>- CHIP_NAME("Intel 3100 Northbridge")<br>- .enable_dev = enable_dev,<br>-};<br>diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c<br>deleted file mode 100644<br>index 3f4939c..0000000<br>--- a/src/northbridge/intel/i3100/pciexp_porta.c<br>+++ /dev/null<br>@@ -1,85 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <device/pciexp.h><br>-#include <arch/io.h><br>-#include "chip.h"<br>-#include <reset.h><br>-<br>-typedef struct northbridge_intel_i3100_config config_t;<br>-<br>-static void pcie_init(struct device *dev)<br>-{<br>- config_t *config;<br>-<br>- /* Get the chip configuration */<br>- config = dev->chip_info;<br>-<br>- if (config->intrline) {<br>- pci_write_config32(dev, 0x3c, config->intrline);<br>- }<br>-<br>-}<br>-<br>-static void pcie_scan_bridge(struct device *dev)<br>-{<br>- u16 val;<br>- u16 ctl;<br>- int flag = 0;<br>- do {<br>- val = pci_read_config16(dev, 0x76);<br>- printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);<br>- if ((val & (1<<10)) && (!flag)) { /* training error */<br>- ctl = pci_read_config16(dev, 0x74);<br>- pci_write_config16(dev, 0x74, (ctl | (1<<5)));<br>- val = pci_read_config16(dev, 0x76);<br>- printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);<br>- flag = 1;<br>- hard_reset();<br>- }<br>- } while (val & (3<<10));<br>-<br>- pciexp_scan_bridge(dev);<br>-}<br>-<br>-static struct device_operations pcie_ops = {<br>- .read_resources = pci_bus_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_bus_enable_resources,<br>- .init = pcie_init,<br>- .scan_bus = pcie_scan_bridge,<br>- .reset_bus = pci_bus_reset,<br>- .ops_pci = 0,<br>-};<br>-<br>-static const struct pci_driver pci_driver_0 __pci_driver = {<br>- .ops = &pcie_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA0,<br>-};<br>-<br>-static const struct pci_driver pci_driver_1 __pci_driver = {<br>- .ops = &pcie_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA1,<br>-};<br>diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c<br>deleted file mode 100644<br>index 62f485d..0000000<br>--- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c<br>+++ /dev/null<br>@@ -1,107 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009 4DSP Inc<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-/* This code is based on src/northbridge/intel/i3100/pciexp_porta.c */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <device/pciexp.h><br>-#include <arch/io.h><br>-#include "chip.h"<br>-#include <reset.h><br>-<br>-typedef struct northbridge_intel_i3100_config config_t;<br>-<br>-static void pcie_init(struct device *dev)<br>-{<br>- config_t *config;<br>- u16 val;<br>-<br>- /* Get the chip configuration */<br>- config = dev->chip_info;<br>-<br>- if (config->intrline) {<br>- pci_write_config32(dev, 0x3c, config->intrline);<br>- }<br>-<br>- printk(BIOS_SPEW, "configure PCIe port as \"Slot Implemented\"\n");<br>- val = pci_read_config16(dev, 0x66);<br>- val &= ~(1<<8);<br>- val |= 1<<8;<br>- pci_write_config16(dev, 0x66, val);<br>-<br>- /* Todo configure the PCIe bootstrap mode (covered by Intel NDA) */<br>-}<br>-<br>-<br>-static void pcie_bus_enable_resources(struct device *dev)<br>-{<br>- if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>- printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n");<br>- pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8);<br>-<br>- dev->command |= PCI_COMMAND_IO;<br>- dev->command |= PCI_COMMAND_MEMORY;<br>- }<br>- pci_dev_enable_resources(dev);<br>-}<br>-<br>-<br>-static void pcie_scan_bridge(struct device *dev)<br>-{<br>- u16 val;<br>- u16 ctl;<br>- int flag = 0;<br>- do {<br>- val = pci_read_config16(dev, 0x76);<br>- printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);<br>- if ((val & (1<<11)) && (!flag)) { /* training error */<br>- ctl = pci_read_config16(dev, 0x74);<br>- pci_write_config16(dev, 0x74, (ctl | (1<<5)));<br>- val = pci_read_config16(dev, 0x76);<br>- printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);<br>- flag = 1;<br>- hard_reset();<br>- }<br>- } while (val & (3<<10));<br>-<br>- pciexp_scan_bridge(dev);<br>-}<br>-<br>-static struct device_operations pcie_ops = {<br>- .read_resources = pci_bus_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pcie_bus_enable_resources,<br>- .init = pcie_init,<br>- .scan_bus = pcie_scan_bridge,<br>- .reset_bus = pci_bus_reset,<br>- .ops_pci = 0,<br>-};<br>-<br>-static const struct pci_driver pci_driver_0 __pci_driver = {<br>- .ops = &pcie_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0,<br>-};<br>-<br>-static const struct pci_driver pci_driver_1 __pci_driver = {<br>- .ops = &pcie_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1,<br>-};<br>diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c<br>deleted file mode 100644<br>index aebe4e8..0000000<br>--- a/src/northbridge/intel/i3100/raminit.c<br>+++ /dev/null<br>@@ -1,1201 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-#include <cpu/x86/mtrr.h><br>-#include <cpu/x86/cache.h><br>-#include <cpu/intel/speedstep.h><br>-#include <lib.h><br>-#include <stdlib.h><br>-#include "raminit.h"<br>-#include "i3100.h"<br>-<br>-/* DDR2 memory controller register space */<br>-#define MCBAR ((u8 *)(0x90000000))<br>-<br>-static void sdram_set_registers(const struct mem_controller *ctrl)<br>-{<br>- static const u32 register_values[] = {<br>-<br>- /* CKDIS 0x8c disable clocks */<br>- PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,<br>-<br>- /* 0x9c Device present and extended RAM control<br>- * DEVPRES is very touchy, hard code the initialization<br>- * of PCI-E ports here.<br>- */<br>- PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,<br>-<br>- /* 0xc8 Remap RAM base and limit off */<br>- PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,<br>-<br>- /* ??? */<br>- PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000,<br>- PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a,<br>-<br>- /* 0x50 scrub */<br>- PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */<br>-<br>- /* 0x58 0x5c PAM */<br>- PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,<br>- PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,<br>-<br>- /* 0xf4 */<br>- PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,<br>-<br>- /* 0x14 */<br>- PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, (uintptr_t)(MCBAR + 0),<br>- };<br>- int i;<br>- int max;<br>-<br>- max = ARRAY_SIZE(register_values);<br>- for (i = 0; i < max; i += 3) {<br>- device_t dev;<br>- u32 where;<br>- u32 reg;<br>- dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;<br>- where = register_values[i] & 0xff;<br>- reg = pci_read_config32(dev, where);<br>- reg &= register_values[i+1];<br>- reg |= register_values[i+2];<br>- pci_write_config32(dev, where, reg);<br>- }<br>- printk(BIOS_SPEW, "done.\n");<br>-}<br>-<br>-struct dimm_size {<br>- u32 side1;<br>- u32 side2;<br>-};<br>-<br>-static struct dimm_size spd_get_dimm_size(u16 device)<br>-{<br>- /* Calculate the log base 2 size of a DIMM in bits */<br>- struct dimm_size sz;<br>- int value, low;<br>- sz.side1 = 0;<br>- sz.side2 = 0;<br>-<br>- /* Note it might be easier to use byte 31 here, it has the DIMM size as<br>- * a multiple of 4MB. The way we do it now we can size both<br>- * sides of an asymmetric dimm.<br>- */<br>- value = spd_read_byte(device, 3); /* rows */<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xf) == 0) goto val_err;<br>- sz.side1 += value & 0xf;<br>-<br>- value = spd_read_byte(device, 4); /* columns */<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xf) == 0) goto val_err;<br>- sz.side1 += value & 0xf;<br>-<br>- value = spd_read_byte(device, 17); /* banks */<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xff) == 0) goto val_err;<br>- sz.side1 += log2(value & 0xff);<br>-<br>- /* Get the module data width and convert it to a power of two */<br>- value = spd_read_byte(device, 7); /* (high byte) */<br>- if (value < 0) goto hw_err;<br>- value &= 0xff;<br>- value <<= 8;<br>-<br>- low = spd_read_byte(device, 6); /* (low byte) */<br>- if (low < 0) goto hw_err;<br>- value = value | (low & 0xff);<br>- if ((value != 72) && (value != 64)) goto val_err;<br>- sz.side1 += log2(value);<br>-<br>- /* side 2 */<br>- value = spd_read_byte(device, 5); /* number of physical banks */<br>-<br>- if (value < 0) goto hw_err;<br>- value &= 7;<br>- value++;<br>- if (value == 1) goto out;<br>- if (value != 2) goto val_err;<br>-<br>- /* Start with the symmetrical case */<br>- sz.side2 = sz.side1;<br>-<br>- value = spd_read_byte(device, 3); /* rows */<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */<br>- sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */<br>- sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */<br>-<br>- value = spd_read_byte(device, 4); /* columns */<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xff) == 0) goto val_err;<br>- sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */<br>- sz.side2 += ((value >> 4) & 0x0f); /* Add in columns on side 2 */<br>- goto out;<br>-<br>- val_err:<br>- die("Bad SPD value\n");<br>- /* If an hw_error occurs report that I have no memory */<br>- hw_err:<br>- sz.side1 = 0;<br>- sz.side2 = 0;<br>-out:<br>- return sz;<br>-<br>-}<br>-<br>-static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)<br>-{<br>- int i;<br>- int cum;<br>-<br>- for (i = cum = 0; i < DIMM_SOCKETS; i++) {<br>- struct dimm_size sz;<br>- if (dimm_mask & (1 << i)) {<br>- sz = spd_get_dimm_size(ctrl->channel0[i]);<br>- if (sz.side1 < 29) {<br>- return -1; /* Report SPD error */<br>- }<br>- /* convert bits to multiples of 64MB */<br>- sz.side1 -= 29;<br>- cum += (1 << sz.side1);<br>- /* DRB = 0x60 */<br>- pci_write_config8(ctrl->f0, DRB + (i*2), cum);<br>- if ( sz.side2 > 28) {<br>- sz.side2 -= 29;<br>- cum += (1 << sz.side2);<br>- }<br>- pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);<br>- }<br>- else {<br>- pci_write_config8(ctrl->f0, DRB + (i*2), cum);<br>- pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);<br>- }<br>- }<br>- cum >>= 1;<br>- /* set TOM top of memory 0xcc */<br>- pci_write_config16(ctrl->f0, TOM, cum);<br>- /* set TOLM top of low memory */<br>- if (cum > 0x18) {<br>- cum = 0x18;<br>- }<br>- cum <<= 11;<br>- /* 0xc4 TOLM */<br>- pci_write_config16(ctrl->f0, TOLM, cum);<br>- return 0;<br>-}<br>-<br>-<br>-static u32 spd_detect_dimms(const struct mem_controller *ctrl)<br>-{<br>- u32 dimm_mask;<br>- int i;<br>- dimm_mask = 0;<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- int byte;<br>- u16 device;<br>- device = ctrl->channel0[i];<br>- if (device) {<br>- byte = spd_read_byte(device, 2); /* Type */<br>- if (byte == 8) {<br>- dimm_mask |= (1 << i);<br>- }<br>- }<br>- device = ctrl->channel1[i];<br>- if (device) {<br>- byte = spd_read_byte(device, 2);<br>- if (byte == 8) {<br>- dimm_mask |= (1 << (i + DIMM_SOCKETS));<br>- }<br>- }<br>- }<br>- return dimm_mask;<br>-}<br>-<br>-<br>-static int spd_set_row_attributes(const struct mem_controller *ctrl,<br>- long dimm_mask)<br>-{<br>- int value;<br>- int reg;<br>- int dra;<br>- int cnt;<br>-<br>- dra = 0;<br>- for (cnt = 0; cnt < 4; cnt++) {<br>- if (!(dimm_mask & (1 << cnt))) {<br>- continue;<br>- }<br>- reg =0;<br>- value = spd_read_byte(ctrl->channel0[cnt], 3); /* rows */<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xf) == 0) goto val_err;<br>- reg += value & 0xf;<br>-<br>- value = spd_read_byte(ctrl->channel0[cnt], 4); /* columns */<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xf) == 0) goto val_err;<br>- reg += value & 0xf;<br>-<br>- value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xff) == 0) goto val_err;<br>- reg += log2(value & 0xff);<br>-<br>- /* Get the device width and convert it to a power of two */<br>- value = spd_read_byte(ctrl->channel0[cnt], 13);<br>- if (value < 0) goto hw_err;<br>- value = log2(value & 0xff);<br>- reg += value;<br>- if (reg < 27) goto hw_err;<br>- reg -= 27;<br>- reg += (value << 2);<br>-<br>- dra += reg << (cnt*8);<br>- value = spd_read_byte(ctrl->channel0[cnt], 5);<br>- if (value & 2)<br>- dra += reg << ((cnt*8)+4);<br>- }<br>-<br>- /* 0x70 DRA */<br>- pci_write_config32(ctrl->f0, DRA, dra);<br>- goto out;<br>-<br>- val_err:<br>- die("Bad SPD value\n");<br>- /* If an hw_error occurs report that I have no memory */<br>- hw_err:<br>- dra = 0;<br>-out:<br>- return dra;<br>-<br>-}<br>-<br>-<br>-static int spd_set_drt_attributes(const struct mem_controller *ctrl,<br>- long dimm_mask, u32 drc)<br>-{<br>- int value;<br>- int reg;<br>- u32 drt;<br>- int cnt;<br>- int first_dimm;<br>- int cas_latency = 0;<br>- int latency;<br>- u32 index = 0;<br>- u32 index2 = 0;<br>- static const u8 cycle_time[3] = { 0x75, 0x60, 0x50 };<br>- static const u8 latency_indicies[] = { 26, 23, 9 };<br>-<br>- /* 0x78 DRT */<br>- drt = pci_read_config32(ctrl->f0, DRT);<br>- drt &= 3; /* save bits 1:0 */<br>-<br>- for (first_dimm = 0; first_dimm < 4; first_dimm++) {<br>- if (dimm_mask & (1 << first_dimm))<br>- break;<br>- }<br>-<br>- drt |= (1<<6); /* back to back write turn around */<br>-<br>- drt |= (3<<18); /* Trasmax */<br>-<br>- for (cnt = 0; cnt < 4; cnt++) {<br>- if (!(dimm_mask & (1 << cnt))) {<br>- continue;<br>- }<br>- reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */<br>- /* Compute the lowest cas latency supported */<br>- latency = log2(reg) -2;<br>-<br>- /* Loop through and find a fast clock with a low latency */<br>- for (index = 0; index < 3; index++, latency++) {<br>- if ((latency < 2) || (latency > 4) ||<br>- (!(reg & (1 << latency)))) {<br>- continue;<br>- }<br>- value = spd_read_byte(ctrl->channel0[cnt],<br>- latency_indicies[index]);<br>-<br>- if (value <= cycle_time[drc & 3]) {<br>- if ( latency > cas_latency) {<br>- cas_latency = latency;<br>- }<br>- break;<br>- }<br>- }<br>- }<br>- index = (cas_latency-2);<br>- if ((index) == 0) cas_latency = 20;<br>- else if ((index) == 1) cas_latency = 25;<br>- else cas_latency = 30;<br>-<br>- for (cnt = 0; cnt < 4; cnt++) {<br>- if (!(dimm_mask & (1 << cnt))) {<br>- continue;<br>- }<br>- reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;<br>- if (((index>>8) & 0x0ff) < reg) {<br>- index &= ~(0x0ff << 8);<br>- index |= (reg << 8);<br>- }<br>- reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;<br>- if (((index>>16) & 0x0ff) < reg) {<br>- index &= ~(0x0ff << 16);<br>- index |= (reg<<16);<br>- }<br>- reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;<br>- if (((index2>>0) & 0x0ff) < reg) {<br>- index2 &= ~(0x0ff << 0);<br>- index2 |= (reg<<0);<br>- }<br>- reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;<br>- if (((index2>>8) & 0x0ff) < reg) {<br>- index2 &= ~(0x0ff << 8);<br>- index2 |= (reg<<8);<br>- }<br>- reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;<br>- if (((index2>>16) & 0x0ff) < reg) {<br>- index2 &= ~(0x0ff << 16);<br>- index2 |= (reg<<16);<br>- }<br>- }<br>-<br>- /* get dimm speed */<br>- value = cycle_time[drc & 3];<br>- if (value <= 0x50) { /* 200 MHz */<br>- if ((index & 7) > 2) {<br>- drt |= (2<<2); /* CAS latency 4 */<br>- cas_latency = 40;<br>- } else {<br>- drt |= (1<<2); /* CAS latency 3 */<br>- cas_latency = 30;<br>- }<br>- if ((index & 0x0ff00) <= 0x03c00) {<br>- drt |= (1<<8); /* Trp RAS Precharge */<br>- } else {<br>- drt |= (2<<8); /* Trp RAS Precharge */<br>- }<br>-<br>- /* Trcd RAS to CAS delay */<br>- if ((index2 & 0x0ff) <= 0x03c) {<br>- drt |= (0<<10);<br>- } else {<br>- drt |= (1<<10);<br>- }<br>-<br>- /* Tdal Write auto precharge recovery delay */<br>- drt |= (1<<12);<br>-<br>- /* Trc TRS min */<br>- if ((index2 & 0x0ff00) <= 0x03700)<br>- drt |= (0<<14);<br>- else if ((index2 & 0xff00) <= 0x03c00)<br>- drt |= (1<<14);<br>- else<br>- drt |= (2<<14); /* spd 41 */<br>-<br>- drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */<br>-<br>- /* Trrd Row Delay */<br>- if ((index & 0x0ff0000) <= 0x0140000) {<br>- drt |= (0<<20);<br>- } else if ((index & 0x0ff0000) <= 0x0280000) {<br>- drt |= (1<<20);<br>- } else if ((index & 0x0ff0000) <= 0x03c0000) {<br>- drt |= (2<<20);<br>- } else {<br>- drt |= (3<<20);<br>- }<br>-<br>- /* Trfc Auto refresh cycle time */<br>- if ((index2 & 0x0ff0000) <= 0x04b0000) {<br>- drt |= (0<<22);<br>- } else if ((index2 & 0x0ff0000) <= 0x0690000) {<br>- drt |= (1<<22);<br>- } else {<br>- drt |= (2<<22);<br>- }<br>- /* Docs say use 55 for all 200MHz */<br>- drt |= (0x055<<24);<br>- }<br>- else if (value <= 0x60) { /* 167 MHz */<br>- /* according to new documentation CAS latency is 00<br>- * for bits 3:2 for all 167 MHz<br>- drt |= ((index & 3)<<2); */ /* set CAS latency */<br>- if ((index & 0x0ff00) <= 0x03000) {<br>- drt |= (1<<8); /* Trp RAS Precharge */<br>- } else {<br>- drt |= (2<<8); /* Trp RAS Precharge */<br>- }<br>-<br>- /* Trcd RAS to CAS delay */<br>- if ((index2 & 0x0ff) <= 0x030) {<br>- drt |= (0<<10);<br>- } else {<br>- drt |= (1<<10);<br>- }<br>-<br>- /* Tdal Write auto precharge recovery delay */<br>- drt |= (2<<12);<br>-<br>- /* Trc TRS min */<br>- drt |= (2<<14); /* spd 41, but only one choice */<br>-<br>- drt |= (2<<16); /* Twr not defined for DDR docs say 2 */<br>-<br>- /* Trrd Row Delay */<br>- if ((index & 0x0ff0000) <= 0x0180000) {<br>- drt |= (0<<20);<br>- } else if ((index & 0x0ff0000) <= 0x0300000) {<br>- drt |= (1<<20);<br>- } else {<br>- drt |= (2<<20);<br>- }<br>-<br>- /* Trfc Auto refresh cycle time */<br>- if ((index2 & 0x0ff0000) <= 0x0480000) {<br>- drt |= (0<<22);<br>- } else if ((index2 & 0x0ff0000) <= 0x0780000) {<br>- drt |= (2<<22);<br>- } else {<br>- drt |= (2<<22);<br>- }<br>- /* Docs state to use 99 for all 167 MHz */<br>- drt |= (0x099<<24);<br>- }<br>- else if (value <= 0x75) { /* 133 MHz */<br>- drt |= ((index & 3)<<2); /* set CAS latency */<br>- if ((index & 0x0ff00) <= 0x03c00) {<br>- drt |= (1<<8); /* Trp RAS Precharge */<br>- } else {<br>- drt |= (2<<8); /* Trp RAS Precharge */<br>- }<br>-<br>- /* Trcd RAS to CAS delay */<br>- if ((index2 & 0x0ff) <= 0x03c) {<br>- drt |= (0<<10);<br>- } else {<br>- drt |= (1<<10);<br>- }<br>-<br>- /* Tdal Write auto precharge recovery delay */<br>- drt |= (1<<12);<br>-<br>- /* Trc TRS min */<br>- drt |= (2<<14); /* spd 41, but only one choice */<br>-<br>- drt |= (1<<16); /* Twr not defined for DDR docs say 1 */<br>-<br>- /* Trrd Row Delay */<br>- if ((index & 0x0ff0000) <= 0x01e0000) {<br>- drt |= (0<<20);<br>- } else if ((index & 0x0ff0000) <= 0x03c0000) {<br>- drt |= (1<<20);<br>- } else {<br>- drt |= (2<<20);<br>- }<br>-<br>- /* Trfc Auto refresh cycle time */<br>- if ((index2 & 0x0ff0000) <= 0x04b0000) {<br>- drt |= (0<<22);<br>- } else if ((index2 & 0x0ff0000) <= 0x0780000) {<br>- drt |= (2<<22);<br>- } else {<br>- drt |= (2<<22);<br>- }<br>-<br>- /* Based on CAS latency */<br>- if (index & 7)<br>- drt |= (0x099<<24);<br>- else<br>- drt |= (0x055<<24);<br>-<br>- }<br>- else {<br>- die("Invalid SPD 9 bus speed.\n");<br>- }<br>-<br>- /* 0x78 DRT */<br>- pci_write_config32(ctrl->f0, DRT, drt);<br>-<br>- return(cas_latency);<br>-}<br>-<br>-static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,<br>- long dimm_mask)<br>-{<br>- int value;<br>- int drc;<br>- int cnt;<br>- msr_t msr;<br>- u8 rate = 62;<br>- static const u8 spd_rates[6] = {15,3,7,7,62,62};<br>- static const u8 drc_rates[5] = {0,15,7,62,3};<br>- static const u8 fsb_conversion[8] = {0,1,3,2,3,0,3,3};<br>-<br>- /* 0x7c DRC */<br>- drc = pci_read_config32(ctrl->f0, DRC);<br>- for (cnt = 0; cnt < 4; cnt++) {<br>- if (!(dimm_mask & (1 << cnt))) {<br>- continue;<br>- }<br>- value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */<br>- if (value != 2) die("ERROR - Non ECC memory dimm\n");<br>-<br>- value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/<br>- value &= 0x0f; /* clip self refresh bit */<br>- if (value > 5) goto hw_err;<br>- if (rate > spd_rates[value])<br>- rate = spd_rates[value];<br>-<br>- value = spd_read_byte(ctrl->channel0[cnt], 9); /* cycle time */<br>- if (value > 0x75) goto hw_err;<br>- }<br>- drc |= (1 << 20); /* enable ECC */<br>- for (cnt = 1; cnt < 5; cnt++)<br>- if (drc_rates[cnt] == rate)<br>- break;<br>- if (cnt < 5) {<br>- drc &= ~(7 << 8); /* clear the rate bits */<br>- drc |= (cnt << 8);<br>- }<br>-<br>- drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */<br>- drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */<br>- drc |= (1 << 7);<br>- drc &= ~(1 << 5); /* enable ODT */<br>- drc |= (1 << 4); /* independent clocks */<br>-<br>- /* set front side bus speed */<br>- msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */<br>- value = msr.lo & 0x07;<br>- drc &= ~(3 << 2);<br>- drc |= (fsb_conversion[value] << 2);<br>-<br>- /* set dram type to ddr2 */<br>- drc &= ~(3 << 0);<br>- drc |= (2 << 0);<br>-<br>- goto out;<br>-<br>- /* If an hw_error occurs report that I have no memory */<br>- hw_err:<br>- drc = 0;<br>-out:<br>- return drc;<br>-}<br>-<br>-static void sdram_set_spd_registers(const struct mem_controller *ctrl)<br>-{<br>- long dimm_mask;<br>-<br>- /* Test if we can read the spd and if RAM is ddr or ddr2 */<br>- dimm_mask = spd_detect_dimms(ctrl);<br>- if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {<br>- printk(BIOS_ERR, "No memory for this cpu\n");<br>- return;<br>- }<br>- return;<br>-}<br>-<br>-static void do_delay(void)<br>-{<br>- int i;<br>- u8 b;<br>- for (i = 0; i < 16; i++)<br>- b = inb(0x80);<br>-}<br>-<br>-#define TIMEOUT_LOOPS 300000<br>-<br>-#define DCALCSR 0x100<br>-#define DCALADDR 0x104<br>-#define DCALDATA 0x108<br>-<br>-static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)<br>-{<br>- u8 c1,c2;<br>- u32 dimm,i;<br>- u32 data32 = 0;<br>- u32 t4;<br>-<br>- /* Set up northbridge values */<br>- /* ODT enable */<br>- pci_write_config32(ctrl->f0, SDRC, 0x30000000);<br>- /* Figure out which slots are Empty, Single, or Double sided */<br>- for (i = 0,t4 = 0,c2 = 0; i < 8; i+=2) {<br>- c1 = pci_read_config8(ctrl->f0, DRB+i);<br>- if (c1 == c2) continue;<br>- c2 = pci_read_config8(ctrl->f0, DRB+1+i);<br>- if (c1 == c2)<br>- t4 |= (1 << (i*4));<br>- else<br>- t4 |= (2 << (i*4));<br>- }<br>- for (i = 0; i < 1; i++) {<br>- if ((t4 & 0x0f) == 1) {<br>- if ( ((t4>>8)&0x0f) == 0 ) {<br>- data32 = 0x00000010; /* EEES */<br>- break;<br>- }<br>- if ( ((t4>>16)&0x0f) == 0 ) {<br>- data32 = 0x00003132; /* EESS */<br>- break;<br>- }<br>- if ( ((t4>>24)&0x0f) == 0 ) {<br>- data32 = 0x00335566; /* ESSS */<br>- break;<br>- }<br>- data32 = 0x77bbddee; /* SSSS */<br>- break;<br>- }<br>- if ((t4 & 0x0f) == 2) {<br>- if ( ((t4>>8)&0x0f) == 0 ) {<br>- data32 = 0x00003132; /* EEED */<br>- break;<br>- }<br>- if ( ((t4>>8)&0x0f) == 2 ) {<br>- data32 = 0xb373ecdc; /* EEDD */<br>- break;<br>- }<br>- if ( ((t4>>16)&0x0f) == 0 ) {<br>- data32 = 0x00b3a898; /* EESD */<br>- break;<br>- }<br>- data32 = 0x777becdc; /* ESSD */<br>- break;<br>- }<br>- die("Error - First dimm slot empty\n");<br>- }<br>-<br>- printk(BIOS_DEBUG, "ODT Value = %08x\n", data32);<br>-<br>- pci_write_config32(ctrl->f0, DDR2ODTC, data32);<br>-<br>- for (dimm = 0;dimm < 8;dimm+=2) {<br>-<br>- write32(MCBAR+DCALADDR, 0x0b840001);<br>- write32(MCBAR+DCALCSR, 0x81000003 | (dimm << 20));<br>-<br>- for (i = 0; i < 1001; i++) {<br>- data32 = read32(MCBAR+DCALCSR);<br>- if (!(data32 & (1<<31)))<br>- break;<br>- }<br>- }<br>-}<br>-static void set_receive_enable(const struct mem_controller *ctrl)<br>-{<br>- u32 i;<br>- u32 cnt;<br>- u32 recena = 0;<br>- u32 recenb = 0;<br>-<br>- {<br>- u32 dimm;<br>- u32 edge;<br>- int32_t data32;<br>- u32 dcal_data32_0;<br>- u32 dcal_data32_1;<br>- u32 dcal_data32_2;<br>- u32 dcal_data32_3;<br>- u32 work32l;<br>- u32 work32h;<br>- u32 data32r;<br>- int32_t recen;<br>- for (dimm = 0;dimm < 8;dimm+=1) {<br>-<br>- if (!(dimm & 1)) {<br>- write32(MCBAR+DCALDATA+(17*4), 0x04020000);<br>- write32(MCBAR+DCALCSR, 0x81800004 | (dimm << 20));<br>-<br>- for (i = 0; i < 1001; i++) {<br>- data32 = read32(MCBAR+DCALCSR);<br>- if (!(data32 & (1<<31)))<br>- break;<br>- }<br>- if (i >= 1000)<br>- continue;<br>-<br>- dcal_data32_0 = read32(MCBAR+DCALDATA + 0);<br>- dcal_data32_1 = read32(MCBAR+DCALDATA + 4);<br>- dcal_data32_2 = read32(MCBAR+DCALDATA + 8);<br>- dcal_data32_3 = read32(MCBAR+DCALDATA + 12);<br>- }<br>- else {<br>- dcal_data32_0 = read32(MCBAR+DCALDATA + 16);<br>- dcal_data32_1 = read32(MCBAR+DCALDATA + 20);<br>- dcal_data32_2 = read32(MCBAR+DCALDATA + 24);<br>- dcal_data32_3 = read32(MCBAR+DCALDATA + 28);<br>- }<br>-<br>- /* check if bank is installed */<br>- if ((dcal_data32_0 == 0) && (dcal_data32_2 == 0))<br>- continue;<br>- /* Calculate the timing value */<br>- {<br>- u32 bit;<br>- for (i = 0,edge = 0,bit = 63,cnt = 31,data32r = 0,<br>- work32l = dcal_data32_1,work32h = dcal_data32_3;<br>- (i < 4) && bit; i++) {<br>- for (;;bit--,cnt--) {<br>- if (work32l & (1<<cnt))<br>- break;<br>- if (!cnt) {<br>- work32l = dcal_data32_0;<br>- work32h = dcal_data32_2;<br>- cnt = 32;<br>- }<br>- if (!bit) break;<br>- }<br>- for (;;bit--,cnt--) {<br>- if (!(work32l & (1<<cnt)))<br>- break;<br>- if (!cnt) {<br>- work32l = dcal_data32_0;<br>- work32h = dcal_data32_2;<br>- cnt = 32;<br>- }<br>- if (!bit) break;<br>- }<br>- if (!bit) {<br>- break;<br>- }<br>- data32 = ((bit%8) << 1);<br>- if (work32h & (1<<cnt))<br>- data32 += 1;<br>- if (data32 < 4) {<br>- if (!edge) {<br>- edge = 1;<br>- }<br>- else {<br>- if (edge != 1) {<br>- data32 = 0x0f;<br>- }<br>- }<br>- }<br>- if (data32 > 12) {<br>- if (!edge) {<br>- edge = 2;<br>- }<br>- else {<br>- if (edge != 2) {<br>- data32 = 0x00;<br>- }<br>- }<br>- }<br>- data32r += data32;<br>- }<br>- }<br>- work32l = dcal_data32_0;<br>- work32h = dcal_data32_2;<br>- recen = data32r;<br>- recen += 3;<br>- recen = recen>>2;<br>- for (cnt = 5; cnt < 24;) {<br>- for (;; cnt++)<br>- if (!(work32l & (1<<cnt)))<br>- break;<br>- for (;; cnt++) {<br>- if (work32l & (1<<cnt))<br>- break;<br>- }<br>- data32 = (((cnt-1)%8)<<1);<br>- if (work32h & (1<<(cnt-1))) {<br>- data32++;<br>- }<br>- /* test for frame edge cross overs */<br>- if ((edge == 1) && (data32 > 12) &&<br>- (((recen+16)-data32) < 3)) {<br>- data32 = 0;<br>- cnt += 2;<br>- }<br>- if ((edge == 2) && (data32 < 4) &&<br>- ((recen - data32) > 12)) {<br>- data32 = 0x0f;<br>- cnt -= 2;<br>- }<br>- if (((recen+3) >= data32) && ((recen-3) <= data32))<br>- break;<br>- }<br>- cnt--;<br>- cnt /= 8;<br>- cnt--;<br>- if (recen & 1)<br>- recen+=2;<br>- recen >>= 1;<br>- recen += (cnt*8);<br>- recen+=2; /* this is not in the spec, but matches<br>- the factory output, and has less failure */<br>- recen <<= (dimm/2) * 8;<br>- if (!(dimm & 1)) {<br>- recena |= recen;<br>- }<br>- else {<br>- recenb |= recen;<br>- }<br>- }<br>- }<br>- /* Check for Errata problem */<br>- for (i = cnt = 0; i < 32; i+=8) {<br>- if (((recena>>i)&0x0f)>7) {<br>- cnt+= 0x101;<br>- }<br>- else {<br>- if ((recena>>i)&0x0f) {<br>- cnt++;<br>- }<br>- }<br>- }<br>- if (cnt & 0x0f00) {<br>- cnt = (cnt & 0x0f) - (cnt>>16);<br>- if (cnt > 1) {<br>- for (i = 0; i < 32; i+=8) {<br>- if (((recena>>i)&0x0f)>7) {<br>- recena &= ~(0x0f<<i);<br>- recena |= (7<<i);<br>- }<br>- }<br>- }<br>- else {<br>- for (i = 0; i < 32; i+=8) {<br>- if (((recena>>i)&0x0f)<8) {<br>- recena &= ~(0x0f<<i);<br>- recena |= (8<<i);<br>- }<br>- }<br>- }<br>- }<br>- for (i = cnt = 0; i < 32; i+=8) {<br>- if (((recenb>>i)&0x0f)>7) {<br>- cnt+= 0x101;<br>- }<br>- else {<br>- if ((recenb>>i)&0x0f) {<br>- cnt++;<br>- }<br>- }<br>- }<br>- if (cnt & 0x0f00) {<br>- cnt = (cnt & 0x0f) - (cnt>>16);<br>- if (cnt > 1) {<br>- for (i = 0; i < 32; i+=8) {<br>- if (((recenb>>i)&0x0f)>7) {<br>- recenb &= ~(0x0f<<i);<br>- recenb |= (7<<i);<br>- }<br>- }<br>- }<br>- else {<br>- for (i = 0; i < 32; i+=8) {<br>- if (((recenb>>8)&0x0f)<8) {<br>- recenb &= ~(0x0f<<i);<br>- recenb |= (8<<i);<br>- }<br>- }<br>- }<br>- }<br>-<br>- printk(BIOS_DEBUG, "Receive enable A = %08x, Receive enable B = %08x\n",<br>- recena, recenb);<br>-<br>- /* clear out the calibration area */<br>- write32(MCBAR+DCALDATA+(16*4), 0x00000000);<br>- write32(MCBAR+DCALDATA+(17*4), 0x00000000);<br>- write32(MCBAR+DCALDATA+(18*4), 0x00000000);<br>- write32(MCBAR+DCALDATA+(19*4), 0x00000000);<br>-<br>- /* No command */<br>- write32(MCBAR+DCALCSR, 0x0000000f);<br>-<br>- write32(MCBAR+0x150, recena);<br>- write32(MCBAR+0x154, recenb);<br>-}<br>-<br>-static void cache_ramstage(void)<br>-{<br>- /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */<br>- disable_cache();<br>- set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);<br>- enable_cache();<br>-}<br>-<br>-static void sdram_enable(int controllers, const struct mem_controller *ctrl)<br>-{<br>- int i;<br>- int cs;<br>- int cnt;<br>- u8 *cntptr;<br>- int cas_latency;<br>- long mask;<br>- u32 drc;<br>- u32 data32;<br>- u32 mode_reg;<br>- const u32 *iptr;<br>- u16 data16;<br>- static const struct {<br>- u32 clkgr[4];<br>- } gearing [] = {<br>- /* FSB 100 */<br>- {{ 0x00000010, 0x00000000, 0x00000002, 0x00000001}},<br>- /* FSB 133 */<br>- {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},<br>- /* FSB 167 */<br>- {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},<br>- /* FSB 200 DIMM 400 */<br>- {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},<br>- };<br>-<br>- static const u32 dqs_data[] = {<br>- 0xffffffff, 0xffffffff, 0x000000ff,<br>- 0xffffffff, 0xffffffff, 0x000000ff,<br>- 0xffffffff, 0xffffffff, 0x000000ff,<br>- 0xffffffff, 0xffffffff, 0x000000ff,<br>- 0xffffffff, 0xffffffff, 0x000000ff,<br>- 0xffffffff, 0xffffffff, 0x000000ff,<br>- 0xffffffff, 0xffffffff, 0x000000ff,<br>- 0xffffffff, 0xffffffff, 0x000000ff};<br>-<br>- mask = spd_detect_dimms(ctrl);<br>- printk(BIOS_DEBUG, "Starting SDRAM Enable\n");<br>-<br>- /* 0x80 */<br>- pci_write_config32(ctrl->f0, DRM,<br>- 0x00410000 | CONFIG_DIMM_MAP_LOGICAL);<br>- /* set dram type and Front Side Bus freq. */<br>- drc = spd_set_dram_controller_mode(ctrl, mask);<br>- if ( drc == 0) {<br>- die("Error calculating DRC\n");<br>- }<br>- data32 = drc & ~(3 << 20); /* clear ECC mode */<br>- data32 = data32 & ~(7 << 8); /* clear refresh rates */<br>- data32 = data32 | (1 << 5); /* temp turn off ODT */<br>- /* Set gearing, then dram controller mode */<br>- /* drc bits 3:2 = FSB speed */<br>- for (iptr = gearing[(drc>>2)&3].clkgr,cnt = 0; cnt < 4; cnt++) {<br>- pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);<br>- }<br>- /* 0x7c DRC */<br>- pci_write_config32(ctrl->f0, DRC, data32);<br>-<br>- /* turn the clocks on */<br>- /* 0x8c CKDIS */<br>- pci_write_config16(ctrl->f0, CKDIS, 0x0000);<br>-<br>- /* 0x9a DDRCSR Take subsystem out of idle */<br>- data16 = pci_read_config16(ctrl->f0, DDRCSR);<br>- data16 &= ~(7 << 12);<br>- data16 |= (1 << 12);<br>- pci_write_config16(ctrl->f0, DDRCSR, data16);<br>-<br>- /* program row size DRB */<br>- spd_set_ram_size(ctrl, mask);<br>-<br>- /* program page size DRA */<br>- spd_set_row_attributes(ctrl, mask);<br>-<br>- /* program DRT timing values */<br>- cas_latency = spd_set_drt_attributes(ctrl, mask, drc);<br>-<br>- for (i = 0; i < 8; i+=2) { /* loop through each dimm to test */<br>- printk(BIOS_DEBUG, "DIMM %08x\n", i);<br>- /* Apply NOP */<br>- do_delay();<br>-<br>- write32(MCBAR+DCALCSR, (0x01000000 | (i<<20)));<br>- write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));<br>-<br>- do data32 = read32(MCBAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* Apply NOP */<br>- do_delay();<br>-<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));<br>- do data32 = read32(MCBAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* Precharge all banks */<br>- do_delay();<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALADDR, 0x04000000);<br>- write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));<br>- do data32 = read32(MCBAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* EMRS dll's enabled */<br>- do_delay();<br>- for (cs = 0; cs < 8; cs+=2) {<br>- /* fixme hard code AL additive latency */<br>- write32(MCBAR+DCALADDR, 0x0b940001);<br>- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));<br>- do data32 = read32(MCBAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>- /* MRS reset dll's */<br>- do_delay();<br>- if (cas_latency == 30)<br>- mode_reg = 0x053a0000;<br>- else<br>- mode_reg = 0x054a0000;<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALADDR, mode_reg);<br>- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));<br>- do data32 = read32(MCBAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* Precharge all banks */<br>- do_delay();<br>- do_delay();<br>- do_delay();<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALADDR, 0x04000000);<br>- write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));<br>- do data32 = read32(MCBAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* Do 2 refreshes */<br>- do_delay();<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>- do data32 = read32(MCBAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>- do_delay();<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>- do data32 = read32(MCBAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>- do_delay();<br>- /* for good luck do 6 more */<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>- }<br>- do_delay();<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>- }<br>- do_delay();<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>- }<br>- do_delay();<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>- }<br>- do_delay();<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>- }<br>- do_delay();<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>- }<br>- do_delay();<br>- /* MRS reset dll's normal */<br>- do_delay();<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));<br>- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));<br>- do data32 = read32(MCBAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* Do only if DDR2 EMRS dll's enabled */<br>- do_delay();<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALADDR, (0x0b940001));<br>- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));<br>- do data32 = read32(MCBAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- do_delay();<br>- /* No command */<br>- write32(MCBAR+DCALCSR, 0x0000000f);<br>-<br>- /* enable on dimm termination */<br>- set_on_dimm_termination_enable(ctrl);<br>-<br>- /* receive enable calibration */<br>- set_receive_enable(ctrl);<br>-<br>- /* DQS */<br>- pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);<br>- for (i = 0, cntptr = (MCBAR+0x200); i < 24; i++, cnt+=4) {<br>- write32(cntptr, dqs_data[i]);<br>- }<br>- pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);<br>-<br>- /* Enable refresh */<br>- /* 0x7c DRC */<br>- data32 = drc & ~(3 << 20); /* clear ECC mode */<br>- pci_write_config32(ctrl->f0, DRC, data32);<br>- write32(MCBAR+DCALCSR, 0x0008000f);<br>-<br>- /* clear memory and init ECC */<br>- printk(BIOS_DEBUG, "Clearing memory\n");<br>- for (i = 0; i < 64; i+=4) {<br>- write32(MCBAR+DCALDATA+i, 0x00000000);<br>- }<br>-<br>- for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));<br>- do data32 = read32(MCBAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* Bring memory subsystem on line */<br>- data32 = pci_read_config32(ctrl->f0, 0x98);<br>- data32 |= (1 << 31);<br>- pci_write_config32(ctrl->f0, 0x98, data32);<br>- /* wait for completion */<br>- printk(BIOS_DEBUG, "Waiting for mem complete\n");<br>- while (1) {<br>- data32 = pci_read_config32(ctrl->f0, 0x98);<br>- if ( (data32 & (1<<31)) == 0)<br>- break;<br>- }<br>- printk(BIOS_DEBUG, "Done\n");<br>-<br>- /* Set initialization complete */<br>- /* 0x7c DRC */<br>- drc |= (1 << 29);<br>- data32 = drc & ~(3 << 20); /* clear ECC mode */<br>- pci_write_config32(ctrl->f0, DRC, data32);<br>-<br>- /* Set the ecc mode */<br>- pci_write_config32(ctrl->f0, DRC, drc);<br>-<br>- /* Enable memory scrubbing */<br>- /* 0x52 MCHSCRB */<br>- data16 = pci_read_config16(ctrl->f0, MCHSCRB);<br>- data16 &= ~0x0f;<br>- data16 |= ((2 << 2) | (2 << 0));<br>- pci_write_config16(ctrl->f0, MCHSCRB, data16);<br>-<br>- /* The memory is now setup, use it */<br>- if (!IS_ENABLED(CONFIG_CACHE_AS_RAM))<br>- cache_ramstage();<br>-}<br>diff --git a/src/northbridge/intel/i3100/raminit.h b/src/northbridge/intel/i3100/raminit.h<br>deleted file mode 100644<br>index aa245de..0000000<br>--- a/src/northbridge/intel/i3100/raminit.h<br>+++ /dev/null<br>@@ -1,31 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* This code is based on src/northbridge/intel/e7520/raminit.h */<br>-<br>-#ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_H<br>-#define NORTHBRIDGE_INTEL_I3100_RAMINIT_H<br>-<br>-#define DIMM_SOCKETS 4<br>-struct mem_controller {<br>- u32 node_id;<br>- device_t f0, f1, f2, f3;<br>- u16 channel0[DIMM_SOCKETS];<br>- u16 channel1[DIMM_SOCKETS];<br>-};<br>-<br>-void sdram_initialize(int controllers, const struct mem_controller *ctrl);<br>-<br>-#endif<br>diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c<br>deleted file mode 100644<br>index fa557da..0000000<br>--- a/src/northbridge/intel/i3100/raminit_ep80579.c<br>+++ /dev/null<br>@@ -1,693 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <lib.h><br>-#include <cpu/x86/mtrr.h><br>-#include <cpu/x86/cache.h><br>-#include <cpu/intel/speedstep.h><br>-#include <lib.h><br>-#include <delay.h><br>-#include "raminit_ep80579.h"<br>-#include "ep80579.h"<br>-<br>-#define BAR ((u8 *)0x90000000)<br>-<br>-static void sdram_set_registers(const struct mem_controller *ctrl)<br>-{<br>- static const u32 register_values[] = {<br>- PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,<br>- PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420001 | DEVPRES_CONFIG,<br>- PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,<br>- PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,<br>- PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a,<br>- PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, (uintptr_t)BAR | 0,<br>- };<br>- int i;<br>-<br>- for (i = 0; i < ARRAY_SIZE(register_values); i += 3) {<br>- device_t dev;<br>- u32 where;<br>- u32 reg;<br>- dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;<br>- where = register_values[i] & 0xff;<br>- reg = pci_read_config32(dev, where);<br>- reg &= register_values[i+1];<br>- reg |= register_values[i+2];<br>- pci_write_config32(dev, where, reg);<br>- }<br>-}<br>-<br>-struct dimm_size {<br>- u32 side1;<br>- u32 side2;<br>-};<br>-<br>-static struct dimm_size spd_get_dimm_size(u16 device)<br>-{<br>- /* Calculate the log base 2 size of a DIMM in bits */<br>- struct dimm_size sz;<br>- int value, low;<br>- sz.side1 = 0;<br>- sz.side2 = 0;<br>-<br>- /* Note it might be easier to use byte 31 here, it has the DIMM size as<br>- * a multiple of 4MB. The way we do it now we can size both<br>- * sides of an assymetric dimm.<br>- */<br>- value = spd_read_byte(device, SPD_NUM_ROWS);<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xf) == 0) goto val_err;<br>- sz.side1 += value & 0xf;<br>-<br>- value = spd_read_byte(device, SPD_NUM_COLUMNS);<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xf) == 0) goto val_err;<br>- sz.side1 += value & 0xf;<br>-<br>- value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM);<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xff) == 0) goto val_err;<br>- sz.side1 += log2(value & 0xff);<br>-<br>- /* Get the module data width and convert it to a power of two */<br>- value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB);<br>- if (value < 0) goto hw_err;<br>- value &= 0xff;<br>- value <<= 8;<br>-<br>- low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);<br>- if (low < 0) goto hw_err;<br>- value = value | (low & 0xff);<br>- if ((value != 72) && (value != 64)) goto val_err;<br>- sz.side1 += log2(value);<br>-<br>- /* side 2 */<br>- value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);<br>-<br>- if (value < 0) goto hw_err;<br>- value &= 7;<br>- value++;<br>- if (value == 1) goto out;<br>- if (value != 2) goto val_err;<br>-<br>- /* Start with the symmetrical case */<br>- sz.side2 = sz.side1;<br>-<br>- value = spd_read_byte(device, SPD_NUM_ROWS);<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */<br>- sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */<br>- sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */<br>-<br>- value = spd_read_byte(device, SPD_NUM_COLUMNS);<br>- if (value < 0) goto hw_err;<br>- if ((value & 0xff) == 0) goto val_err;<br>- sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */<br>- sz.side2 += ((value >> 4) & 0x0f); /* Add in columns on side 2 */<br>- goto out;<br>-<br>- val_err:<br>- die("Bad SPD value\n");<br>- /* If an hw_error occurs report that I have no memory */<br>- hw_err:<br>- sz.side1 = 0;<br>- sz.side2 = 0;<br>-out:<br>- printk(BIOS_DEBUG, "dimm %02x size = %02x.%02x\n", device, sz.side1, sz.side2);<br>- return sz;<br>-<br>-}<br>-<br>-static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask)<br>-{<br>- int i;<br>- int cum;<br>-<br>- for (i = cum = 0; i < DIMM_SOCKETS; i++) {<br>- struct dimm_size sz;<br>- if (dimm_mask & (1 << i)) {<br>- sz = spd_get_dimm_size(ctrl->channel0[i]);<br>- if (sz.side1 < 29) {<br>- return -1; /* Report SPD error */<br>- }<br>- /* convert bits to multiples of 64MB */<br>- sz.side1 -= 29;<br>- cum += (1 << sz.side1);<br>- pci_write_config8(ctrl->f0, DRB + (i*2), cum);<br>- pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);<br>- if (spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS) & 0x1) {<br>- cum <<= 1;<br>- }<br>- }<br>- else {<br>- pci_write_config8(ctrl->f0, DRB + (i*2), cum);<br>- pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);<br>- }<br>- }<br>- printk(BIOS_DEBUG, "DRB = %08x\n", pci_read_config32(ctrl->f0, DRB));<br>-<br>- cum >>= 1;<br>- /* set TOM top of memory */<br>- pci_write_config16(ctrl->f0, TOM, cum);<br>- printk(BIOS_DEBUG, "TOM = %04x\n", cum);<br>- /* set TOLM top of low memory */<br>- if (cum > 0x18) {<br>- cum = 0x18;<br>- }<br>- cum <<= 11;<br>- pci_write_config16(ctrl->f0, TOLM, cum);<br>- printk(BIOS_DEBUG, "TOLM = %04x\n", cum);<br>- return 0;<br>-}<br>-<br>-<br>-static u8 spd_detect_dimms(const struct mem_controller *ctrl)<br>-{<br>- u8 dimm_mask = 0;<br>- int i;<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- int byte;<br>- u16 device;<br>- device = ctrl->channel0[i];<br>- if (device) {<br>- byte = spd_read_byte(device, SPD_MEMORY_TYPE);<br>- printk(BIOS_DEBUG, "spd %02x = %02x\n", device, byte);<br>- if (byte == 8) {<br>- dimm_mask |= (1 << i);<br>- }<br>- }<br>- }<br>- return dimm_mask;<br>-}<br>-<br>-<br>-static int spd_set_row_attributes(const struct mem_controller *ctrl,<br>- u8 dimm_mask)<br>-{<br>- int value;<br>- int i;<br>-<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- u32 dra = 0;<br>- int reg = 0;<br>-<br>- if (!(dimm_mask & (1 << i))) {<br>- continue;<br>- }<br>-<br>- value = spd_read_byte(ctrl->channel0[i], SPD_NUM_ROWS);<br>- if (value < 0) die("Bad SPD data\n");<br>- if ((value & 0xf) == 0) die("Invalid # of rows\n");<br>- dra |= (((value-13) & 0x7) << 23);<br>- dra |= (((value-13) & 0x7) << 29);<br>- reg += value & 0xf;<br>-<br>- value = spd_read_byte(ctrl->channel0[i], SPD_NUM_COLUMNS);<br>- if (value < 0) die("Bad SPD data\n");<br>- if ((value & 0xf) == 0) die("Invalid # of columns\n");<br>- dra |= (((value-10) & 0x7) << 20);<br>- dra |= (((value-10) & 0x7) << 26);<br>- reg += value & 0xf;<br>-<br>- value = spd_read_byte(ctrl->channel0[i], SPD_NUM_BANKS_PER_SDRAM);<br>- if (value < 0) die("Bad SPD data\n");<br>- if ((value & 0xff) == 0) die("Invalid # of banks\n");<br>- reg += log2(value & 0xff);<br>-<br>- printk(BIOS_DEBUG, "dimm %02x reg = %02x\n", i, reg);<br>-<br>- /* set device density */<br>- dra |= ((31-reg));<br>- dra |= ((31-reg) << 6);<br>-<br>- /* set device width (x8) */<br>- dra |= (1 << 4);<br>- dra |= (1 << 10);<br>-<br>- /* set device type (registered) */<br>- dra |= (1 << 14);<br>-<br>- /* set number of ranks (0 = single, 1 = dual) */<br>- value = spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS);<br>- dra |= ((value & 0x1) << 17);<br>-<br>- printk(BIOS_DEBUG, "DRA%02x = %08x\n", i, dra);<br>-<br>- pci_write_config32(ctrl->f0, DRA + (i*4), dra);<br>- }<br>- return 0;<br>-}<br>-<br>-<br>-static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,<br>- u8 dimm_mask, u32 drc)<br>-{<br>- int i;<br>- u32 val, val1;<br>- u32 cl;<br>- u32 trc = 0;<br>- u32 trfc = 0;<br>- u32 tras = 0;<br>- u32 trtp = 0;<br>- u32 twtr = 0;<br>- int index = drc & 0x00000003;<br>- int ci;<br>- static const u8 latencies[] = { /* 533, 800, 400, 667 */<br>- 0x10, 0x60, 0x10, 0x20 };<br>- static const u32 drt0[] = { /* 533, 800, 400, 667 */<br>- 0x24240002, 0x24360002, 0x24220002, 0x24360002 };<br>- static const u32 drt1[] = { /* 533, 800, 400, 667 */<br>- 0x00400000, 0x00900000, 0x00200000, 0x00700000 };<br>- static const u32 magic[] = { /* 533, 800, 400, 667 */<br>- 0x007b8221, 0x00b94331, 0x005ca1a1, 0x009a62b1 };<br>- static const u32 mrs[] = { /* 533, 800, 400, 667 */<br>- 0x07020000, 0x0b020000, 0x05020000, 0x09020000 };<br>- static const int cycle[] = { /* 533, 800, 400, 667 */<br>- 15, 10, 20, 12 }; /* cycle time in 1/4 ns units */<br>- static const int byte40rem[] = {<br>- 0, 1, 2, 2, 3, 3, 0, 0 }; /* byte 40 remainder in 1/4 ns units */<br>-<br>- /* CAS latency in cycles */<br>- val = latencies[index];<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- if (!(dimm_mask & (1 << i)))<br>- continue;<br>- val &= spd_read_byte(ctrl->channel0[i], SPD_ACCEPTABLE_CAS_LATENCIES);<br>- }<br>- if (val & 0x10)<br>- cl = 4;<br>- else if (val & 0x20)<br>- cl = 5;<br>- else if (val & 0x40)<br>- cl = 6;<br>- else<br>- die("CAS latency mismatch\n");<br>- printk(BIOS_DEBUG, "cl = %02x\n", cl);<br>-<br>- ci = cycle[index];<br>-<br>- /* Trc, Trfc in cycles */<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- if (!(dimm_mask & (1 << i)))<br>- continue;<br>- val1 = spd_read_byte(ctrl->channel0[i], SPD_BYTE_41_42_EXTENSION);<br>- val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACT_TO_ACT_AUTO_REFRESH);<br>- val <<= 2; /* convert to 1/4 ns */<br>- val += byte40rem[(val1 >> 4) & 0x7];<br>- val = CEIL_DIV(val, ci) + 1; /* convert to cycles */<br>- if (trc < val)<br>- trc = val;<br>- val = spd_read_byte(ctrl->channel0[i], SPD_MIN_AUTO_REFRESH_TO_ACT);<br>- val <<= 2; /* convert to 1/4 ns */<br>- if (val1 & 0x01)<br>- val += 1024;<br>- val += byte40rem[(val1 >> 1) & 0x7];<br>- val = CEIL_DIV(val, ci); /* convert to cycles */<br>- if (trfc < val)<br>- trfc = val;<br>- }<br>- printk(BIOS_DEBUG, "trc = %02x\n", trc);<br>- printk(BIOS_DEBUG, "trfc = %02x\n", trfc);<br>-<br>- /* Tras, Trtp, Twtr in cycles */<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- if (!(dimm_mask & (1 << i)))<br>- continue;<br>- val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);<br>- val <<= 2; /* convert to 1/4 ns */<br>- val = CEIL_DIV(val, ci); /* convert to cycles */<br>- if (tras < val)<br>- tras = val;<br>- val = spd_read_byte(ctrl->channel0[i], SPD_INT_READ_TO_PRECHARGE_DELAY);<br>- val = CEIL_DIV(val, ci); /* convert to cycles */<br>- if (trtp < val)<br>- trtp = val;<br>- val = spd_read_byte(ctrl->channel0[i], SPD_INT_WRITE_TO_READ_DELAY);<br>- val = CEIL_DIV(val, ci); /* convert to cycles */<br>- if (twtr < val)<br>- twtr = val;<br>- }<br>- printk(BIOS_DEBUG, "tras = %02x\n", tras);<br>- printk(BIOS_DEBUG, "trtp = %02x\n", trtp);<br>- printk(BIOS_DEBUG, "twtr = %02x\n", twtr);<br>-<br>- val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9)<br>- | ((cl - 3) << 6) | ((cl - 3) << 3));<br>- printk(BIOS_DEBUG, "drt0 = %08x\n", val);<br>- pci_write_config32(ctrl->f0, DRT0, val);<br>-<br>- val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25)<br>- | (twtr << 15));<br>- printk(BIOS_DEBUG, "drt1 = %08x\n", val);<br>- pci_write_config32(ctrl->f0, DRT1, val);<br>-<br>- val = (magic[index]);<br>- printk(BIOS_DEBUG, "magic = %08x\n", val);<br>- pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);<br>-<br>- val = (mrs[index] | (cl << 20));<br>- printk(BIOS_DEBUG, "mrs = %08x\n", val);<br>- return val;<br>-}<br>-<br>-static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,<br>- u8 dimm_mask)<br>-{<br>- int value;<br>- int drc = 0;<br>- int i;<br>- msr_t msr;<br>- u8 cycle = 0x25;<br>-<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- if (!(dimm_mask & (1 << i)))<br>- continue;<br>- if ((spd_read_byte(ctrl->channel0[i], SPD_MODULE_DATA_WIDTH_LSB) & 0xf0) != 0x40)<br>- die("ERROR: Only 64-bit DIMMs supported\n");<br>- if (!(spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02))<br>- die("ERROR: Only ECC DIMMs supported\n");<br>- if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 0x08)<br>- die("ERROR: Only x8 DIMMs supported\n");<br>-<br>- value = spd_read_byte(ctrl->channel0[i], SPD_MIN_CYCLE_TIME_AT_CAS_MAX);<br>- if (value > cycle)<br>- cycle = value;<br>- }<br>- printk(BIOS_DEBUG, "cycle = %02x\n", cycle);<br>-<br>- drc |= (1 << 20); /* enable ECC */<br>- drc |= (3 << 30); /* enable CKE on each DIMM */<br>- drc |= (1 << 4); /* enable CKE globally */<br>-<br>- /* TODO check: */<br>- /* set front side bus speed */<br>- msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */<br>- printk(BIOS_DEBUG, "MSR FSB_FREQ(0xcd) = %08x%08x\n", msr.hi, msr.lo);<br>-<br>- /* TODO check that this msr really indicates fsb speed! */<br>- if (msr.lo & 0x07) {<br>- printk(BIOS_INFO, "533 MHz FSB\n");<br>- if (cycle <= 0x25) {<br>- drc |= 0x5;<br>- printk(BIOS_INFO, "400 MHz DDR\n");<br>- } else if (cycle <= 0x30) {<br>- drc |= 0x7;<br>- printk(BIOS_INFO, "333 MHz DDR\n");<br>- } else if (cycle <= 0x3d) {<br>- drc |= 0x4;<br>- printk(BIOS_INFO, "266 MHz DDR\n");<br>- } else {<br>- drc |= 0x2;<br>- printk(BIOS_INFO, "200 MHz DDR\n");<br>- }<br>- }<br>- else {<br>- printk(BIOS_INFO, "400 MHz FSB\n");<br>- if (cycle <= 0x30) {<br>- drc |= 0x7;<br>- printk(BIOS_INFO, "333 MHz DDR\n");<br>- } else if (cycle <= 0x3d) {<br>- drc |= 0x0;<br>- printk(BIOS_INFO, "266 MHz DDR\n");<br>- } else {<br>- drc |= 0x2;<br>- printk(BIOS_INFO, "200 MHz DDR\n");<br>- }<br>- }<br>-<br>- printk(BIOS_DEBUG, "DRC = %08x\n", drc);<br>-<br>- return drc;<br>-}<br>-<br>-static void sdram_set_spd_registers(const struct mem_controller *ctrl)<br>-{<br>- u8 dimm_mask;<br>-<br>- /* Test if we can read the SPD */<br>- dimm_mask = spd_detect_dimms(ctrl);<br>- if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {<br>- printk(BIOS_ERR, "No memory for this cpu\n");<br>- return;<br>- }<br>- return;<br>-}<br>-<br>-static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)<br>-{<br>- u8 c1,c2;<br>- u32 i;<br>- u32 data32 = 0;<br>-<br>- /* Set up northbridge values */<br>- /* ODT enable */<br>- pci_write_config32(ctrl->f0, SDRC, 0xa0002c30);<br>-<br>- c1 = pci_read_config8(ctrl->f0, DRB);<br>- c2 = pci_read_config8(ctrl->f0, DRB+2);<br>- if (c1 == c2) {<br>- /* 1 single-rank DIMM */<br>- data32 = 0x00000010;<br>- }<br>- else {<br>- /* 2 single-rank DIMMs or 1 double-rank DIMM */<br>- data32 = 0x00002010;<br>- }<br>-<br>- printk(BIOS_DEBUG, "ODT Value = %08x\n", data32);<br>-<br>- pci_write_config32(ctrl->f0, DDR2ODTC, data32);<br>-<br>- for (i = 0; i < 2; i++) {<br>- printk(BIOS_DEBUG, "ODT CS%d\n", i);<br>-<br>- write32(BAR+DCALADDR, 0x0b840001);<br>- write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));<br>- do data32 = read32(BAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-}<br>-<br>-<br>-static void dump_dcal_regs(void)<br>-{<br>- int i;<br>- for (i = 0x0; i < 0x2a0; i += 4) {<br>- if ((i % 16) == 0) {<br>- printk(BIOS_DEBUG, "\n%04x: ", i);<br>- }<br>- printk(BIOS_DEBUG, "%08x ", read32(BAR+i));<br>- }<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-<br>-static void sdram_enable(int controllers, const struct mem_controller *ctrl)<br>-{<br>- int i;<br>- int cs;<br>- long mask;<br>- u32 drc;<br>- u32 data32;<br>- u32 mode_reg;<br>-<br>- mask = spd_detect_dimms(ctrl);<br>- printk(BIOS_DEBUG, "Starting SDRAM Enable\n");<br>-<br>- /* Set DRAM type and Front Side Bus frequency */<br>- drc = spd_set_dram_controller_mode(ctrl, mask);<br>- if (drc == 0) {<br>- die("Error calculating DRC\n");<br>- }<br>- data32 = drc & ~(3 << 20); /* clear ECC mode */<br>- data32 = data32 | (3 << 5); /* temp turn off ODT */<br>- /* Set DRAM controller mode */<br>- pci_write_config32(ctrl->f0, DRC, data32);<br>-<br>- /* Turn the clocks on */<br>- pci_write_config16(ctrl->f0, CKDIS, 0x0000);<br>-<br>- /* Program row size */<br>- spd_set_ram_size(ctrl, mask);<br>-<br>- /* Program row attributes */<br>- spd_set_row_attributes(ctrl, mask);<br>-<br>- /* Program timing values */<br>- mode_reg = spd_set_drt_attributes(ctrl, mask, drc);<br>-<br>- dump_dcal_regs();<br>-<br>- /* Apply NOP */<br>- for (cs = 0; cs < 2; cs++) {<br>- printk(BIOS_DEBUG, "NOP CS%d\n", cs);<br>- udelay(16);<br>- write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));<br>- write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));<br>- do data32 = read32(BAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* Apply NOP */<br>- udelay(16);<br>- for (cs = 0; cs < 2; cs++) {<br>- printk(BIOS_DEBUG, "NOP CS%d\n", cs);<br>- write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));<br>- do data32 = read32(BAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* Precharge all banks */<br>- udelay(16);<br>- for (cs = 0; cs < 2; cs++) {<br>- printk(BIOS_DEBUG, "Precharge CS%d\n", cs);<br>- write32(BAR+DCALADDR, 0x04000000);<br>- write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));<br>- do data32 = read32(BAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* EMRS: Enable DLLs, set OCD calibration mode to default */<br>- udelay(16);<br>- for (cs = 0; cs < 2; cs++) {<br>- printk(BIOS_DEBUG, "EMRS CS%d\n", cs);<br>- write32(BAR+DCALADDR, 0x0b840001);<br>- write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));<br>- do data32 = read32(BAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>- /* MRS: Reset DLLs */<br>- udelay(16);<br>- for (cs = 0; cs < 2; cs++) {<br>- printk(BIOS_DEBUG, "MRS CS%d\n", cs);<br>- write32(BAR+DCALADDR, mode_reg);<br>- write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));<br>- do data32 = read32(BAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* Precharge all banks */<br>- udelay(48);<br>- for (cs = 0; cs < 2; cs++) {<br>- printk(BIOS_DEBUG, "Precharge CS%d\n", cs);<br>- write32(BAR+DCALADDR, 0x04000000);<br>- write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));<br>- do data32 = read32(BAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* Do 2 refreshes */<br>- for (i = 0; i < 2; i++) {<br>- udelay(16);<br>- for (cs = 0; cs < 2; cs++) {<br>- printk(BIOS_DEBUG, "Refresh CS%d\n", cs);<br>- write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));<br>- do data32 = read32(BAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>- }<br>-<br>- /* MRS: Set DLLs to normal */<br>- udelay(16);<br>- for (cs = 0; cs < 2; cs++) {<br>- printk(BIOS_DEBUG, "MRS CS%d\n", cs);<br>- write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));<br>- write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));<br>- do data32 = read32(BAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- /* EMRS: Enable DLLs */<br>- udelay(16);<br>- for (cs = 0; cs < 2; cs++) {<br>- printk(BIOS_DEBUG, "EMRS CS%d\n", cs);<br>- write32(BAR+DCALADDR, 0x0b840001);<br>- write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));<br>- do data32 = read32(BAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- udelay(16);<br>- /* No command */<br>- write32(BAR+DCALCSR, 0x0000000f);<br>-<br>- write32(BAR, 0x00100000);<br>-<br>- /* Enable on-DIMM termination */<br>- set_on_dimm_termination_enable(ctrl);<br>-<br>- dump_dcal_regs();<br>-<br>- /* Receive enable calibration */<br>- udelay(16);<br>- for (cs = 0; cs < 1; cs++) {<br>- printk(BIOS_DEBUG, "receive enable calibration CS%d\n", cs);<br>- write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));<br>- do data32 = read32(BAR+DCALCSR);<br>- while (data32 & 0x80000000);<br>- }<br>-<br>- dump_dcal_regs();<br>-<br>- /* Adjust RCOMP */<br>- data32 = read32(BAR+DDRIOMC2);<br>- data32 &= ~(0xf << 16);<br>- data32 |= (0xb << 16);<br>- write32(BAR+DDRIOMC2, data32);<br>-<br>- dump_dcal_regs();<br>-<br>- data32 = drc & ~(3 << 20); /* clear ECC mode */<br>- pci_write_config32(ctrl->f0, DRC, data32);<br>- write32(BAR+DCALCSR, 0x0008000f);<br>-<br>- /* Clear memory and init ECC */<br>- for (cs = 0; cs < 2; cs++) {<br>- if (!(mask & (1<<cs)))<br>- continue;<br>- printk(BIOS_DEBUG, "clear memory CS%d\n", cs);<br>- write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));<br>- do data32 = read32(BAR+MBCSR);<br>- while (data32 & 0x80000000);<br>- if (data32 & 0x40000000)<br>- printk(BIOS_DEBUG, "failed!\n");<br>- }<br>-<br>- /* Clear read/write FIFO pointers */<br>- printk(BIOS_DEBUG, "clear read/write fifo pointers\n");<br>- write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));<br>- udelay(16);<br>- write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));<br>- udelay(16);<br>-<br>- dump_dcal_regs();<br>-<br>- printk(BIOS_DEBUG, "Done\n");<br>-<br>- /* Set initialization complete */<br>- drc |= (1 << 29);<br>- drc |= (3 << 30);<br>- data32 = drc & ~(3 << 20); /* clear ECC mode */<br>- pci_write_config32(ctrl->f0, DRC, data32);<br>-<br>- /* Set the ECC mode */<br>- pci_write_config32(ctrl->f0, DRC, drc);<br>-}<br>-<br>-static inline int memory_initialized(void)<br>-{<br>- return pci_read_config32(PCI_DEV(0, 0x00, 0), DRC) & (1 << 29);<br>-}<br>diff --git a/src/northbridge/intel/i3100/raminit_ep80579.h b/src/northbridge/intel/i3100/raminit_ep80579.h<br>deleted file mode 100644<br>index aca96d2..0000000<br>--- a/src/northbridge/intel/i3100/raminit_ep80579.h<br>+++ /dev/null<br>@@ -1,27 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H<br>-#define NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H<br>-<br>-#define DIMM_SOCKETS 2<br>-struct mem_controller {<br>- u32 node_id;<br>- device_t f0;<br>- u16 channel0[DIMM_SOCKETS];<br>-};<br>-<br>-void sdram_initialize(int controllers, const struct mem_controller *ctrl);<br>-#endif<br>diff --git a/src/northbridge/intel/i3100/reset_test.c b/src/northbridge/intel/i3100/reset_test.c<br>deleted file mode 100644<br>index 1ea62c0..0000000<br>--- a/src/northbridge/intel/i3100/reset_test.c<br>+++ /dev/null<br>@@ -1,20 +0,0 @@<br>-/* Convert to C by yhlu */<br>-#define MCH_DRC 0x7c<br>-#define DRC_DONE (1 << 29)<br>-<br>-/* If I have already booted once skip a bunch of initialization */<br>-/* To see if I have already booted I check to see if memory<br>- * has been enabled.<br>- */<br>-int bios_reset_detected(void)<br>-{<br>- uint32_t dword;<br>-<br>- dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);<br>-<br>- if ( (dword & DRC_DONE) != 0 ) {<br>- return 1;<br>- }<br>-<br>- return 0;<br>-}<br>diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig<br>deleted file mode 100644<br>index 20990ba..0000000<br>--- a/src/southbridge/intel/i3100/Kconfig<br>+++ /dev/null<br>@@ -1,14 +0,0 @@<br>-config SOUTHBRIDGE_INTEL_I3100<br>- bool<br>- select IOAPIC<br>- select HAVE_HARD_RESET<br>- select SOUTHBRIDGE_INTEL_COMMON<br>- select SOUTHBRIDGE_INTEL_COMMON_SMBUS<br>-<br>-if SOUTHBRIDGE_INTEL_I3100<br>-<br>-config HPET_MIN_TICKS<br>- hex<br>- default 0x90<br>-<br>-endif<br>diff --git a/src/southbridge/intel/i3100/Makefile.inc b/src/southbridge/intel/i3100/Makefile.inc<br>deleted file mode 100644<br>index bcc6d06..0000000<br>--- a/src/southbridge/intel/i3100/Makefile.inc<br>+++ /dev/null<br>@@ -1,14 +0,0 @@<br>-ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I3100),y)<br>-<br>-ramstage-y += i3100.c<br>-ramstage-y += uhci.c<br>-ramstage-y += lpc.c<br>-ramstage-y += sata.c<br>-ramstage-y += ehci.c<br>-ramstage-y += smbus.c<br>-ramstage-y += pci.c<br>-ramstage-y += ioapic.c<br>-ramstage-y += reset.c<br>-ramstage-y += pciexp_portb.c<br>-<br>-endif<br>diff --git a/src/southbridge/intel/i3100/chip.h b/src/southbridge/intel/i3100/chip.h<br>deleted file mode 100644<br>index 26a452a..0000000<br>--- a/src/southbridge/intel/i3100/chip.h<br>+++ /dev/null<br>@@ -1,45 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-struct southbridge_intel_i3100_config<br>-{<br>-#define I3100_GPIO_USE_MASK 0x03<br>-#define I3100_GPIO_USE_DEFAULT 0x00<br>-#define I3100_GPIO_USE_AS_NATIVE 0x01<br>-#define I3100_GPIO_USE_AS_GPIO 0x02<br>-<br>-#define I3100_GPIO_SEL_MASK 0x0c<br>-#define I3100_GPIO_SEL_DEFAULT 0x00<br>-#define I3100_GPIO_SEL_OUTPUT 0x04<br>-#define I3100_GPIO_SEL_INPUT 0x08<br>-<br>-#define I3100_GPIO_LVL_MASK 0x30<br>-#define I3100_GPIO_LVL_DEFAULT 0x00<br>-#define I3100_GPIO_LVL_LOW 0x10<br>-#define I3100_GPIO_LVL_HIGH 0x20<br>-#define I3100_GPIO_LVL_BLINK 0x30<br>-<br>-#define I3100_GPIO_INV_MASK 0xc0<br>-#define I3100_GPIO_INV_DEFAULT 0x00<br>-#define I3100_GPIO_INV_OFF 0x40<br>-#define I3100_GPIO_INV_ON 0x80<br>-<br>- /* GPIO use select */<br>- u8 gpio[64];<br>- int sata_ports_implemented;<br>- u32 pirq_a_d;<br>- u32 pirq_e_h;<br>-};<br>diff --git a/src/southbridge/intel/i3100/early_lpc.c b/src/southbridge/intel/i3100/early_lpc.c<br>deleted file mode 100644<br>index bd9d974..0000000<br>--- a/src/southbridge/intel/i3100/early_lpc.c<br>+++ /dev/null<br>@@ -1,42 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-static void i3100_enable_superio(void)<br>-{<br>- device_t dev = PCI_DEV(0x0, 0x1f, 0x0);<br>-<br>- /* Enable decoding of I/O locations for SuperIO devices */<br>- pci_write_config16(dev, 0x80, 0x0010);<br>- pci_write_config16(dev, 0x82, 0x340f);<br>-<br>- /* Enable the SERIRQs (start pulse width is 8 clock cycles) */<br>- pci_write_config8(dev, 0x64, 0xD2);<br>-}<br>-<br>-static void i3100_halt_tco_timer(void)<br>-{<br>- device_t dev = PCI_DEV(0x0, 0x1f, 0x0);<br>-<br>- /* Temporarily enable the ACPI I/O range at 0x4000 */<br>- pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));<br>- pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7));<br>-<br>- /* Halt the TCO timer, preventing SMI and automatic reboot */<br>- outw(inw(0x4068) | (1 << 11), 0x4068);<br>-<br>- /* Disable the ACPI I/O range */<br>- pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7));<br>-}<br>diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c<br>deleted file mode 100644<br>index 35fe614..0000000<br>--- a/src/southbridge/intel/i3100/early_smbus.c<br>+++ /dev/null<br>@@ -1,44 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-#include <southbridge/intel/common/smbus.h><br>-<br>-#define SMBUS_IO_BASE 0x0f00<br>-<br>-static void enable_smbus(void)<br>-{<br>- pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);<br>-<br>- printk(BIOS_SPEW, "SMBus controller enabled\n");<br>- pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);<br>- pci_write_config8(dev, 0x40, 1);<br>- pci_write_config8(dev, 0x4, 1);<br>- /* SMBALERT_DIS */<br>- outb(4, SMBUS_IO_BASE + SMBSLVCMD);<br>-<br>- /* Disable interrupt generation */<br>- outb(0, SMBUS_IO_BASE + SMBHSTCTL);<br>-}<br>-<br>-static __attribute__((unused)) int smbus_read_byte(u32 device, u32 address)<br>-{<br>- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);<br>-}<br>-<br>-static __attribute__((unused)) int smbus_write_byte(unsigned device, u8 address, u8 data)<br>-{<br>- return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);<br>-}<br>diff --git a/src/southbridge/intel/i3100/ehci.c b/src/southbridge/intel/i3100/ehci.c<br>deleted file mode 100644<br>index e8809d8..0000000<br>--- a/src/southbridge/intel/i3100/ehci.c<br>+++ /dev/null<br>@@ -1,64 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include "i3100.h"<br>-<br>-static void ehci_init(struct device *dev)<br>-{<br>-}<br>-<br>-static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- u8 access_cntl;<br>- access_cntl = pci_read_config8(dev, 0x80);<br>- /* Enable writes to protected registers */<br>- pci_write_config8(dev, 0x80, access_cntl | 1);<br>- /* Write the subsystem vendor and device id */<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- /* Restore protection */<br>- pci_write_config8(dev, 0x80, access_cntl);<br>-}<br>-<br>-static struct pci_operations lops_pci = {<br>- .set_subsystem = &ehci_set_subsystem,<br>-};<br>-static struct device_operations ehci_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = ehci_init,<br>- .scan_bus = 0,<br>- .enable = i3100_enable,<br>- .ops_pci = &lops_pci,<br>-};<br>-<br>-static const struct pci_driver ehci_driver __pci_driver = {<br>- .ops = &ehci_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_EHCI,<br>-};<br>-<br>-static const struct pci_driver ehci_driver_ep80579 __pci_driver = {<br>- .ops = &ehci_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_EP80579_EHCI,<br>-};<br>diff --git a/src/southbridge/intel/i3100/i3100.c b/src/southbridge/intel/i3100/i3100.c<br>deleted file mode 100644<br>index 7becc0e..0000000<br>--- a/src/southbridge/intel/i3100/i3100.c<br>+++ /dev/null<br>@@ -1,58 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include "i3100.h"<br>-<br>-void i3100_enable(device_t dev)<br>-{<br>- device_t lpc_dev;<br>- u8 func;<br>- volatile u32 *disable;<br>-<br>- if (dev->enabled)<br>- return;<br>-<br>- /*<br>- * To disable an integrated southbridge device, set the corresponding<br>- * flag in the Function Disable register.<br>- */<br>-<br>- /* Temporarily enable the root complex register block at 0xa0000000. */<br>- lpc_dev = dev_find_slot(0x0, PCI_DEVFN(0x1f, 0x0));<br>- pci_write_config32(lpc_dev, 0xf0, 0xa0000000 | (1 << 0));<br>- disable = (volatile u32 *) 0xa0003418;<br>- func = PCI_FUNC(dev->path.pci.devfn);<br>- switch (PCI_SLOT(dev->path.pci.devfn)) {<br>- case 0x1f: /* LPC (fn0), SATA (fn2), SMBus (fn3) */<br>- *disable |= (1 << (func == 0x0 ? 14 : func));<br>- break;<br>- case 0x1d: /* UHCI (fn0, fn1), EHCI (fn7) */<br>- *disable |= (1 << (func + 8));<br>- break;<br>- case 0x1c: /* PCIe ports B0-B3 (fn0-fn3) */<br>- *disable |= (1 << (func + 16));<br>- break;<br>- }<br>- /* Disable the root complex register block. */<br>- pci_write_config32(lpc_dev, 0xf0, 0);<br>-}<br>-<br>-struct chip_operations southbridge_intel_i3100_ops = {<br>- CHIP_NAME("Intel 3100 Southbridge")<br>-};<br>diff --git a/src/southbridge/intel/i3100/i3100.h b/src/southbridge/intel/i3100/i3100.h<br>deleted file mode 100644<br>index 297a2a6..0000000<br>--- a/src/southbridge/intel/i3100/i3100.h<br>+++ /dev/null<br>@@ -1,43 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef SOUTHBRIDGE_INTEL_I3100_I3100_H<br>-#define SOUTHBRIDGE_INTEL_I3100_I3100_H<br>-#include "chip.h"<br>-<br>-#define SATA_CMD 0x04<br>-#define SATA_PI 0x09<br>-#define SATA_PTIM 0x40<br>-#define SATA_STIM 0x42<br>-#define SATA_D1TIM 0x44<br>-#define SATA_SYNCC 0x48<br>-#define SATA_SYNCTIM 0x4A<br>-#define SATA_IIOC 0x54<br>-#define SATA_MAP 0x90<br>-#define SATA_PCS 0x91<br>-#define SATA_ACR0 0xA8<br>-#define SATA_ACR1 0xAC<br>-#define SATA_ATC 0xC0<br>-#define SATA_ATS 0xC4<br>-#define SATA_SP 0xD0<br>-<br>-#define SATA_MODE_IDE 0x00<br>-#define SATA_MODE_AHCI 0x01<br>-<br>-#ifndef __SIMPLE_DEVICE__<br>-void i3100_enable(device_t dev);<br>-#endif<br>-<br>-#endif<br>diff --git a/src/southbridge/intel/i3100/ioapic.c b/src/southbridge/intel/i3100/ioapic.c<br>deleted file mode 100644<br>index a324e7d..0000000<br>--- a/src/southbridge/intel/i3100/ioapic.c<br>+++ /dev/null<br>@@ -1,56 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include "i3100.h"<br>-<br>-<br>-static void read_resources(struct device *dev)<br>-{<br>- u32 tmp;<br>-<br>- /* Enable IO(X)APIC config space */<br>- tmp = pci_read_config16(dev, 0x40);<br>- pci_write_config16(dev, 0x40, tmp & ~(1 << 13));<br>- /* Enable I/O APIC space at 0xfec80000 */<br>- dev->path.pci.devfn |= 1;<br>- pci_write_config16(dev, 0x04, 0x06);<br>- pci_write_config32(dev, 0x10, 0xfec80000);<br>- dev->path.pci.devfn &= ~1;<br>- pci_write_config16(dev, 0x40, tmp);<br>-<br>- pci_bus_read_resources(dev);<br>-}<br>-<br>-static struct device_operations pci_ops = {<br>- .read_resources = read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_bus_enable_resources,<br>- .scan_bus = pci_scan_bridge,<br>- .reset_bus = pci_bus_reset,<br>- .ops_pci = 0,<br>-<br>-};<br>-<br>-static const struct pci_driver pci_driver0 __pci_driver = {<br>- .ops = &pci_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x3500,<br>-};<br>diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c<br>deleted file mode 100644<br>index e3c463b..0000000<br>--- a/src/southbridge/intel/i3100/lpc.c<br>+++ /dev/null<br>@@ -1,471 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2004 Linux Networx<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-/* This code is based on src/southbridge/intel/esb6300/esb6300_lpc.c */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <pc80/mc146818rtc.h><br>-#include <pc80/isa-dma.h><br>-#include <pc80/i8259.h><br>-#include <arch/io.h><br>-#include <arch/ioapic.h><br>-#include <arch/acpi.h><br>-#include "i3100.h"<br>-<br>-#define ACPI_BAR 0x40<br>-#define GPIO_BAR 0x48<br>-#define RCBA 0xf0<br>-<br>-#define SERIRQ_CNTL 0x64<br>-<br>-#define GEN_PMCON_1 0xA0<br>-#define GEN_PMCON_2 0xA2<br>-#define GEN_PMCON_3 0xA4<br>-<br>-#define NMI_OFF 0<br>-#define MAINBOARD_POWER_OFF 0<br>-#define MAINBOARD_POWER_ON 1<br>-<br>-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL<br>-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON<br>-#endif<br>-<br>-static void i3100_enable_serial_irqs(device_t dev)<br>-{<br>- /* set packet length and toggle silent mode bit */<br>- pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));<br>- pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));<br>-}<br>-<br>-typedef struct southbridge_intel_i3100_config config_t;<br>-<br>-static void set_i3100_gpio_use_sel(<br>- device_t dev, struct resource *res, config_t *config)<br>-{<br>- u32 gpio_use_sel, gpio_use_sel2;<br>- int i;<br>-<br>- gpio_use_sel = inl(res->base + 0x00) | 0x0000c603;<br>- gpio_use_sel2 = inl(res->base + 0x30) | 0x00000100;<br>- for (i = 0; i < 64; i++) {<br>- int val;<br>- switch (config->gpio[i] & I3100_GPIO_USE_MASK) {<br>- case I3100_GPIO_USE_AS_NATIVE:<br>- val = 0;<br>- break;<br>- case I3100_GPIO_USE_AS_GPIO:<br>- val = 1;<br>- break;<br>- default:<br>- continue;<br>- }<br>- /* The caller is responsible for not playing with unimplemented bits */<br>- if (i < 32) {<br>- gpio_use_sel &= ~(1 << i);<br>- gpio_use_sel |= (val << i);<br>- } else {<br>- gpio_use_sel2 &= ~(1 << (i - 32));<br>- gpio_use_sel2 |= (val << (i - 32));<br>- }<br>- }<br>- outl(gpio_use_sel, res->base + 0x00);<br>- outl(gpio_use_sel2, res->base + 0x30);<br>-}<br>-<br>-static void set_i3100_gpio_direction(<br>- device_t dev, struct resource *res, config_t *config)<br>-{<br>- u32 gpio_io_sel, gpio_io_sel2;<br>- int i;<br>-<br>- gpio_io_sel = inl(res->base + 0x04);<br>- gpio_io_sel2 = inl(res->base + 0x34);<br>- for (i = 0; i < 64; i++) {<br>- int val;<br>- switch (config->gpio[i] & I3100_GPIO_SEL_MASK) {<br>- case I3100_GPIO_SEL_OUTPUT:<br>- val = 0;<br>- break;<br>- case I3100_GPIO_SEL_INPUT:<br>- val = 1;<br>- break;<br>- default:<br>- continue;<br>- }<br>- /* The caller is responsible for not playing with unimplemented bits */<br>- if (i < 32) {<br>- gpio_io_sel &= ~(1 << i);<br>- gpio_io_sel |= (val << i);<br>- } else {<br>- gpio_io_sel2 &= ~(1 << (i - 32));<br>- gpio_io_sel2 |= (val << (i - 32));<br>- }<br>- }<br>- outl(gpio_io_sel, res->base + 0x04);<br>- outl(gpio_io_sel2, res->base + 0x34);<br>-}<br>-<br>-static void set_i3100_gpio_level(<br>- device_t dev, struct resource *res, config_t *config)<br>-{<br>- u32 gpio_lvl, gpio_lvl2;<br>- u32 gpio_blink;<br>- int i;<br>-<br>- gpio_lvl = inl(res->base + 0x0c);<br>- gpio_blink = inl(res->base + 0x18);<br>- gpio_lvl2 = inl(res->base + 0x38);<br>- for (i = 0; i < 64; i++) {<br>- int val, blink;<br>- switch (config->gpio[i] & I3100_GPIO_LVL_MASK) {<br>- case I3100_GPIO_LVL_LOW:<br>- val = 0;<br>- blink = 0;<br>- break;<br>- case I3100_GPIO_LVL_HIGH:<br>- val = 1;<br>- blink = 0;<br>- break;<br>- case I3100_GPIO_LVL_BLINK:<br>- val = 1;<br>- blink = 1;<br>- break;<br>- default:<br>- continue;<br>- }<br>- /* The caller is responsible for not playing with unimplemented bits */<br>- if (i < 32) {<br>- gpio_lvl &= ~(1 << i);<br>- gpio_blink &= ~(1 << i);<br>- gpio_lvl |= (val << i);<br>- gpio_blink |= (blink << i);<br>- } else {<br>- gpio_lvl2 &= ~(1 << (i - 32));<br>- gpio_lvl2 |= (val << (i - 32));<br>- }<br>- }<br>- outl(gpio_lvl, res->base + 0x0c);<br>- outl(gpio_blink, res->base + 0x18);<br>- outl(gpio_lvl2, res->base + 0x38);<br>-}<br>-<br>-static void set_i3100_gpio_inv(<br>- device_t dev, struct resource *res, config_t *config)<br>-{<br>- u32 gpio_inv;<br>- int i;<br>-<br>- gpio_inv = inl(res->base + 0x2c);<br>- for (i = 0; i < 32; i++) {<br>- int val;<br>- switch (config->gpio[i] & I3100_GPIO_INV_MASK) {<br>- case I3100_GPIO_INV_OFF:<br>- val = 0;<br>- break;<br>- case I3100_GPIO_INV_ON:<br>- val = 1;<br>- break;<br>- default:<br>- continue;<br>- }<br>- gpio_inv &= ~(1 << i);<br>- gpio_inv |= (val << i);<br>- }<br>- outl(gpio_inv, res->base + 0x2c);<br>-}<br>-<br>-static void i3100_pirq_init(device_t dev)<br>-{<br>- device_t irq_dev;<br>- config_t *config;<br>-<br>- /* Get the chip configuration */<br>- config = dev->chip_info;<br>-<br>- if (config->pirq_a_d)<br>- pci_write_config32(dev, 0x60, config->pirq_a_d);<br>-<br>- if (config->pirq_e_h)<br>- pci_write_config32(dev, 0x68, config->pirq_e_h);<br>-<br>- for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {<br>- u8 int_pin=0, int_line=0;<br>-<br>- if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)<br>- continue;<br>-<br>- int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);<br>- switch (int_pin) {<br>- case 1: /* INTA# */<br>- int_line = config->pirq_a_d & 0xff;<br>- break;<br>-<br>- case 2: /* INTB# */<br>- int_line = (config->pirq_a_d >> 8) & 0xff;<br>- break;<br>-<br>- case 3: /* INTC# */<br>- int_line = (config->pirq_a_d >> 16) & 0xff;<br>- break;<br>-<br>- case 4: /* INTD# */<br>- int_line = (config->pirq_a_d >> 24) & 0xff;<br>- break;<br>- }<br>-<br>- if (!int_line)<br>- continue;<br>-<br>- printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line);<br>- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);<br>- }<br>-<br>-<br>-}<br>-<br>-static void i3100_power_options(device_t dev) {<br>- u8 reg8;<br>- u16 reg16;<br>- int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;<br>- int nmi_option;<br>-<br>- /* Which state do we want to goto after g3 (power restored)?<br>- * 0 == S0 Full On<br>- * 1 == S5 Soft Off<br>- */<br>- get_option(&pwr_on, "power_on_after_fail");<br>- reg8 = pci_read_config8(dev, GEN_PMCON_3);<br>- reg8 &= 0xfe;<br>- if (pwr_on) {<br>- reg8 &= ~1;<br>- } else {<br>- reg8 |= 1;<br>- }<br>- /* avoid #S4 assertions */<br>- reg8 |= (3 << 4);<br>- /* minimum asssertion is 1 to 2 RTCCLK */<br>- reg8 &= ~(1 << 3);<br>- pci_write_config8(dev, GEN_PMCON_3, reg8);<br>- printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off");<br>-<br>- /* Set up NMI on errors. */<br>- reg8 = inb(0x61);<br>- /* Higher Nibble must be 0 */<br>- reg8 &= 0x0f;<br>- /* IOCHK# NMI Enable */<br>- reg8 &= ~(1 << 3);<br>- /* PCI SERR# Enable */<br>- // reg8 &= ~(1 << 2);<br>- /* PCI SERR# Disable for now */<br>- reg8 |= (1 << 2);<br>- outb(reg8, 0x61);<br>-<br>- reg8 = inb(0x70);<br>- nmi_option = NMI_OFF;<br>- get_option(&nmi_option, "nmi");<br>- if (nmi_option) {<br>- /* Set NMI. */<br>- printk(BIOS_INFO, "NMI sources enabled.\n");<br>- reg8 &= ~(1 << 7);<br>- } else {<br>- /* Can't mask NMI from PCI-E and NMI_NOW */<br>- printk(BIOS_INFO, "NMI sources disabled.\n");<br>- reg8 |= ( 1 << 7);<br>- }<br>- outb(reg8, 0x70);<br>-<br>- // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down<br>- reg16 = pci_read_config16(dev, GEN_PMCON_1);<br>- reg16 &= ~((3 << 0) | (1 << 10));<br>- reg16 |= (1 << 3) | (1 << 5);<br>- /* CLKRUN_EN */<br>- // reg16 |= (1 << 2);<br>- pci_write_config16(dev, GEN_PMCON_1, reg16);<br>-<br>- // Set the board's GPI routing.<br>- // i82801gx_gpi_routing(dev);<br>-}<br>-<br>-static void i3100_gpio_init(device_t dev)<br>-{<br>- struct resource *res;<br>- config_t *config;<br>-<br>- /* Skip if I don't have any configuration */<br>- if (!dev->chip_info) {<br>- return;<br>- }<br>- /* The programmer is responsible for ensuring<br>- * a valid gpio configuration.<br>- */<br>-<br>- /* Get the chip configuration */<br>- config = dev->chip_info;<br>- /* Find the GPIO bar */<br>- res = find_resource(dev, GPIO_BAR);<br>- if (!res) {<br>- return;<br>- }<br>-<br>- /* Set the use selects */<br>- set_i3100_gpio_use_sel(dev, res, config);<br>-<br>- /* Set the IO direction */<br>- set_i3100_gpio_direction(dev, res, config);<br>-<br>- /* Setup the input inverters */<br>- set_i3100_gpio_inv(dev, res, config);<br>-<br>- /* Set the value on the GPIO output pins */<br>- set_i3100_gpio_level(dev, res, config);<br>-<br>-}<br>-<br>-<br>-static void lpc_init(struct device *dev)<br>-{<br>- struct resource *res;<br>-<br>- /* Enable IO APIC */<br>- res = find_resource(dev, RCBA);<br>- if (!res) {<br>- return;<br>- }<br>- *((u8 *)((u32)res->base + 0x31ff)) |= (1 << 0);<br>-<br>- // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode<br>- // (register 0x10/0x11) while the old code used int 1 (register 0x12)<br>- // ... Why?<br>- setup_ioapic(VIO_APIC_VADDR, 0); // Don't rename IOAPIC ID<br>-<br>- /* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */<br>- pci_write_config32(dev, 0xd0, 0x00000000);<br>-<br>- i3100_enable_serial_irqs(dev);<br>-<br>- /* Set up the PIRQ */<br>- i3100_pirq_init(dev);<br>-<br>- /* Setup power options */<br>- i3100_power_options(dev);<br>-<br>- /* Set the state of the gpio lines */<br>- i3100_gpio_init(dev);<br>-<br>- /* Initialize the real time clock */<br>- cmos_init(0);<br>-<br>- /* Initialize isa dma */<br>- isa_dma_init();<br>-<br>- setup_i8259();<br>- i8259_configure_irq_trigger(9, 1);<br>-}<br>-<br>-static void i3100_lpc_read_resources(device_t dev)<br>-{<br>- struct resource *res;<br>-<br>- /* Get the normal pci resources of this device */<br>- pci_dev_read_resources(dev);<br>-<br>- /* Add the ACPI BAR */<br>- res = pci_get_resource(dev, ACPI_BAR);<br>-<br>- /* Add the GPIO BAR */<br>- res = pci_get_resource(dev, GPIO_BAR);<br>-<br>- /* Add an extra subtractive resource for both memory and I/O. */<br>- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));<br>- res->base = 0;<br>- res->size = 0x1000;<br>- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |<br>- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-<br>- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));<br>- res->base = 0xff800000;<br>- res->size = 0x00800000; /* 8 MB for flash */<br>- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |<br>- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-<br>- res = new_resource(dev, 3); /* IOAPIC */<br>- res->base = IO_APIC_ADDR;<br>- res->size = 0x00001000;<br>- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-<br>- /* Add resource for RCBA */<br>- res = new_resource(dev, RCBA);<br>- res->size = 0x4000;<br>- res->limit = 0xffffc000;<br>- res->align = 14;<br>- res->gran = 14;<br>- res->flags = IORESOURCE_MEM;<br>-}<br>-<br>-static void i3100_lpc_enable_resources(device_t dev)<br>-{<br>- u8 acpi_cntl, gpio_cntl;<br>-<br>- /* Enable the normal pci resources */<br>- pci_dev_enable_resources(dev);<br>-<br>- /* Enable the ACPI bar */<br>- acpi_cntl = pci_read_config8(dev, 0x44);<br>- acpi_cntl |= (1 << 7);<br>- pci_write_config8(dev, 0x44, acpi_cntl);<br>-<br>- /* Enable the GPIO bar */<br>- gpio_cntl = pci_read_config8(dev, 0x4c);<br>- gpio_cntl |= (1 << 4);<br>- pci_write_config8(dev, 0x4c, gpio_cntl);<br>-<br>- /* Enable the RCBA */<br>- pci_write_config32(dev, RCBA, pci_read_config32(dev, RCBA) | (1 << 0));<br>-}<br>-<br>-static struct pci_operations lops_pci = {<br>- .set_subsystem = 0,<br>-};<br>-<br>-static struct device_operations lpc_ops = {<br>- .read_resources = i3100_lpc_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = i3100_lpc_enable_resources,<br>- .init = lpc_init,<br>-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)<br>- .write_acpi_tables = acpi_write_hpet,<br>-#endif<br>- .scan_bus = scan_lpc_bus,<br>- .enable = i3100_enable,<br>- .ops_pci = &lops_pci,<br>-};<br>-<br>-static const struct pci_driver lpc_driver __pci_driver = {<br>- .ops = &lpc_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_LPC,<br>-};<br>-<br>-static const struct pci_driver lpc_driver_ep80579 __pci_driver = {<br>- .ops = &lpc_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_EP80579_LPC,<br>-};<br>diff --git a/src/southbridge/intel/i3100/pci.c b/src/southbridge/intel/i3100/pci.c<br>deleted file mode 100644<br>index 6ad0318..0000000<br>--- a/src/southbridge/intel/i3100/pci.c<br>+++ /dev/null<br>@@ -1,41 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include "i3100.h"<br>-<br>-static void pci_init(struct device *dev)<br>-{<br>-}<br>-<br>-static struct device_operations pci_ops = {<br>- .read_resources = pci_bus_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_bus_enable_resources,<br>- .init = pci_init,<br>- .scan_bus = pci_scan_bridge,<br>- .ops_pci = 0,<br>-};<br>-<br>-static const struct pci_driver pci_driver __pci_driver = {<br>- .ops = &pci_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_PCI,<br>-};<br>diff --git a/src/southbridge/intel/i3100/pciexp_portb.c b/src/southbridge/intel/i3100/pciexp_portb.c<br>deleted file mode 100644<br>index 3782f30..0000000<br>--- a/src/southbridge/intel/i3100/pciexp_portb.c<br>+++ /dev/null<br>@@ -1,91 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <device/pciexp.h><br>-#include <arch/io.h><br>-#include "chip.h"<br>-#include <reset.h><br>-<br>-#define PCIE_LCTL 0x50<br>-#define PCIE_LSTS 0x52<br>-<br>-typedef struct northbridge_intel_i3100_config config_t;<br>-<br>-static void pcie_init(struct device *dev)<br>-{<br>-}<br>-<br>-static void pcie_scan_bridge(struct device *dev)<br>-{<br>- u16 val;<br>- u16 ctl;<br>- int flag = 0;<br>- do {<br>- val = pci_read_config16(dev, PCIE_LSTS);<br>- printk(BIOS_DEBUG, "pcie portb link status: %02x\n", val);<br>- if ((val & (1<<10)) && (!flag)) { /* training error */<br>- ctl = pci_read_config16(dev, PCIE_LCTL);<br>- pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5)));<br>- val = pci_read_config16(dev, PCIE_LSTS);<br>- printk(BIOS_DEBUG, "pcie portb reset link status: %02x\n", val);<br>- flag=1;<br>- hard_reset();<br>- }<br>- } while (val & (3<<10));<br>-<br>- pciexp_scan_bridge(dev);<br>-}<br>-<br>-static struct device_operations pcie_ops = {<br>- .read_resources = pci_bus_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_bus_enable_resources,<br>- .init = pcie_init,<br>- .scan_bus = pcie_scan_bridge,<br>- .reset_bus = pci_bus_reset,<br>- .ops_pci = 0,<br>-};<br>-<br>-static const struct pci_driver pci_driver_0 __pci_driver = {<br>- .ops = &pcie_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0,<br>-};<br>-<br>-static const struct pci_driver pci_driver_1 __pci_driver = {<br>- .ops = &pcie_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1,<br>-};<br>-<br>-static const struct pci_driver pci_driver_2 __pci_driver = {<br>- .ops = &pcie_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2,<br>-};<br>-<br>-static const struct pci_driver pci_driver_3 __pci_driver = {<br>- .ops = &pcie_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3,<br>-};<br>diff --git a/src/southbridge/intel/i3100/reset.c b/src/southbridge/intel/i3100/reset.c<br>deleted file mode 100644<br>index af000e3..0000000<br>--- a/src/southbridge/intel/i3100/reset.c<br>+++ /dev/null<br>@@ -1,23 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-#include <arch/io.h><br>-#include <reset.h><br>-<br>-void do_hard_reset(void)<br>-{<br>- outb(0x06, 0xcf9);<br>-}<br>diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c<br>deleted file mode 100644<br>index 27bd2ce..0000000<br>--- a/src/southbridge/intel/i3100/sata.c<br>+++ /dev/null<br>@@ -1,152 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-/* This code is based on src/southbridge/intel/esb6300/esb6300_sata.c */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include "i3100.h"<br>-<br>-typedef struct southbridge_intel_i3100_config config_t;<br>-<br>-static void sata_init(struct device *dev)<br>-{<br>- u8 ahci;<br>- u32 *ahci_bar;<br>- config_t *config = dev->chip_info;<br>-<br>- if (config == NULL) {<br>- printk(BIOS_ERR, "i3100_sata: error: device not in devicetree.cb!\n");<br>- return;<br>- }<br>-<br>- /* Get the chip configuration */<br>- ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03;<br>-<br>- /* Enable SATA devices */<br>- printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");<br>-<br>- if (ahci) {<br>- /* AHCI mode */<br>- pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));<br>-<br>- /* Enable ports */<br>- pci_write_config8(dev, SATA_PCS, 0x03);<br>- pci_write_config8(dev, SATA_PCS + 1, 0x0F);<br>-<br>- /* Setup timings */<br>- pci_write_config16(dev, SATA_PTIM, 0x8000);<br>- pci_write_config16(dev, SATA_STIM, 0x8000);<br>-<br>- /* Synchronous DMA */<br>- pci_write_config8(dev, SATA_SYNCC, 0);<br>- pci_write_config16(dev, SATA_SYNCTIM, 0);<br>-<br>- /* IDE I/O configuration */<br>- pci_write_config32(dev, SATA_IIOC, 0);<br>-<br>- ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);<br>- ahci_bar[3] = config->sata_ports_implemented;<br>- } else {<br>- /* SATA configuration */<br>- pci_write_config8(dev, SATA_CMD, 0x07);<br>- pci_write_config8(dev, SATA_PI, 0x8f);<br>-<br>- /* Set timings */<br>- pci_write_config16(dev, SATA_PTIM, 0x0a307);<br>- pci_write_config16(dev, SATA_STIM, 0x0a307);<br>-<br>- /* Sync DMA */<br>- pci_write_config8(dev, SATA_SYNCC, 0x0f);<br>- pci_write_config16(dev, SATA_SYNCTIM, 0x1111);<br>-<br>- /* Fast ATA */<br>- pci_write_config16(dev, SATA_IIOC, 0x1000);<br>-<br>- /* Select IDE mode */<br>- pci_write_config8(dev, SATA_MAP, 0x00);<br>-<br>- /* Enable ports 0-3 */<br>- pci_write_config8(dev, SATA_PCS + 1, 0x0f);<br>-<br>- }<br>-<br>- /* secret init sequence, required */<br>- pci_write_config32(dev, 0x94, 0x00400180);<br>- pci_write_config32(dev, 0xa0, 0x18);<br>- pci_write_config32(dev, 0xa4, 0x224);<br>- pci_write_config32(dev, 0xa0, 0x42);<br>- pci_write_config32(dev, 0xa4, 0x22006d);<br>- pci_write_config32(dev, 0xa0, 0x84);<br>- pci_write_config32(dev, 0xa4, 0x24);<br>- pci_write_config32(dev, 0xa0, 0x7a);<br>- pci_write_config32(dev, 0xa4, 0x220000);<br>- pci_write_config32(dev, 0xa0, 0x9c);<br>- pci_write_config32(dev, 0xa4, 0x24);<br>- pci_write_config32(dev, 0xa0, 0x90);<br>- pci_write_config32(dev, 0xa4, 0x220000);<br>- pci_write_config32(dev, 0xa0, 0xa0);<br>- pci_write_config32(dev, 0xa4, 0x12492aa);<br>-<br>- printk(BIOS_DEBUG, "SATA Enabled\n");<br>-}<br>-<br>-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>-}<br>-<br>-static struct pci_operations lops_pci = {<br>- .set_subsystem = sata_set_subsystem,<br>-};<br>-<br>-static struct device_operations sata_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = sata_init,<br>- .scan_bus = 0,<br>- .enable = i3100_enable,<br>- .ops_pci = &lops_pci,<br>-};<br>-<br>-static const struct pci_driver ide_driver __pci_driver = {<br>- .ops = &sata_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_IDE,<br>-};<br>-<br>-static const struct pci_driver sata_driver __pci_driver = {<br>- .ops = &sata_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_AHCI,<br>-};<br>-<br>-static const struct pci_driver ide_driver_ep80579 __pci_driver = {<br>- .ops = &sata_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_EP80579_IDE,<br>-};<br>-<br>-static const struct pci_driver sata_driver_ep80579 __pci_driver = {<br>- .ops = &sata_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_EP80579_AHCI,<br>-};<br>diff --git a/src/southbridge/intel/i3100/smbus.c b/src/southbridge/intel/i3100/smbus.c<br>deleted file mode 100644<br>index 850982a..0000000<br>--- a/src/southbridge/intel/i3100/smbus.c<br>+++ /dev/null<br>@@ -1,89 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-#include <device/device.h><br>-#include <device/path.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <device/smbus.h><br>-#include <arch/io.h><br>-#include <southbridge/intel/common/smbus.h><br>-#include "i3100.h"<br>-<br>-static int lsmbus_read_byte(device_t dev, u8 address)<br>-{<br>- u16 device;<br>- struct resource *res;<br>- struct bus *pbus;<br>-<br>- device = dev->path.i2c.device;<br>- pbus = get_pbus_smbus(dev);<br>- res = find_resource(pbus->dev, 0x20);<br>-<br>- return do_smbus_read_byte(res->base, device, address);<br>-}<br>-<br>-static int lsmbus_write_byte(device_t dev, u8 address, u8 byte)<br>-{<br>- u16 device;<br>- struct resource *res;<br>- struct bus *pbus;<br>-<br>- device = dev->path.i2c.device;<br>- pbus = get_pbus_smbus(dev);<br>- res = find_resource(pbus->dev, 0x20);<br>-<br>- return do_smbus_write_byte(res->base, device, address, byte);<br>-}<br>-<br>-static struct smbus_bus_operations lops_smbus_bus = {<br>- .read_byte = lsmbus_read_byte,<br>- .write_byte = lsmbus_write_byte,<br>-};<br>-<br>-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>-}<br>-<br>-static struct pci_operations lops_pci = {<br>- .set_subsystem = &smbus_set_subsystem,<br>-};<br>-<br>-static struct device_operations smbus_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = 0,<br>- .scan_bus = scan_smbus,<br>- .enable = i3100_enable,<br>- .ops_pci = &lops_pci,<br>- .ops_smbus_bus = &lops_smbus_bus,<br>-};<br>-<br>-static const struct pci_driver smbus_driver __pci_driver = {<br>- .ops = &smbus_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_SMB,<br>-};<br>-<br>-static const struct pci_driver smbus_driver_ep80579 __pci_driver = {<br>- .ops = &smbus_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_EP80579_SMB,<br>-};<br>diff --git a/src/southbridge/intel/i3100/uhci.c b/src/southbridge/intel/i3100/uhci.c<br>deleted file mode 100644<br>index befde92..0000000<br>--- a/src/southbridge/intel/i3100/uhci.c<br>+++ /dev/null<br>@@ -1,64 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include "i3100.h"<br>-<br>-static void uhci_init(struct device *dev)<br>-{<br>-}<br>-<br>-static void uhci_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>-}<br>-<br>-static struct pci_operations lops_pci = {<br>- .set_subsystem = &uhci_set_subsystem,<br>-};<br>-<br>-static struct device_operations uhci_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = uhci_init,<br>- .scan_bus = 0,<br>- .enable = i3100_enable,<br>- .ops_pci = &lops_pci,<br>-};<br>-<br>-static const struct pci_driver uhci_driver __pci_driver = {<br>- .ops = &uhci_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_UHCI,<br>-};<br>-<br>-static const struct pci_driver usb2_driver __pci_driver = {<br>- .ops = &uhci_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_3100_UHCI2,<br>-};<br>-<br>-static const struct pci_driver uhci_driver_ep80579 __pci_driver = {<br>- .ops = &uhci_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_EP80579_UHCI,<br>-};<br>diff --git a/src/superio/intel/i3100/Kconfig b/src/superio/intel/i3100/Kconfig<br>deleted file mode 100644<br>index e797bd7..0000000<br>--- a/src/superio/intel/i3100/Kconfig<br>+++ /dev/null<br>@@ -1,17 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2009 Ronald G. Minnich<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-config SUPERIO_INTEL_I3100<br>- bool<br>diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc<br>deleted file mode 100644<br>index 840483d..0000000<br>--- a/src/superio/intel/i3100/Makefile.inc<br>+++ /dev/null<br>@@ -1,18 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2008 Arastra, Inc.<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; either version 2 of the License, or<br>-## (at your option) any later version.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c<br>-ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c<br>diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c<br>deleted file mode 100644<br>index 0b0bb26..0000000<br>--- a/src/superio/intel/i3100/early_serial.c<br>+++ /dev/null<br>@@ -1,54 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <device/pnp.h><br>-#include <stdint.h><br>-#include "i3100.h"<br>-<br>-static void pnp_enter_ext_func_mode(pnp_devfn_t dev)<br>-{<br>- u16 port = dev >> 8;<br>-<br>- outb(0x80, port);<br>- outb(0x86, port);<br>-}<br>-<br>-static void pnp_exit_ext_func_mode(pnp_devfn_t dev)<br>-{<br>- u16 port = dev >> 8;<br>-<br>- outb(0x68, port);<br>- outb(0x08, port);<br>-}<br>-<br>-/* Enable device interrupts, set UART_CLK predivide. */<br>-void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide)<br>-{<br>- pnp_enter_ext_func_mode(dev);<br>- pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1);<br>- pnp_exit_ext_func_mode(dev);<br>-}<br>-<br>-void i3100_enable_serial(pnp_devfn_t dev, u16 iobase)<br>-{<br>- pnp_enter_ext_func_mode(dev);<br>- pnp_set_logical_device(dev);<br>- pnp_set_enable(dev, 0);<br>- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);<br>- pnp_set_enable(dev, 1);<br>- pnp_exit_ext_func_mode(dev);<br>-}<br>diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h<br>deleted file mode 100644<br>index fa71c05..0000000<br>--- a/src/superio/intel/i3100/i3100.h<br>+++ /dev/null<br>@@ -1,66 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef SUPERIO_INTEL_I3100_H<br>-#define SUPERIO_INTEL_I3100_H<br>-<br>-/*<br>- * Datasheet:<br>- * - Name: Intel 3100 Chipset<br>- * - URL: http://www.intel.com/design/intarch/datashts/313458.htm<br>- * - PDF: http://download.intel.com/design/intarch/datashts/31345803.pdf<br>- * - Revision / Date: 007, October 2008<br>- * - Order number: 313458-007US<br>- */<br>-<br>-/*<br>- * The SIW ("Serial I/O and Watchdog Timer") integrated into the i3100 is<br>- * very similar to a Super I/O, both in functionality and config mechanism.<br>- *<br>- * The SIW contains:<br>- * - UART(s)<br>- * - Serial interrupt controller<br>- * - Watchdog timer (WDT)<br>- * - LPC interface<br>- */<br>-<br>-/* Logical device numbers (LDNs). */<br>-#define I3100_SP1 0x04 /* Com1 */<br>-#define I3100_SP2 0x05 /* Com2 */<br>-#define I3100_WDT 0x06 /* Watchdog timer */<br>-<br>-/* Registers and bit definitions: */<br>-<br>-#define I3100_SIW_CONFIGURATION 0x29<br>-<br>-/*<br>- * SIW_CONFIGURATION[3:2] = UART_CLK predivide<br>- * 00: divide by 1<br>- * 01: divide by 8<br>- * 10: divide by 26<br>- * 11: reserved<br>- */<br>-#define I3100_UART_CLK_PREDIVIDE_1 0x00<br>-#define I3100_UART_CLK_PREDIVIDE_8 0x01<br>-#define I3100_UART_CLK_PREDIVIDE_26 0x02<br>-<br>-#include <arch/io.h><br>-#include <stdint.h><br>-<br>-void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide);<br>-void i3100_enable_serial(pnp_devfn_t dev, u16 iobase);<br>-<br>-#endif /* SUPERIO_INTEL_I3100_H */<br>diff --git a/src/superio/intel/i3100/superio.c b/src/superio/intel/i3100/superio.c<br>deleted file mode 100644<br>index 1055b7a..0000000<br>--- a/src/superio/intel/i3100/superio.c<br>+++ /dev/null<br>@@ -1,68 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Arastra, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdlib.h><br>-#include <device/device.h><br>-#include <device/pnp.h><br>-#include "i3100.h"<br>-#include <arch/io.h><br>-<br>-static void pnp_enter_ext_func_mode(struct device *dev)<br>-{<br>- outb(0x80, dev->path.pnp.port);<br>- outb(0x86, dev->path.pnp.port);<br>-}<br>-<br>-static void pnp_exit_ext_func_mode(struct device *dev)<br>-{<br>- outb(0x68, dev->path.pnp.port);<br>- outb(0x08, dev->path.pnp.port);<br>-}<br>-<br>-static void i3100_init(struct device *dev)<br>-{<br>- if (!dev->enabled)<br>- return;<br>-}<br>-<br>-static const struct pnp_mode_ops pnp_conf_mode_ops = {<br>- .enter_conf_mode = pnp_enter_ext_func_mode,<br>- .exit_conf_mode = pnp_exit_ext_func_mode,<br>-};<br>-<br>-static struct device_operations ops = {<br>- .read_resources = pnp_read_resources,<br>- .set_resources = pnp_set_resources,<br>- .enable_resources = pnp_enable_resources,<br>- .enable = pnp_alt_enable,<br>- .init = i3100_init,<br>- .ops_pnp_mode = &pnp_conf_mode_ops,<br>-};<br>-<br>-static struct pnp_info pnp_dev_info[] = {<br>- { &ops, I3100_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },<br>- { &ops, I3100_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },<br>-};<br>-<br>-static void enable_dev(struct device *dev)<br>-{<br>- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);<br>-}<br>-<br>-struct chip_operations superio_intel_i3100_ops = {<br>- CHIP_NAME("Intel 3100 Super I/O")<br>- .enable_dev = enable_dev,<br>-};<br></pre><p>To view, visit <a href="https://review.coreboot.org/22031">change 22031</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22031"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb </div>
<div style="display:none"> Gerrit-Change-Number: 22031 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>