<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22030">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Intel i5000 board & chips: Remove - using LATE_CBMEM_INIT<br><br>All boards and chips that are still using LATE_CBMEM_INIT are being<br>removed as previously discussed.<br><br>If these boards and chips are updated to not use LATE_CBMEM_INIT, they<br>can be restored to the active codebase from the 4.8 branch.<br><br>chips:<br>northbridge/intel/i5000<br><br>Mainboards:<br>mainboard/supermicro/x7db8<br>mainboard/asus/dsbf<br><br>Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00<br>Signed-off-by: Martin Roth <gaumless@gmail.com><br>---<br>M src/cpu/intel/Makefile.inc<br>D src/cpu/intel/socket_LGA771/Kconfig<br>D src/cpu/intel/socket_LGA771/Makefile.inc<br>D src/mainboard/asus/dsbf/Kconfig<br>D src/mainboard/asus/dsbf/Kconfig.name<br>D src/mainboard/asus/dsbf/board_info.txt<br>D src/mainboard/asus/dsbf/cmos.layout<br>D src/mainboard/asus/dsbf/devicetree.cb<br>D src/mainboard/asus/dsbf/irq_tables.c<br>D src/mainboard/asus/dsbf/romstage.c<br>D src/mainboard/supermicro/x7db8/Kconfig<br>D src/mainboard/supermicro/x7db8/Kconfig.name<br>D src/mainboard/supermicro/x7db8/board_info.txt<br>D src/mainboard/supermicro/x7db8/cmos.layout<br>D src/mainboard/supermicro/x7db8/devicetree.cb<br>D src/mainboard/supermicro/x7db8/irq_tables.c<br>D src/mainboard/supermicro/x7db8/romstage.c<br>D src/northbridge/intel/i5000/Kconfig<br>D src/northbridge/intel/i5000/Makefile.inc<br>D src/northbridge/intel/i5000/bootblock.c<br>D src/northbridge/intel/i5000/halt_second_bsp.S<br>D src/northbridge/intel/i5000/northbridge.c<br>D src/northbridge/intel/i5000/raminit.c<br>D src/northbridge/intel/i5000/raminit.h<br>24 files changed, 0 insertions(+), 3,469 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/22030/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc<br>index 1874075..3c94a71 100644<br>--- a/src/cpu/intel/Makefile.inc<br>+++ b/src/cpu/intel/Makefile.inc<br>@@ -16,7 +16,6 @@<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603<br>-subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989<br>@@ -30,7 +29,6 @@<br> subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2<br> subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1155) += socket_LGA1155<br>-subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775<br> <br> #socket_mPGA604_533Mhz<br>diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig<br>deleted file mode 100644<br>index d9bd44d..0000000<br>--- a/src/cpu/intel/socket_LGA771/Kconfig<br>+++ /dev/null<br>@@ -1,18 +0,0 @@<br>-config CPU_INTEL_SOCKET_LGA771<br>- bool<br>- select CPU_INTEL_MODEL_6FX<br>- select SSE2<br>- select MMX<br>- select AP_IN_SIPI_WAIT<br>-<br>-if CPU_INTEL_SOCKET_LGA771<br>-<br>-config DCACHE_RAM_BASE<br>- hex<br>- default 0xfefc0000<br>-<br>-config DCACHE_RAM_SIZE<br>- hex<br>- default 0x8000<br>-<br>-endif<br>diff --git a/src/cpu/intel/socket_LGA771/Makefile.inc b/src/cpu/intel/socket_LGA771/Makefile.inc<br>deleted file mode 100644<br>index d0a5b63..0000000<br>--- a/src/cpu/intel/socket_LGA771/Makefile.inc<br>+++ /dev/null<br>@@ -1,12 +0,0 @@<br>-subdirs-y += ../model_6ex<br>-subdirs-y += ../model_6fx<br>-subdirs-y += ../../x86/tsc<br>-subdirs-y += ../../x86/mtrr<br>-subdirs-y += ../../x86/lapic<br>-subdirs-y += ../../x86/cache<br>-subdirs-y += ../../x86/smm<br>-subdirs-y += ../microcode<br>-subdirs-y += ../hyperthreading<br>-<br>-cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc<br>-romstage-y += ../car/romstage.c<br>diff --git a/src/mainboard/asus/dsbf/Kconfig b/src/mainboard/asus/dsbf/Kconfig<br>deleted file mode 100644<br>index fa0b659..0000000<br>--- a/src/mainboard/asus/dsbf/Kconfig<br>+++ /dev/null<br>@@ -1,34 +0,0 @@<br>-if BOARD_ASUS_DSBF<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_INTEL_SOCKET_LGA771<br>- select SOUTHBRIDGE_INTEL_I3100<br>- select NORTHBRIDGE_INTEL_I5000<br>- select SUPERIO_WINBOND_W83627HF<br>- select BOARD_ROMSIZE_KB_512<br>- select HAVE_PIRQ_TABLE<br>- select DRIVERS_I2C_W83793<br>- select DRIVERS_GENERIC_IOAPIC<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default asus/dsbf<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "DSBF"<br>-<br>-config MMCONF_BASE_ADDRESS<br>- hex<br>- default 0xe0000000<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 48<br>-<br>-config MAX_CPUS<br>- int<br>- default 8<br>-<br>-endif<br>diff --git a/src/mainboard/asus/dsbf/Kconfig.name b/src/mainboard/asus/dsbf/Kconfig.name<br>deleted file mode 100644<br>index 9bacd4f..0000000<br>--- a/src/mainboard/asus/dsbf/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_ASUS_DSBF<br>- bool "DSBF"<br>diff --git a/src/mainboard/asus/dsbf/board_info.txt b/src/mainboard/asus/dsbf/board_info.txt<br>deleted file mode 100644<br>index 3d902b6..0000000<br>--- a/src/mainboard/asus/dsbf/board_info.txt<br>+++ /dev/null<br>@@ -1 +0,0 @@<br>-Category: server<br>diff --git a/src/mainboard/asus/dsbf/cmos.layout b/src/mainboard/asus/dsbf/cmos.layout<br>deleted file mode 100644<br>index 6f5898e..0000000<br>--- a/src/mainboard/asus/dsbf/cmos.layout<br>+++ /dev/null<br>@@ -1,104 +0,0 @@<br>-#<br>-# This file is part of the coreboot project.<br>-#<br>-# Copyright (C) 2007-2008 coresystems GmbH<br>-#<br>-# This program is free software; you can redistribute it and/or<br>-# modify it under the terms of the GNU General Public License as<br>-# published by the Free Software Foundation; version 2 of<br>-# the License.<br>-#<br>-# This program is distributed in the hope that it will be useful,<br>-# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-# GNU General Public License for more details.<br>-#<br>-<br>-# -----------------------------------------------------------------<br>-entries<br>-<br>-# -----------------------------------------------------------------<br>-# Status Register A<br>-# -----------------------------------------------------------------<br>-# Status Register B<br>-# -----------------------------------------------------------------<br>-# Status Register C<br>-#96 4 r 0 status_c_rsvd<br>-#100 1 r 0 uf_flag<br>-#101 1 r 0 af_flag<br>-#102 1 r 0 pf_flag<br>-#103 1 r 0 irqf_flag<br>-# -----------------------------------------------------------------<br>-# Status Register D<br>-#104 7 r 0 status_d_rsvd<br>-#111 1 r 0 valid_cmos_ram<br>-# -----------------------------------------------------------------<br>-# Diagnostic Status Register<br>-#112 8 r 0 diag_rsvd1<br>-<br>-# -----------------------------------------------------------------<br>-0 120 r 0 reserved_memory<br>-#120 264 r 0 unused<br>-<br>-# -----------------------------------------------------------------<br>-# RTC_BOOT_BYTE (coreboot hardcoded)<br>-384 1 e 4 boot_option<br>-388 4 h 0 reboot_counter<br>-#390 2 r 0 unused?<br>-<br>-# -----------------------------------------------------------------<br>-# coreboot config options: console<br>-#392 3 r 0 unused<br>-395 4 e 6 debug_level<br>-#399 1 r 0 unused<br>-<br>-# coreboot config options: cpu<br>-400 1 e 2 hyper_threading<br>-#401 7 r 0 unused<br>-<br>-# coreboot config options: southbridge<br>-408 1 e 1 nmi<br>-#409 2 e 7 power_on_after_fail<br>-#411 5 r 0 unused<br>-<br>-# coreboot config options: bootloader<br>-416 512 s 0 boot_devices<br>-928 8 h 0 boot_default<br>-936 1 e 8 cmos_defaults_loaded<br>-937 1 e 1 lpt<br>-#938 46 r 0 unused<br>-<br>-# coreboot config options: check sums<br>-984 16 h 0 check_sum<br>-<br>-# -----------------------------------------------------------------<br>-<br>-enumerations<br>-<br>-#ID value text<br>-1 0 Disable<br>-1 1 Enable<br>-2 0 Enable<br>-2 1 Disable<br>-4 0 Fallback<br>-4 1 Normal<br>-6 1 Emergency<br>-6 2 Alert<br>-6 3 Critical<br>-6 4 Error<br>-6 5 Warning<br>-6 6 Notice<br>-6 7 Info<br>-6 8 Debug<br>-6 9 Spew<br>-7 0 Disable<br>-7 1 Enable<br>-7 2 Keep<br>-8 0 No<br>-8 1 Yes<br>-9 0 Secondary<br>-9 1 Primary<br>-# -----------------------------------------------------------------<br>-checksums<br>-<br>-checksum 392 983 984<br>diff --git a/src/mainboard/asus/dsbf/devicetree.cb b/src/mainboard/asus/dsbf/devicetree.cb<br>deleted file mode 100644<br>index e8dcae7..0000000<br>--- a/src/mainboard/asus/dsbf/devicetree.cb<br>+++ /dev/null<br>@@ -1,180 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2007-2009 coresystems GmbH<br>-## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org><br>-##<br>-## This program is free software; you can redistribute it and/or<br>-## modify it under the terms of the GNU General Public License as<br>-## published by the Free Software Foundation; version 2 of<br>-## the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-chip northbridge/intel/i5000<br>-<br>- device cpu_cluster 0 on<br>- chip cpu/intel/socket_LGA771<br>- device lapic 0 on end<br>- end<br>- end<br>-<br>- device domain 0 on<br>- device pci 00.0 on # Host bridge<br>- subsystemid 0x1043 0x81db<br>- end<br>-<br>- device pci 02.0 on # PCI Express x8 Port 2-3<br>- ioapic_irq 8 INTA 0x10<br>- ioapic_irq 8 INTB 0x11<br>- ioapic_irq 8 INTC 0x12<br>- ioapic_irq 8 INTD 0x13<br>- device pci 00.0 on # PCI Express Upstream Port<br>- device pci 00.0 on # PCI Express Downstream Port E1<br>- device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A<br>- ioapic_irq 8 INTA 0x11<br>- ioapic_irq 8 INTB 0x10<br>- ioapic_irq 8 INTC 0x11<br>- ioapic_irq 8 INTD 0x10<br>- # PCI slot<br>- device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B<br>- # PCI slot<br>- end<br>- end<br>- end<br>- device pci 00.1 on end<br>- device pci 00.3 on # PCI Express to PCI-X Bridge<br>- ioapic_irq 9 INTA 3<br>- ioapic_irq 9 INTB 0<br>- ioapic_irq 9 INTC 1<br>- ioapic_irq 9 INTD 2<br>- # PCI-X Slot<br>- end<br>-<br>- end<br>- end<br>-<br>- device pci 03.0 on<br>- ioapic_irq 8 INTA 0x10<br>- end<br>- device pci 04.0 on<br>- ioapic_irq 8 INTA 0x10<br>- end<br>- device pci 05.0 on<br>- ioapic_irq 8 INTA 0x10<br>- end<br>- device pci 06.0 on<br>- ioapic_irq 8 INTA 0x10<br>- end<br>- device pci 07.0 on<br>- ioapic_irq 8 INTA 0x10<br>- end<br>-<br>- device pci 10.0 on end # FBD<br>- device pci 10.1 on end # FBD<br>- device pci 10.2 on end # FBD<br>- device pci 11.0 on end # FBD reserved<br>- device pci 13.0 on end # FBD reserved<br>- device pci 15.0 on end # FBD<br>- device pci 16.0 on end # FBD<br>-<br>- chip drivers/generic/ioapic<br>- register "have_isa_interrupts" = "1"<br>- register "irq_on_fsb" = "1"<br>- register "enable_virtual_wire" = "1"<br>- register "base" = "(void *)0xfec00000"<br>- device ioapic 8 on end<br>- end<br>-<br>- chip drivers/generic/ioapic<br>- register "irq_on_fsb" = "1"<br>- register "base" = "(void *)0xfec80000"<br>- device ioapic 9 on end<br>- end<br>-<br>- chip southbridge/intel/i3100<br>- register "pirq_a_d" = "0x0b0b0b0b"<br>- register "pirq_e_h" = "0x80808080"<br>- register "sata_ports_implemented" = "0x3f"<br>-<br>- device pci 1c.0 on<br>- ioapic_irq 8 INTA 0x14<br>- ioapic_irq 8 INTB 0x15<br>- ioapic_irq 8 INTC 0x16<br>- ioapic_irq 8 INTD 0x17<br>- end # PCIe bridge<br>- device pci 1d.0 on<br>- ioapic_irq 8 INTA 0x10<br>- end # USB UHCI<br>- device pci 1d.1 on<br>- ioapic_irq 8 INTB 0x11<br>- end # USB UHCI<br>- device pci 1d.2 on<br>- ioapic_irq 8 INTC 0x12<br>- end # USB UHCI<br>- device pci 1d.3 on<br>- ioapic_irq 8 INTD 0x13<br>- end # USB UHCI<br>- device pci 1d.7 on end # USB2 EHCI<br>- device pci 1e.0 on<br>- device pci 01.0 on end<br>- end<br>-<br>- device pci 1f.0 on # PCI-LPC bridge<br>- ioapic_irq 8 INTA 0x11<br>- chip superio/winbond/w83627hf<br>- device pnp 2e.0 off end # FDC<br>- device pnp 2e.1 on # Parallel Port<br>- io 0x60 = 0x378<br>- irq 0x70 = 7<br>- end<br>- device pnp 2e.2 on # Serial Port 1<br>- io 0x60 = 0x3f8<br>- irq 0x70 = 4<br>- end<br>-<br>- device pnp 2e.3 off end<br>- device pnp 2e.5 on # KBC<br>- io 0x60 = 0x60<br>- io 0x62 = 0x64<br>- irq 0x70 = 1<br>- irq 0x72 = 12<br>- end<br>-<br>- device pnp 2e.6 off end # CIR<br>- device pnp 2e.7 off end # Game port / MIDI<br>- device pnp 2e.8 off end # GPIO2<br>- device pnp 2e.9 on end # GPIO3<br>- device pnp 2e.a on end # ACPI<br>- device pnp 2e.b off end # HWMON<br>- end<br>- end<br>- device pci 1f.1 off end # IDE<br>- device pci 1f.2 on end # SATA<br>- device pci 1f.3 on # SMBUS<br>- chip drivers/i2c/w83793<br>- register "mfc" = "0x28"<br>- register "fanin" = "0x1f"<br>- register "peci_agent_conf" = "0x33"<br>- register "tcase0" = "0x5e"<br>- register "tcase1" = "0x5e"<br>- register "tcase2" = "0x5e"<br>- register "tcase3" = "0x5e"<br>- register "tr_enable" = "0x01"<br>- register "critical_temperature" = "0x7f"<br>- register "td1_fan_select" = "0x09"<br>- register "td2_fan_select" = "0x09"<br>- register "td3_fan_select" = "0x09"<br>- register "td4_fan_select" = "0x09"<br>- register "tr1_fan_select" = "0x09"<br>- register "tr2_fan_select" = "0x09"<br>- device i2c 0x2f on end<br>- end<br>- end<br>- end<br>- end<br>-end<br>diff --git a/src/mainboard/asus/dsbf/irq_tables.c b/src/mainboard/asus/dsbf/irq_tables.c<br>deleted file mode 100644<br>index 9a2e09d..0000000<br>--- a/src/mainboard/asus/dsbf/irq_tables.c<br>+++ /dev/null<br>@@ -1,53 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */<br>- 0x00, /* Interrupt router bus */<br>- (0x1f << 3) | 0x0, /* Interrupt router dev */<br>- 0, /* IRQs devoted exclusively to PCI usage */<br>- 0x8086, /* Vendor */<br>- 0x2670, /* Device */<br>- 0, /* Miniport */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0, /* Checksum (has to be set to some value that<br>- * would give 0 after the sum of all bytes<br>- * for this structure (including checksum).<br>- */<br>- {<br>- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},<br>- {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},<br>- {0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- }<br>-};<br>-<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c<br>deleted file mode 100644<br>index 273b6d2..0000000<br>--- a/src/mainboard/asus/dsbf/romstage.c<br>+++ /dev/null<br>@@ -1,139 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org><br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <string.h><br>-#include <arch/io.h><br>-#include <device/pci_def.h><br>-#include <device/pnp_def.h><br>-#include <cpu/x86/lapic.h><br>-#include <lib.h><br>-#include <console/console.h><br>-#include <cpu/x86/bist.h><br>-#include <cpu/intel/romstage.h><br>-#include <superio/winbond/common/winbond.h><br>-#include <superio/winbond/w83627hf/w83627hf.h><br>-#include <northbridge/intel/i5000/raminit.h><br>-#include <northbridge/intel/i3100/i3100.h><br>-#include <southbridge/intel/i3100/i3100.h><br>-#include <southbridge/intel/i3100/early_smbus.c><br>-<br>-#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)<br>-#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)<br>-<br>-#define RCBA_RPC 0x0224 /* 32 bit */<br>-#define RCBA_HPTC 0x3404 /* 32 bit */<br>-#define RCBA_GCS 0x3410 /* 32 bit */<br>-#define RCBA_FD 0x3418 /* 32 bit */<br>-<br>-static void early_config(void)<br>-{<br>- u32 gcs, rpc, fd;<br>-<br>- /* Enable RCBA */<br>- pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);<br>-<br>- /* Disable watchdog */<br>- gcs = read32(DEFAULT_RCBA + RCBA_GCS);<br>- gcs |= (1 << 5); /* No reset */<br>- write32(DEFAULT_RCBA + RCBA_GCS, gcs);<br>-<br>- /* Configure PCIe port B as 4x */<br>- rpc = read32(DEFAULT_RCBA + RCBA_RPC);<br>- rpc |= (3 << 0);<br>- write32(DEFAULT_RCBA + RCBA_RPC, rpc);<br>-<br>- /* Disable Modem, Audio, PCIe ports 2/3/4 */<br>- fd = read32(DEFAULT_RCBA + RCBA_FD);<br>- fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);<br>- write32(DEFAULT_RCBA + RCBA_FD, fd);<br>-<br>- /* Enable HPET */<br>- write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));<br>-<br>- /* Setup sata mode */<br>- pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40);<br>-}<br>-<br>-#define DEFAULT_GPIOBASE 0x1180<br>-static void setup_gpio(void)<br>-{<br>- pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1);<br>- pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4));<br>-<br>- outl(0x1b0ce7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */<br>- outl(0xec00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */<br>- outl(0xff350000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */<br>- outl(0x0000e742, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */<br>- outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */<br>- outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */<br>- outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */<br>-<br>-}<br>-<br>-static void i5000_lpc_config(void)<br>-{<br>- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);<br>-}<br>-<br>-int mainboard_set_fbd_clock(int speed)<br>-{<br>- switch(speed) {<br>- case 533:<br>- smbus_write_byte(0x6f, 0x80, 0x21);<br>- return 0;<br>- case 667:<br>- smbus_write_byte(0x6f, 0x80, 0x23);<br>- return 0;<br>- default:<br>- printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed);<br>- die("");<br>- return -1;<br>- }<br>-}<br>-<br>-void mainboard_romstage_entry(unsigned long bist)<br>-{<br>- if (bist == 0)<br>- enable_lapic();<br>-<br>- i5000_lpc_config();<br>-<br>- winbond_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);<br>-<br>- console_init();<br>-<br>- /* Halt if there was a built in self test failure */<br>- report_bist_failure(bist);<br>-<br>- early_config();<br>-<br>- setup_gpio();<br>-<br>- enable_smbus();<br>-<br>- smbus_write_byte(0x6f, 0x00, 0x63);<br>- smbus_write_byte(0x6f, 0x01, 0x04);<br>- smbus_write_byte(0x6f, 0x02, 0x53);<br>- smbus_write_byte(0x6f, 0x03, 0x39);<br>- smbus_write_byte(0x6f, 0x08, 0x06);<br>- smbus_write_byte(0x6f, 0x09, 0x00);<br>-<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1);<br>- i5000_fbdimm_init();<br>- smbus_write_byte(0x69, 0x01, 0x01);<br>-}<br>diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig<br>deleted file mode 100644<br>index fd71254..0000000<br>--- a/src/mainboard/supermicro/x7db8/Kconfig<br>+++ /dev/null<br>@@ -1,34 +0,0 @@<br>-if BOARD_SUPERMICRO_X7DB8<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_INTEL_SOCKET_LGA771<br>- select SOUTHBRIDGE_INTEL_I3100<br>- select NORTHBRIDGE_INTEL_I5000<br>- select SUPERIO_WINBOND_W83627HF<br>- select BOARD_ROMSIZE_KB_512<br>- select HAVE_PIRQ_TABLE<br>- select DRIVERS_I2C_W83793<br>- select DRIVERS_GENERIC_IOAPIC<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default supermicro/x7db8<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "X7DB8 / X7DB8+"<br>-<br>-config MMCONF_BASE_ADDRESS<br>- hex<br>- default 0xe0000000<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 48<br>-<br>-config MAX_CPUS<br>- int<br>- default 8<br>-<br>-endif<br>diff --git a/src/mainboard/supermicro/x7db8/Kconfig.name b/src/mainboard/supermicro/x7db8/Kconfig.name<br>deleted file mode 100644<br>index b964bcf..0000000<br>--- a/src/mainboard/supermicro/x7db8/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_SUPERMICRO_X7DB8<br>- bool "X7DB8 / X7DB8+"<br>diff --git a/src/mainboard/supermicro/x7db8/board_info.txt b/src/mainboard/supermicro/x7db8/board_info.txt<br>deleted file mode 100644<br>index fee61ac..0000000<br>--- a/src/mainboard/supermicro/x7db8/board_info.txt<br>+++ /dev/null<br>@@ -1,5 +0,0 @@<br>-Category: server<br>-Board URL: http://www.supermicro.com/products/motherboard/xeon1333/5000p/x7db8_.cfm<br>-ROM package: PLCC32<br>-ROM protocol: FWH<br>-ROM socketed: y<br>diff --git a/src/mainboard/supermicro/x7db8/cmos.layout b/src/mainboard/supermicro/x7db8/cmos.layout<br>deleted file mode 100644<br>index 6f5898e..0000000<br>--- a/src/mainboard/supermicro/x7db8/cmos.layout<br>+++ /dev/null<br>@@ -1,104 +0,0 @@<br>-#<br>-# This file is part of the coreboot project.<br>-#<br>-# Copyright (C) 2007-2008 coresystems GmbH<br>-#<br>-# This program is free software; you can redistribute it and/or<br>-# modify it under the terms of the GNU General Public License as<br>-# published by the Free Software Foundation; version 2 of<br>-# the License.<br>-#<br>-# This program is distributed in the hope that it will be useful,<br>-# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-# GNU General Public License for more details.<br>-#<br>-<br>-# -----------------------------------------------------------------<br>-entries<br>-<br>-# -----------------------------------------------------------------<br>-# Status Register A<br>-# -----------------------------------------------------------------<br>-# Status Register B<br>-# -----------------------------------------------------------------<br>-# Status Register C<br>-#96 4 r 0 status_c_rsvd<br>-#100 1 r 0 uf_flag<br>-#101 1 r 0 af_flag<br>-#102 1 r 0 pf_flag<br>-#103 1 r 0 irqf_flag<br>-# -----------------------------------------------------------------<br>-# Status Register D<br>-#104 7 r 0 status_d_rsvd<br>-#111 1 r 0 valid_cmos_ram<br>-# -----------------------------------------------------------------<br>-# Diagnostic Status Register<br>-#112 8 r 0 diag_rsvd1<br>-<br>-# -----------------------------------------------------------------<br>-0 120 r 0 reserved_memory<br>-#120 264 r 0 unused<br>-<br>-# -----------------------------------------------------------------<br>-# RTC_BOOT_BYTE (coreboot hardcoded)<br>-384 1 e 4 boot_option<br>-388 4 h 0 reboot_counter<br>-#390 2 r 0 unused?<br>-<br>-# -----------------------------------------------------------------<br>-# coreboot config options: console<br>-#392 3 r 0 unused<br>-395 4 e 6 debug_level<br>-#399 1 r 0 unused<br>-<br>-# coreboot config options: cpu<br>-400 1 e 2 hyper_threading<br>-#401 7 r 0 unused<br>-<br>-# coreboot config options: southbridge<br>-408 1 e 1 nmi<br>-#409 2 e 7 power_on_after_fail<br>-#411 5 r 0 unused<br>-<br>-# coreboot config options: bootloader<br>-416 512 s 0 boot_devices<br>-928 8 h 0 boot_default<br>-936 1 e 8 cmos_defaults_loaded<br>-937 1 e 1 lpt<br>-#938 46 r 0 unused<br>-<br>-# coreboot config options: check sums<br>-984 16 h 0 check_sum<br>-<br>-# -----------------------------------------------------------------<br>-<br>-enumerations<br>-<br>-#ID value text<br>-1 0 Disable<br>-1 1 Enable<br>-2 0 Enable<br>-2 1 Disable<br>-4 0 Fallback<br>-4 1 Normal<br>-6 1 Emergency<br>-6 2 Alert<br>-6 3 Critical<br>-6 4 Error<br>-6 5 Warning<br>-6 6 Notice<br>-6 7 Info<br>-6 8 Debug<br>-6 9 Spew<br>-7 0 Disable<br>-7 1 Enable<br>-7 2 Keep<br>-8 0 No<br>-8 1 Yes<br>-9 0 Secondary<br>-9 1 Primary<br>-# -----------------------------------------------------------------<br>-checksums<br>-<br>-checksum 392 983 984<br>diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb<br>deleted file mode 100644<br>index d496206..0000000<br>--- a/src/mainboard/supermicro/x7db8/devicetree.cb<br>+++ /dev/null<br>@@ -1,177 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2007-2009 coresystems GmbH<br>-## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org><br>-##<br>-## This program is free software; you can redistribute it and/or<br>-## modify it under the terms of the GNU General Public License as<br>-## published by the Free Software Foundation; version 2 of<br>-## the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-chip northbridge/intel/i5000<br>-<br>- device cpu_cluster 0 on<br>- chip cpu/intel/socket_LGA771<br>- device lapic 0 on end<br>- end<br>- end<br>-<br>- device domain 0 on<br>- device pci 00.0 on # Host bridge<br>- subsystemid 0x15d9 0x2017<br>- end<br>-<br>- device pci 02.0 on # PCI Express x8 Port 2-3<br>- ioapic_irq 8 INTA 0x10<br>- ioapic_irq 8 INTB 0x11<br>- ioapic_irq 8 INTC 0x12<br>- ioapic_irq 8 INTD 0x13<br>- device pci 00.0 on # PCI Express Upstream Port<br>- device pci 00.0 on # PCI Express Downstream Port E1<br>- device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A<br>- ioapic_irq 8 INTA 0x11<br>- ioapic_irq 8 INTB 0x10<br>- ioapic_irq 8 INTC 0x11<br>- ioapic_irq 8 INTD 0x10<br>- # PCI slot<br>- device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B<br>- # PCI slot<br>- end<br>- device pci 02.0 on # Adaptec U320 #1<br>- ioapic_irq 8 INTA 0x10<br>- end<br>- device pci 02.1 on # Adaptec U320 #2<br>- ioapic_irq 8 INTB 0x11<br>- end<br>- end<br>- end<br>- device pci 00.1 on end<br>- device pci 00.3 on end<br>- end<br>-<br>- device pci 03.0 on end<br>- device pci 04.0 on end<br>- device pci 05.0 on end<br>- device pci 06.0 on end<br>- device pci 07.0 on end<br>- device pci 00.3 on # PCI Express to PCI-X Bridge<br>- ioapic_irq 9 INTA 3<br>- ioapic_irq 9 INTB 0<br>- ioapic_irq 9 INTC 1<br>- ioapic_irq 9 INTD 2<br>- # PCI-X Slot<br>- end<br>- end<br>-<br>- device pci 03.0 on<br>- ioapic_irq 8 INTA 0x10<br>- end<br>- device pci 04.0 on<br>- ioapic_irq 8 INTA 0x10<br>- end<br>- device pci 05.0 on<br>- ioapic_irq 8 INTA 0x10<br>- end<br>- device pci 06.0 on<br>- ioapic_irq 8 INTA 0x10<br>- end<br>- device pci 07.0 on<br>- ioapic_irq 8 INTA 0x10<br>- end<br>-<br>- device pci 10.0 on end # FBD<br>- device pci 10.1 on end # FBD<br>- device pci 10.2 on end # FBD<br>- device pci 11.0 on end # FBD reserved<br>- device pci 13.0 on end # FBD reserved<br>- device pci 15.0 on end # FBD<br>- device pci 16.0 on end # FBD<br>-<br>- chip southbridge/intel/i3100<br>- register "pirq_a_d" = "0x0b0b0b0b"<br>- register "pirq_e_h" = "0x80808080"<br>- register "sata_ports_implemented" = "0x3f"<br>-<br>- device pci 1c.0 on<br>- ioapic_irq 8 INTA 0x14<br>- ioapic_irq 8 INTB 0x15<br>- ioapic_irq 8 INTC 0x16<br>- ioapic_irq 8 INTD 0x17<br>- end # PCIe bridge<br>- device pci 1d.0 on<br>- ioapic_irq 8 INTA 0x10<br>- end # USB UHCI<br>- device pci 1d.1 on<br>- ioapic_irq 8 INTB 0x11<br>- end # USB UHCI<br>- device pci 1d.2 on<br>- ioapic_irq 8 INTC 0x12<br>- end # USB UHCI<br>- device pci 1d.3 on<br>- ioapic_irq 8 INTD 0x13<br>- end # USB UHCI<br>- device pci 1d.7 on end # USB2 EHCI<br>- device pci 1e.0 on<br>- device pci 01.0 on end<br>- end<br>-<br>- device pci 1f.0 on # PCI-LPC bridge<br>- ioapic_irq 8 INTA 0x11<br>- subsystemid 0x15d9 0x2009<br>- chip superio/winbond/w83627hf<br>- device pnp 2e.0 off end # FDC<br>- device pnp 2e.1 on # Parallel Port<br>- io 0x60 = 0x378<br>- irq 0x70 = 7<br>- end<br>- device pnp 2e.2 on # Serial Port 1<br>- io 0x60 = 0x3f8<br>- irq 0x70 = 4<br>- end<br>-<br>- device pnp 2e.3 off end<br>- device pnp 2e.5 on # KBC<br>- io 0x60 = 0x60<br>- io 0x62 = 0x64<br>- irq 0x70 = 1<br>- irq 0x72 = 12<br>- end<br>-<br>- device pnp 2e.6 off end # CIR<br>- device pnp 2e.7 off end # Game port / MIDI<br>- device pnp 2e.8 off end # GPIO2<br>- device pnp 2e.9 on end # GPIO3<br>- device pnp 2e.a on end # ACPI<br>- device pnp 2e.b off end # HWMON<br>- end<br>- end<br>- device pci 1f.1 off end # IDE<br>- device pci 1f.2 on end # SATA<br>- device pci 1f.3 on<br>- chip drivers/i2c/w83793<br>- register "mfc" = "0x28"<br>- register "fanin" = "0x1f"<br>- register "peci_agent_conf" = "0x33"<br>- register "tcase0" = "0x5e"<br>- register "tcase1" = "0x5e"<br>- register "tcase2" = "0x5e"<br>- register "tcase3" = "0x5e"<br>- register "tr_enable" = "0x01"<br>- register "critical_temperature" = "0x7f"<br>- register "td1_fan_select" = "0x01"<br>- register "td2_fan_select" = "0x01"<br>- register "td3_fan_select" = "0x01"<br>- register "td4_fan_select" = "0x01"<br>- device i2c 0x2f on end<br>- end<br>- end # SMBUS<br>- end<br>- end<br>-end<br>diff --git a/src/mainboard/supermicro/x7db8/irq_tables.c b/src/mainboard/supermicro/x7db8/irq_tables.c<br>deleted file mode 100644<br>index 9a2e09d..0000000<br>--- a/src/mainboard/supermicro/x7db8/irq_tables.c<br>+++ /dev/null<br>@@ -1,53 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */<br>- 0x00, /* Interrupt router bus */<br>- (0x1f << 3) | 0x0, /* Interrupt router dev */<br>- 0, /* IRQs devoted exclusively to PCI usage */<br>- 0x8086, /* Vendor */<br>- 0x2670, /* Device */<br>- 0, /* Miniport */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0, /* Checksum (has to be set to some value that<br>- * would give 0 after the sum of all bytes<br>- * for this structure (including checksum).<br>- */<br>- {<br>- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},<br>- {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},<br>- {0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- {0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},<br>- }<br>-};<br>-<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c<br>deleted file mode 100644<br>index ac8da6d..0000000<br>--- a/src/mainboard/supermicro/x7db8/romstage.c<br>+++ /dev/null<br>@@ -1,145 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org><br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <string.h><br>-#include <arch/io.h><br>-#include <device/pci_def.h><br>-#include <device/pnp_def.h><br>-#include <cpu/x86/lapic.h><br>-#include <lib.h><br>-#include <console/console.h><br>-#include <cpu/x86/bist.h><br>-#include <cpu/intel/romstage.h><br>-#include <superio/winbond/common/winbond.h><br>-#include <superio/winbond/w83627hf/w83627hf.h><br>-#include <northbridge/intel/i5000/raminit.h><br>-#include <northbridge/intel/i3100/i3100.h><br>-#include <southbridge/intel/i3100/i3100.h><br>-#include <southbridge/intel/i3100/early_smbus.c><br>-<br>-#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)<br>-#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)<br>-<br>-#define RCBA_RPC 0x0224 /* 32 bit */<br>-#define RCBA_HPTC 0x3404 /* 32 bit */<br>-#define RCBA_GCS 0x3410 /* 32 bit */<br>-#define RCBA_FD 0x3418 /* 32 bit */<br>-<br>-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)<br>-<br>-static void early_config(void)<br>-{<br>- u32 gcs, rpc, fd;<br>-<br>- /* Enable RCBA */<br>- pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);<br>-<br>- /* Disable watchdog */<br>- gcs = read32(DEFAULT_RCBA + RCBA_GCS);<br>- gcs |= (1 << 5); /* No reset */<br>- write32(DEFAULT_RCBA + RCBA_GCS, gcs);<br>-<br>- /* Configure PCIe port B as 4x */<br>- rpc = read32(DEFAULT_RCBA + RCBA_RPC);<br>- rpc |= (3 << 0);<br>- write32(DEFAULT_RCBA + RCBA_RPC, rpc);<br>-<br>- /* Disable Modem, Audio, PCIe ports 2/3/4 */<br>- fd = read32(DEFAULT_RCBA + RCBA_FD);<br>- fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);<br>- write32(DEFAULT_RCBA + RCBA_FD, fd);<br>-<br>- /* Enable HPET */<br>- write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));<br>-<br>- /* Setup sata mode */<br>- pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40);<br>-}<br>-<br>-#define DEFAULT_GPIOBASE 0x1180<br>-static void setup_gpio(void)<br>-{<br>- pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1);<br>- pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4));<br>-<br>- outl(0xff0c79cf, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */<br>- outl(0xe700ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */<br>- outl(0x65b70000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */<br>- outl(0x0000718a, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */<br>- outl(0x00000106, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */<br>- outl(0x00000301, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */<br>- outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */<br>-}<br>-<br>-static void i5000_lpc_config(void)<br>-{<br>- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);<br>-}<br>-<br>-int mainboard_set_fbd_clock(int speed)<br>-{<br>- switch(speed) {<br>- case 533:<br>- smbus_write_byte(0x6f, 0x80, 0x21);<br>- return 0;<br>- case 667:<br>- smbus_write_byte(0x6f, 0x80, 0x23);<br>- return 0;<br>- default:<br>- printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed);<br>- die("");<br>- return -1;<br>- }<br>-}<br>-<br>-void mainboard_romstage_entry(unsigned long bist)<br>-{<br>- if (bist == 0)<br>- enable_lapic();<br>-<br>- i5000_lpc_config();<br>-<br>- winbond_enable_serial(SERIAL_DEV, 0x3f8);<br>- console_init();<br>-<br>- /* Halt if there was a built in self test failure */<br>- report_bist_failure(bist);<br>-<br>- early_config();<br>-<br>- setup_gpio();<br>-<br>- enable_smbus();<br>-<br>- outb(0x07, 0x11b8);<br>-<br>- /* These are smbus write captured with serialice. They<br>- seem to setup the clock generator */<br>-<br>- smbus_write_byte(0x6f, 0x88, 0x1f);<br>- smbus_write_byte(0x6f, 0x81, 0xff);<br>- smbus_write_byte(0x6f, 0x82, 0xff);<br>- smbus_write_byte(0x6f, 0x80, 0x23);<br>-<br>- outb(0x03, 0x11b8);<br>- outb(0x01, 0x11b8);<br>-<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1);<br>- i5000_fbdimm_init();<br>- smbus_write_byte(0x69, 0x01, 0x01);<br>-}<br>diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig<br>deleted file mode 100644<br>index 67a21fc..0000000<br>--- a/src/northbridge/intel/i5000/Kconfig<br>+++ /dev/null<br>@@ -1,31 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org><br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-config NORTHBRIDGE_INTEL_I5000<br>- bool<br>- select HAVE_DEBUG_RAM_SETUP<br>- select LATE_CBMEM_INIT<br>-<br>-if NORTHBRIDGE_INTEL_I5000<br>-<br>-config NORTHBRIDGE_INTEL_I5000_RAM_CHECK<br>- bool<br>- prompt "Run ramcheck after RAM initialization"<br>-<br>-config BOOTBLOCK_NORTHBRIDGE_INIT<br>- string<br>- default "northbridge/intel/i5000/bootblock.c"<br>-<br>-endif<br>diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc<br>deleted file mode 100644<br>index 9f6c38e..0000000<br>--- a/src/northbridge/intel/i5000/Makefile.inc<br>+++ /dev/null<br>@@ -1,22 +0,0 @@<br>-#<br>-# This file is part of the coreboot project.<br>-#<br>-# Copyright (C) 2007-2009 coresystems GmbH<br>-#<br>-# This program is free software; you can redistribute it and/or modify<br>-# it under the terms of the GNU General Public License as published by<br>-# the Free Software Foundation; version 2 of the License.<br>-#<br>-# This program is distributed in the hope that it will be useful,<br>-# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-# GNU General Public License for more details.<br>-#<br>-<br>-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I5000),y)<br>-<br>-ramstage-y += northbridge.c<br>-romstage-y += raminit.c<br>-cpu_incs-y += src/northbridge/intel/i5000/halt_second_bsp.S<br>-<br>-endif<br>diff --git a/src/northbridge/intel/i5000/bootblock.c b/src/northbridge/intel/i5000/bootblock.c<br>deleted file mode 100644<br>index ff7513a..0000000<br>--- a/src/northbridge/intel/i5000/bootblock.c<br>+++ /dev/null<br>@@ -1,21 +0,0 @@<br>-#include <arch/io.h><br>-<br>-static void bootblock_northbridge_init(void)<br>-{<br>- /*<br>- * The "io" variant of the config access is explicitly used to<br>- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to<br>- * to true. That way all subsequent non-explicit config accesses use<br>- * MCFG. This code also assumes that bootblock_northbridge_init() is<br>- * the first thing called in the non-asm boot block code. The final<br>- * assumption is that no assembly code is using the<br>- * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.<br>- *<br>- * The PCIEXBAR is assumed to live in the memory mapped IO space under<br>- * 4GiB.<br>- */<br>-<br>- /* setup PCIe MMCONF base address */<br>- pci_io_write_config32(PCI_DEV(0, 16, 0), 0x64,<br>- CONFIG_MMCONF_BASE_ADDRESS >> 16);<br>-}<br>diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S<br>deleted file mode 100644<br>index 041807e..0000000<br>--- a/src/northbridge/intel/i5000/halt_second_bsp.S<br>+++ /dev/null<br>@@ -1,58 +0,0 @@<br>- /* Save BIST result */<br>-<br>- movl %eax, %ebp<br>-<br>- /* check if SPAD0 is cleared. If yes, it means this was a hard reset */<br>- movl $0x800080d0, %eax<br>- movw $0xcf8, %dx<br>- outl %eax, %dx<br>-<br>- addw $4, %dx<br>- inl %dx, %eax<br>- cmp $0, %eax<br>- je no_reset<br>-<br>- /* perform hard reset */<br>- movw $0xcf9, %dx<br>- movb $0x06, %al<br>- outb %al, %dx<br>-<br>-loop0: hlt<br>- jmp loop0<br>-<br>-no_reset:<br>-<br>- /* Read the semaphore register of i5000 (BOFL0).<br>- If it returns zero, it means there was already<br>- another read by another CPU */<br>-<br>- movl $0x800080c0, %eax<br>- movw $0xcf8, %dx<br>- outl %eax, %dx<br>-<br>- addw $4, %dx<br>- inl %dx, %eax<br>- cmp $0, %eax<br>- jne 1f<br>-<br>- /* degrade BSP to AP */<br>- mov $0x1b, %ecx<br>- rdmsr<br>- andl $(~0x100), %eax<br>- wrmsr<br>-<br>- cli<br>-loop: hlt<br>- jmp loop<br>-<br>-1: /* set magic value for soft reset detection */<br>- movl $0x800080d0, %eax<br>- movw $0xcf8, %dx<br>- outl %eax, %dx<br>-<br>- addw $4, %dx<br>- movl $0x12345678, %eax<br>- outl %eax, %dx<br>-<br>- /* Restore BIST */<br>- mov %ebp, %eax<br>diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c<br>deleted file mode 100644<br>index f54ab5e..0000000<br>--- a/src/northbridge/intel/i5000/northbridge.c<br>+++ /dev/null<br>@@ -1,177 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include <cpu/cpu.h><br>-#include <arch/acpi.h><br>-#include <cbmem.h><br>-<br>-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- if (!vendor || !device) {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- pci_read_config32(dev, PCI_VENDOR_ID));<br>- } else {<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>- }<br>-}<br>-<br>-static void mc_read_resources(device_t dev)<br>-{<br>- struct resource *resource;<br>- uint32_t hecbase, amsize, tolm;<br>- uint64_t ambase, memsize;<br>- int idx = 0;<br>-<br>- device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0));<br>- device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1));<br>-<br>- pci_dev_read_resources(dev);<br>-<br>- tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16;<br>- hecbase = pci_read_config16(dev16_0, 0x64) >> 12;<br>- hecbase &= 0xffff;<br>-<br>- ambase = ((u64)pci_read_config32(dev16_0, 0x48) |<br>- (u64)pci_read_config32(dev16_0, 0x4c) << 32);<br>-<br>- amsize = pci_read_config32(dev16_0, 0x50);<br>- ambase &= 0x000000ffffff0000;<br>-<br>- printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase);<br>-<br>- /* Report the memory regions */<br>- ram_resource(dev, idx++, 0, 640);<br>- ram_resource(dev, idx++, 768, ((tolm >> 10) - 768));<br>-<br>- memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3,<br>- pci_read_config16(dev16_1, 0x84) & ~3);<br>- memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3);<br>-<br>- memsize <<= 24;<br>- printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize);<br>- if (memsize > 0xd0000000) {<br>- memsize -= 0xd0000000;<br>- printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576);<br>- ram_resource(dev, idx++, 4096 * 1024, memsize / 1024);<br>- }<br>-<br>- if (hecbase) {<br>- printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28);<br>- resource = new_resource(dev, idx++);<br>- resource->base = (resource_t)(uint64_t)hecbase << 28;<br>- resource->size = (resource_t)256 * 1024 * 1024;<br>- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |<br>- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;<br>- }<br>-<br>- resource = new_resource(dev, idx++);<br>- resource->base = (resource_t)(uint64_t)0xffe00000;<br>- resource->size = (resource_t)0x200000;<br>- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |<br>- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;<br>-<br>- if (ambase && amsize) {<br>- resource = new_resource(dev, idx++);<br>- resource->base = (resource_t)ambase;<br>- resource->size = (resource_t)amsize;<br>- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |<br>- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;<br>- }<br>-<br>- /* add resource for 0xfe6xxxxx range. This range is used by i5000 for<br>- various fixed address registers (BOFL, SPAD, SPADS */<br>- resource = new_resource(dev, idx++);<br>- resource->base = (resource_t)0xfe600000;<br>- resource->size = (resource_t)0x00100000;<br>- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |<br>- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;<br>-<br>- set_late_cbmem_top(tolm);<br>-}<br>-<br>-static struct pci_operations intel_pci_ops = {<br>- .set_subsystem = intel_set_subsystem,<br>-};<br>-<br>-static struct device_operations mc_ops = {<br>- .read_resources = mc_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .scan_bus = 0,<br>- .ops_pci = &intel_pci_ops,<br>-};<br>-<br>-static const unsigned short nb_ids[] = {<br>- 0x25c0, /* 5000X */<br>- 0x25d0, /* 5000Z */<br>- 0x25d4, /* 5000V */<br>- 0x25d8, /* 5000P */<br>- 0};<br>-<br>-static const struct pci_driver mc_driver __pci_driver = {<br>- .ops = &mc_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .devices = nb_ids,<br>-};<br>-<br>-static void cpu_bus_init(device_t dev)<br>-{<br>- initialize_cpus(dev->link_list);<br>-}<br>-<br>-static struct device_operations cpu_bus_ops = {<br>- .read_resources = DEVICE_NOOP,<br>- .set_resources = DEVICE_NOOP,<br>- .enable_resources = DEVICE_NOOP,<br>- .init = cpu_bus_init,<br>- .scan_bus = 0,<br>-};<br>-static void pci_domain_set_resources(device_t dev)<br>-{<br>- assign_resources(dev->link_list);<br>-}<br>-<br>-static struct device_operations pci_domain_ops = {<br>- .read_resources = pci_domain_read_resources,<br>- .set_resources = pci_domain_set_resources,<br>- .enable_resources = NULL,<br>- .init = NULL,<br>- .scan_bus = pci_domain_scan_bus,<br>- .ops_pci_bus = pci_bus_default_ops,<br>-};<br>-<br>-static void enable_dev(device_t dev)<br>-{<br>- /* Set the operations if it is a special bus type */<br>- if (dev->path.type == DEVICE_PATH_DOMAIN) {<br>- dev->ops = &pci_domain_ops;<br>- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {<br>- dev->ops = &cpu_bus_ops;<br>- }<br>-}<br>-<br>-struct chip_operations northbridge_intel_i5000_ops = {<br>- CHIP_NAME("Intel i5000 Northbridge")<br>- .enable_dev = enable_dev,<br>-};<br>diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c<br>deleted file mode 100644<br>index 4c71a5a..0000000<br>--- a/src/northbridge/intel/i5000/raminit.c<br>+++ /dev/null<br>@@ -1,1764 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org><br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include "raminit.h"<br>-#include <arch/io.h><br>-#include <device/pci_def.h><br>-#include <device/pnp_def.h><br>-#include <cpu/x86/lapic.h><br>-#include <cpu/intel/speedstep.h><br>-#include <console/console.h><br>-#include <halt.h><br>-#include <spd.h><br>-#include <types.h><br>-#include <string.h><br>-#include <cbmem.h><br>-#include <stdlib.h><br>-#include <lib.h><br>-#include <delay.h><br>-<br>-static int i5000_for_each_channel(struct i5000_fbd_branch *branch,<br>- int (*cb)(struct i5000_fbd_channel *))<br>-{<br>- struct i5000_fbd_channel *c;<br>- int ret;<br>-<br>- for (c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++)<br>- if (c->used && (ret = cb(c)))<br>- return ret;<br>- return 0;<br>-}<br>-<br>-static int i5000_for_each_branch(struct i5000_fbd_setup *setup,<br>- int (*cb)(struct i5000_fbd_branch *))<br>-{<br>- struct i5000_fbd_branch *b;<br>- int ret;<br>-<br>- for (b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++)<br>- if (b->used && (ret = cb(b)))<br>- return ret;<br>- return 0;<br>-}<br>-<br>-static int i5000_for_each_dimm(struct i5000_fbd_setup *setup,<br>- int (*cb)(struct i5000_fbdimm *))<br>-{<br>- struct i5000_fbdimm *d;<br>- int ret, i;<br>-<br>- for (i = 0; i < I5000_MAX_DIMMS; i++) {<br>- d = setup->dimms[i];<br>- if ((ret = cb(d))) {<br>- return ret;<br>- }<br>- }<br>- return 0;<br>-}<br>-<br>-static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup,<br>- int (*cb)(struct i5000_fbdimm *))<br>-{<br>- struct i5000_fbdimm *d;<br>- int ret, i;<br>-<br>- for (i = 0; i < I5000_MAX_DIMMS; i++) {<br>- d = setup->dimms[i];<br>- if (d->present && (ret = cb(d)))<br>- return ret;<br>- }<br>- return 0;<br>-}<br>-<br>-static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out)<br>-{<br>- u16 status;<br>- pci_devfn_t dev = d->branch->branchdev;<br>-<br>- int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;<br>- int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;<br>-<br>- while (count-- > 0) {<br>- pci_write_config32(dev, cmdreg, 0xa8000000 | \<br>- (d->num & 0x03) << 24 | addr++ << 16);<br>-<br>- int timeout = 1000;<br>- while ((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY && timeout--)<br>- udelay(10);<br>-<br>- if (status & I5000_SPD_SBE || !timeout)<br>- return -1;<br>-<br>- if (status & I5000_SPD_RDO) {<br>- *out = status & 0xff;<br>- out++;<br>- }<br>- }<br>- return 0;<br>-}<br>-<br>-static void i5000_clear_fbd_errors(void)<br>-{<br>- pci_devfn_t dev16_1, dev16_2;<br>-<br>- dev16_1 = PCI_ADDR(0, 16, 1, 0);<br>- dev16_2 = PCI_ADDR(0, 16, 2, 0);<br>-<br>- pci_write_config32(dev16_1, I5000_EMASK_FBD,<br>- pci_read_config32(dev16_1, I5000_EMASK_FBD));<br>-<br>- pci_write_config32(dev16_1, I5000_NERR_FAT_FBD,<br>- pci_read_config32(dev16_1, I5000_NERR_FAT_FBD));<br>-<br>- pci_write_config32(dev16_1, I5000_FERR_FAT_FBD,<br>- pci_read_config32(dev16_1, I5000_FERR_FAT_FBD));<br>-<br>- pci_write_config32(dev16_1, I5000_NERR_NF_FBD,<br>- pci_read_config32(dev16_1, I5000_NERR_NF_FBD));<br>-<br>- pci_write_config32(dev16_1, I5000_FERR_NF_FBD,<br>- pci_read_config32(dev16_1, I5000_FERR_NF_FBD));<br>-<br>- pci_write_config32(dev16_2, I5000_FERR_GLOBAL,<br>- pci_read_config32(dev16_2, I5000_FERR_GLOBAL));<br>-<br>- pci_write_config32(dev16_2, I5000_NERR_GLOBAL,<br>- pci_read_config32(dev16_2, I5000_NERR_GLOBAL));<br>-}<br>-<br>-static int i5000_branch_reset(struct i5000_fbd_branch *b)<br>-{<br>- pci_devfn_t dev = b->branchdev;<br>-<br>- pci_write_config8(dev, I5000_FBDRST, 0x00);<br>-<br>- udelay(5000);<br>-<br>- pci_write_config8(dev, I5000_FBDRST, 0x05);<br>- udelay(1);<br>- pci_write_config8(dev, I5000_FBDRST, 0x04);<br>- udelay(2);<br>- pci_write_config8(dev, I5000_FBDRST, 0x05);<br>- pci_write_config8(dev, I5000_FBDRST, 0x07);<br>- return 0;<br>-}<br>-<br>-static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del)<br>-{<br>- int div;<br>-<br>- switch (d->setup->ddr_speed) {<br>- case DDR_533MHZ:<br>- div = 375;<br>- break;<br>-<br>- default:<br>- printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n",<br>- d->setup->ddr_speed);<br>-<br>- case DDR_667MHZ:<br>- div = 300;<br>- break;<br>- }<br>-<br>- return (del * 100) / div;<br>-}<br>-<br>-static int mtb2clks(struct i5000_fbdimm *d, int del)<br>-{<br>- int val, div;<br>-<br>- switch (d->setup->ddr_speed) {<br>- case DDR_533MHZ:<br>- div = 375;<br>- break;<br>- default:<br>- printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n",<br>- d->setup->ddr_speed);<br>-<br>- case DDR_667MHZ:<br>- div = 300;<br>- break;<br>- }<br>-<br>- val = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * div);<br>- if ((val % 10) > 0)<br>- val += 10;<br>- return val / 10;<br>-}<br>-<br>-static int i5000_read_spd_data(struct i5000_fbdimm *d)<br>-{<br>- struct i5000_fbd_setup *s = d->setup;<br>- u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr;<br>- u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min;<br>- u8 cmd2data_addr;<br>- int t_ck_min, dimmsize;<br>-<br>- if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) {<br>- printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n",<br>- d->branch->num, d->channel->num, d->num);<br>- return 0; // No FBDIMM present<br>- }<br>-<br>- if (val != 0x09)<br>- return -1; // SDRAM type not FBDIMM<br>-<br>- if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes))<br>- return -1;<br>-<br>- switch(s->ddr_speed) {<br>- case DDR_533MHZ:<br>- cmd2data_addr = FBDIMM_SPD_CMD2DATA_533;<br>- break;<br>-<br>- case DDR_667MHZ:<br>- cmd2data_addr = FBDIMM_SPD_CMD2DATA_667;<br>- break;<br>-<br>- default:<br>- printk(BIOS_ERR, "Unsupported FBDIMM clock\n");<br>- return -1;<br>- }<br>-<br>- if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) ||<br>- spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) ||<br>- spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) ||<br>- spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) ||<br>- spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) ||<br>- spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) ||<br>- spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) ||<br>- spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) ||<br>- spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) ||<br>- spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) ||<br>- spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) ||<br>- spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) ||<br>- spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) ||<br>- spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) ||<br>- spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) ||<br>- spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) ||<br>- spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) ||<br>- spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) ||<br>- spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) ||<br>- spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) ||<br>- spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) ||<br>- spd_read_byte(d, FBDIMM_SPD_CMD2DATA_533, 1, &d->cmd2datanxt[DDR_533MHZ]) ||<br>- spd_read_byte(d, FBDIMM_SPD_CMD2DATA_667, 1, &d->cmd2datanxt[DDR_667MHZ]) ||<br>- spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) {<br>- printk(BIOS_ERR, "failed to read data from SPD\n");<br>- return 0;<br>- }<br>-<br>-<br>- t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor;<br>- if (t_ck_min <= 300)<br>- d->speed = DDR_667MHZ;<br>- else if (t_ck_min <= 375)<br>- d->speed = DDR_533MHZ;<br>- else {<br>- printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min);<br>- return -1;<br>- }<br>-<br>- d->sdram_width = org & 0x07;<br>- if (d->sdram_width > 1) {<br>- printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width);<br>- return -1;<br>- }<br>-<br>- if (s->ddr_speed == DDR_667MHZ && d->speed == DDR_533MHZ)<br>- s->ddr_speed = DDR_533MHZ;<br>-<br>- d->banks = 4 << (addr & 0x03);<br>- d->columns = 9 + ((addr >> 2) & 0x03);<br>- d->rows = 12 + ((addr >> 5) & 0x03);<br>- d->ranks = (org >> 3) & 0x03;<br>- d->min_cas_latency = cas & 0x0f;<br>-<br>- s->bl &= bl;<br>-<br>- if (!s->bl) {<br>- printk(BIOS_ERR, "no compatible burst length found\n");<br>- return -1;<br>- }<br>-<br>- s->t_rc = MAX(s->t_rc, mtb2clks(d,<br>- t_rc | ((t_ras_rc_h & 0xf0) << 4)));<br>- s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd));<br>- s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc));<br>- s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd));<br>- s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min));<br>- s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr));<br>- s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp));<br>- s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp));<br>- s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr));<br>- s->t_ras = MAX(s->t_ras, mtb2clks(d,<br>- t_ras | ((t_ras_rc_h & 0x0f) << 8)));<br>- s->t_r2r = MAX(s->t_r2r, bb & 3);<br>- s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3);<br>- s->t_w2r = MAX(s->t_w2r, (bb >> 2) & 3);<br>-<br>- d->ranksize = (1 << (d->banks + d->columns + d->rows + 1)) >> 20;<br>- dimmsize = d->ranksize * d->ranks;<br>- d->branch->totalmem += dimmsize;<br>- s->totalmem += dimmsize;<br>-<br>- d->channel->columns = d->columns;<br>- d->channel->rows = d->rows;<br>- d->channel->ranks = d->ranks;<br>- d->channel->banks = d->banks;<br>- d->channel->width = d->sdram_width;<br>-<br>- printk(BIOS_INFO, "DIMM %d/%d/%d %dMB: %d banks, "<br>- "%d columns, %d rows, %d ranks\n",<br>- d->branch->num, d->channel->num, d->num, dimmsize,<br>- d->banks, d->columns, d->rows, d->ranks);<br>-<br>- d->present = 1;<br>- d->branch->used |= 1;<br>- d->channel->used |= 1;<br>- d->channel->highest_amb = d->num;<br>- return 0;<br>-}<br>-<br>-static int i5000_amb_smbus_write(struct i5000_fbdimm *d, int byte1, int byte2)<br>-{<br>- u16 status;<br>- pci_devfn_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);<br>- int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;<br>- int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;<br>- int timeout = 1000;<br>-<br>- pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |<br>- (byte1 << 16) | (byte2 << 8) | 1);<br>-<br>- while (((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--)<br>- udelay(10);<br>-<br>- if (status & I5000_SPD_WOD && timeout)<br>- return 0;<br>-<br>- printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n",<br>- d->branch->num, d->channel->num, d->num, byte1, byte2, status);<br>- die("Error: SMBus write failed");<br>-}<br>-<br>-static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out)<br>-{<br>- u16 status;<br>- pci_devfn_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);<br>- int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;<br>- int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;<br>- int timeout = 1000;<br>-<br>- pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |<br>- (byte1 << 16));<br>-<br>- while (((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--)<br>- udelay(10);<br>-<br>- if ((status & I5000_SPD_RDO) && timeout)<br>- *out = status & 0xff;<br>-<br>- if (status & I5000_SPD_SBE || !timeout) {<br>- printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x status %04x\n",<br>- d->branch->num, d->channel->num, d->num, byte1, status);<br>- return -1;<br>- }<br>- return 0;<br>-<br>-}<br>-<br>-static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d,<br>- int fn, int reg, u8 val)<br>-{<br>- if (i5000_amb_smbus_write(d, 0x84, 00) ||<br>- i5000_amb_smbus_write(d, 0x04, fn) ||<br>- i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) ||<br>- i5000_amb_smbus_write(d, 0x04, reg & 0xff) ||<br>- i5000_amb_smbus_write(d, 0x44, val)) {<br>- printk(BIOS_ERR, "AMB SMBUS write failed\n");<br>- return 1;<br>- }<br>- return 0;<br>-}<br>-<br>-static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d,<br>- int fn, int reg, u16 val)<br>-{<br>- if (i5000_amb_smbus_write(d, 0x88, 00) ||<br>- i5000_amb_smbus_write(d, 0x08, fn) ||<br>- i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) ||<br>- i5000_amb_smbus_write(d, 0x08, reg & 0xff) ||<br>- i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) ||<br>- i5000_amb_smbus_write(d, 0x48, val & 0xff)) {<br>- printk(BIOS_ERR, "AMB SMBUS write failed\n");<br>- return 1;<br>- }<br>- return 0;<br>-}<br>-<br>-static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d,<br>- int fn, int reg, u32 val)<br>-{<br>- if (i5000_amb_smbus_write(d, 0x8c, 00) ||<br>- i5000_amb_smbus_write(d, 0x0c, fn) ||<br>- i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) ||<br>- i5000_amb_smbus_write(d, 0x0c, reg & 0xff) ||<br>- i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) ||<br>- i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) ||<br>- i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) ||<br>- i5000_amb_smbus_write(d, 0x4c, val & 0xff)) {<br>- printk(BIOS_ERR, "AMB SMBUS write failed\n");<br>- return 1;<br>- }<br>- return 0;<br>-}<br>-<br>-static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d,<br>- int fn, int reg, u32 *val)<br>-{<br>- u8 byte3, byte2, byte1, byte0;<br>-<br>- if (i5000_amb_smbus_write(d, 0x80, 00) ||<br>- i5000_amb_smbus_write(d, 0x00, fn) ||<br>- i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) ||<br>- i5000_amb_smbus_write(d, 0x40, reg & 0xff) ||<br>- i5000_amb_smbus_read(d, 0x80, &byte3) ||<br>- i5000_amb_smbus_read(d, 0x00, &byte3) ||<br>- i5000_amb_smbus_read(d, 0x00, &byte2) ||<br>- i5000_amb_smbus_read(d, 0x00, &byte1) ||<br>- i5000_amb_smbus_read(d, 0x40, &byte0)) {<br>- printk(BIOS_ERR, "AMB SMBUS read failed\n");<br>- return 1;<br>- }<br>- *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;<br>- return 0;<br>-}<br>-<br>-static void i5000_amb_write_config8(struct i5000_fbdimm *d,<br>- int fn, int reg, u32 val)<br>-{<br>- write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);<br>-}<br>-<br>-static void i5000_amb_write_config16(struct i5000_fbdimm *d,<br>- int fn, int reg, u32 val)<br>-{<br>- write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);<br>-}<br>-<br>-static void i5000_amb_write_config32(struct i5000_fbdimm *d,<br>- int fn, int reg, u32 val)<br>-{<br>- write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);<br>-}<br>-<br>-static u32 i5000_amb_read_config32(struct i5000_fbdimm *d,<br>- int fn, int reg)<br>-{<br>- return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg));<br>-}<br>-<br>-static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command)<br>-{<br>- u32 drc, status;<br>-<br>- printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...",<br>- d->branch->num, d->channel->num, d->num, rank, command, addr);<br>-<br>- drc = i5000_amb_read_config32(d, 3, AMB_DRC);<br>- drc &= ~((3 << 9) | (1 << 12));<br>- drc |= (rank << 9);<br>-<br>- command &= 0x0f;<br>- command |= AMB_DCALCSR_START | (rank << 21);<br>-<br>- printk(BIOS_DEBUG, "%s: AMB_DCALADDR: %08x AMB_DCALCSR: %08x\n", __func__, addr, command);<br>- i5000_amb_write_config32(d, 3, AMB_DRC, drc);<br>- i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr);<br>- i5000_amb_write_config32(d, 4, AMB_DCALCSR, command);<br>-<br>- udelay(1000);<br>- while ((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR)))<br>- & (1 << 31));<br>-<br>- if (status & (1 << 30)) {<br>- printk(BIOS_SPEW, "failed (status 0x%08x)\n", status);<br>- return -1;<br>- }<br>-<br>- printk(BIOS_SPEW, "done\n");<br>- return 0;<br>-}<br>-<br>-static int i5000_ddr_calibration(struct i5000_fbdimm *d)<br>-{<br>- u32 status;<br>-<br>- i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);<br>- i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050);<br>- while ((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));<br>-<br>- i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050);<br>- while ((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));<br>-<br>- if (ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) ||<br>- ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL))<br>- return -1;<br>- return 0;<br>-}<br>-<br>-static int i5000_ddr_init(struct i5000_fbdimm *d)<br>-{<br>-<br>- int rank;<br>- u32 val;<br>- u8 odt;<br>-<br>- for (rank = 0; rank < d->ranks; rank++) {<br>- printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__,<br>- d->branch->num, d->channel->num, d->num, rank);<br>-<br>- if (ddr_command(d, 1 << rank,<br>- 0, AMB_DCALCSR_OPCODE_NOP))<br>- return -1;<br>-<br>- if (ddr_command(d, 1 << rank,<br>- 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))<br>- return -1;<br>-<br>- /* EMRS(2) */<br>- if (ddr_command(d, 1 << rank,<br>- 2, AMB_DCALCSR_OPCODE_MRS_EMRS))<br>- return -1;<br>-<br>- /* EMRS(3) */<br>- if (ddr_command(d, 1 << rank,<br>- 3, AMB_DCALCSR_OPCODE_MRS_EMRS))<br>- return -1;<br>-<br>- /* EMRS(1) */<br>- if (ddr_command(d, 1 << rank,<br>- 1, AMB_DCALCSR_OPCODE_MRS_EMRS))<br>- return -1;<br>-<br>- /* MRS: DLL reset */<br>- if (ddr_command(d, 1 << rank,<br>- 0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS))<br>- return -1;<br>-<br>- udelay(20);<br>-<br>- if (ddr_command(d, 1 << rank,<br>- 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))<br>- return -1;<br>-<br>- if (ddr_command(d, 1 << rank,<br>- 0, AMB_DCALCSR_OPCODE_REFRESH))<br>- return -1;<br>-<br>- if (ddr_command(d, 1 << rank, 0,<br>- AMB_DCALCSR_OPCODE_REFRESH))<br>- return -1;<br>-<br>- /* burst length + cas latency */<br>- val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) |<br>- (1 << 19) /* interleaved burst */ |<br>- (d->setup->t_cl << 20) |<br>- (((d->setup->t_wr - 1) & 7) << 25);<br>-<br>- printk(BIOS_DEBUG, "MRS: 0x%08x\n", val);<br>- if (ddr_command(d, 1 << rank,<br>- val, AMB_DCALCSR_OPCODE_MRS_EMRS))<br>- return -1;<br>-<br>- /* OCD calibration default */<br>- if (ddr_command(d, 1 << rank, 0x03800001,<br>- AMB_DCALCSR_OPCODE_MRS_EMRS))<br>- return -1;<br>-<br>-<br>- odt = d->odt;<br>- if (rank)<br>- odt >>= 4;<br>-<br>- val = (d->setup->t_al << 19) |<br>- ((odt & 1) << 18) |<br>- ((odt & 2) << 21) | 1;<br>-<br>- printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);<br>-<br>- /* ODT, OCD exit, additive latency */<br>- if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS))<br>- return -1;<br>- }<br>- return 0;<br>-}<br>-<br>-static int i5000_amb_preinit(struct i5000_fbdimm *d)<br>-{<br>- u32 *p32 = (u32 *)d->amb_personality_bytes;<br>- u16 *p16 = (u16 *)d->amb_personality_bytes;<br>- u32 id, drc, fbdsbcfg = 0x0909;<br>-<br>- printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__,<br>- d->branch->num, d->channel->num, d->num);<br>-<br>- i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]);<br>- i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]);<br>-<br>- drc = (d->setup->t_al << 4) | (d->setup->t_cl);<br>- printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc,<br>- d->cmd2datanxt[d->setup->ddr_speed]);<br>-<br>- switch(d->setup->ddr_speed) {<br>- case DDR_533MHZ:<br>- fbdsbcfg |= (1 << 16);<br>- break;<br>- case DDR_667MHZ:<br>- fbdsbcfg |= (2 << 16);<br>- break;<br>- default:<br>- return -1;<br>- }<br>-<br>- printk(BIOS_DEBUG, "FBDSBCFGNXT: %08x\n", fbdsbcfg);<br>- i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, fbdsbcfg);<br>- i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651);<br>- i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT,<br>- d->cmd2datanxt[d->setup->ddr_speed]);<br>-<br>- i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc);<br>-<br>- if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) {<br>- d->vendor = id & 0xffff;<br>- d->device = id >> 16;<br>- }<br>-<br>- pci_write_config8(d->branch->branchdev,<br>- d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04);<br>- return 0;<br>-}<br>-<br>-static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state)<br>-{<br>- int timeout = 10000;<br>- pci_devfn_t dev = b->branchdev;<br>-<br>- printk(BIOS_DEBUG, " FBD state branch %d: %02x,", b->num, state);<br>-<br>- pci_write_config8(dev, I5000_FBDHPC, state);<br>-<br>- printk(BIOS_DEBUG, "waiting for new state...");<br>-<br>- while (pci_read_config8(dev, I5000_FBDST) != state && timeout--)<br>- udelay(10);<br>-<br>- if (timeout) {<br>- printk(BIOS_DEBUG, "done\n");<br>- return;<br>- }<br>-<br>- printk(BIOS_ERR, "timeout while entering state %02x on branch %d\n",<br>- state, b->num);<br>-}<br>-<br>-static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c)<br>-{<br>- int i = 10;<br>- pci_devfn_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,<br>- c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);<br>-<br>- printk(BIOS_DEBUG, " waiting for pattern recognition...");<br>- while (pci_read_config16(dev, 0) != 0x1fff && --i > 0)<br>- udelay(5000);<br>-<br>- printk(BIOS_DEBUG, i ? "done\n" : "failed\n");<br>- printk(BIOS_DEBUG, "%d/%d Round trip latency: %d\n", c->branch->num, c->num,<br>- pci_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f);<br>- return !i;<br>-}<br>-<br>-static const char *pattern_names[16] = {<br>- "EI", "EI", "EI", "EI",<br>- "EI", "EI", "EI", "EI",<br>- "TS0", "TS1", "TS2", "TS3",<br>- "RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones",<br>-};<br>-<br>-static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait)<br>-{<br>- pci_devfn_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,<br>- c->num ? I5000_FBDICMD1 : I5000_FBDICMD0);<br>-<br>- printk(BIOS_DEBUG, " %d/%d driving pattern %s to AMB%d (%02x)\n",<br>- c->branch->num, c->num,<br>- pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern);<br>- pci_write_config8(dev, 0, pattern);<br>-<br>- if (!wait)<br>- return 0;<br>-<br>- return i5000_wait_pattern_recognized(c);<br>-}<br>-<br>-static int i5000_set_ambpresent(struct i5000_fbd_channel *c)<br>-{<br>- int i;<br>- pci_devfn_t branchdev = c->branch->branchdev;<br>- u16 ambpresent = 0x8000;<br>-<br>- for (i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {<br>- if (c->dimm[i].present)<br>- ambpresent |= (1 << i);<br>- }<br>-<br>- printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent);<br>- pci_write_config16(branchdev,<br>- c->num ?<br>- I5000_AMBPRESENT1 : \<br>- I5000_AMBPRESENT0, ambpresent);<br>-<br>- return 0;<br>-}<br>-<br>-<br>-static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad)<br>-{<br>- pci_devfn_t branchdev = c->branch->branchdev;<br>- int off = c->num ? 0x100 : 0;<br>- u32 portctl;<br>- int i, cnt = 1000;<br>-<br>- portctl = pci_read_config32(branchdev, I5000_FBD0IBPORTCTL + off);<br>- portctl &= ~0x01000020;<br>- if (mchpad)<br>- portctl |= 0x00800000;<br>- else<br>- portctl &= ~0x00800000;<br>- portctl &= ~0x01000020;<br>- pci_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl);<br>-<br>- /* drive calibration patterns */<br>- if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1))<br>- return -1;<br>-<br>- if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1))<br>- return -1;<br>-<br>- while (!(pci_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--)<br>- udelay(10);<br>-<br>- if (!cnt) {<br>- printk(BIOS_ERR, "IBIST timeout\n");<br>- return -1;<br>- }<br>-<br>- if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))<br>- return -1;<br>-<br>- for (i = 0; i < highest_amb; i++) {<br>- if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1)))<br>- return -1;<br>- }<br>-<br>- if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))<br>- return -1;<br>-<br>- if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1))<br>- return -1;<br>-<br>- if (i5000_set_ambpresent(c))<br>- return -1;<br>- return 0;<br>-}<br>-<br>-static int i5000_train_channel_idle(struct i5000_fbd_channel *c)<br>-{<br>- int i;<br>- u32 fbdsbcfg = 0x0b1b;<br>-<br>- switch(c->setup->ddr_speed) {<br>- case DDR_533MHZ:<br>- fbdsbcfg |= (1 << 16);<br>- break;<br>- case DDR_667MHZ:<br>- fbdsbcfg |= (2 << 16);<br>- break;<br>- default:<br>- return -1;<br>- }<br>-<br>- pci_write_config8(c->branch->branchdev,<br>- c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);<br>-<br>- for (i = 0; i < 4; i++) {<br>- if (c->dimm[i].present)<br>- i5000_amb_smbus_write_config32(c->dimm + i, 1, AMB_FBDSBCFGNXT, i ? (fbdsbcfg | 0x1000) : fbdsbcfg);<br>- }<br>-<br>- return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1);<br>-}<br>-<br>-static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c)<br>-{<br>- if (i5000_train_channel_idle(c))<br>- return -1;<br>-<br>- return i5000_drive_test_patterns(c, c->highest_amb, 0);<br>-}<br>-<br>-static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c)<br>-{<br>- if (i5000_train_channel_idle(c))<br>- return -1;<br>-<br>- return i5000_drive_test_patterns(c, c->highest_amb, 1);<br>-}<br>-<br>-static int i5000_setup_channel(struct i5000_fbd_channel *c)<br>-{<br>- pci_devfn_t branchdev = c->branch->branchdev;<br>- int off = c->branch->num ? 0x100 : 0;<br>- u32 val;<br>-<br>- pci_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);<br>- pci_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);<br>- pci_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff);<br>- pci_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff);<br>-<br>- pci_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db);<br>-<br>- /* unknown */<br>- val = pci_read_config32(branchdev, off + 0x0164);<br>- val &= 0xfffbcffc;<br>- val |= 0x4004;<br>- pci_write_config32(branchdev, off + 0x164, val);<br>-<br>- pci_write_config32(branchdev, off + 0x15c, 0xff);<br>- i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0);<br>- return 0;<br>-}<br>-<br>-static int i5000_link_training0(struct i5000_fbd_branch *b)<br>-{<br>- pci_devfn_t branchdev = b->branchdev;<br>-<br>- pci_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);<br>-<br>- if (i5000_for_each_channel(b, i5000_setup_channel))<br>- return -1;<br>-<br>- if (i5000_for_each_channel(b, i5000_train_channel_idle))<br>- return -1;<br>-<br>- i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);<br>-<br>- if (i5000_for_each_channel(b, i5000_drive_test_patterns0))<br>- return -1;<br>-<br>- i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);<br>- return 0;<br>-}<br>-<br>-static int i5000_link_training1(struct i5000_fbd_branch *b)<br>-{<br>- if (i5000_for_each_channel(b, i5000_train_channel_idle))<br>- return -1;<br>-<br>- i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);<br>-<br>- if (i5000_for_each_channel(b, i5000_drive_test_patterns1))<br>- return -1;<br>-<br>- i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);<br>- return 0;<br>-}<br>-<br>-<br>-static int i5000_amb_check(struct i5000_fbdimm *d)<br>-{<br>- u32 id = i5000_amb_read_config32(d, 0, 0);<br>-<br>- printk(BIOS_DEBUG, "AMB %d/%d/%d ID: %04x:%04x\n",<br>- d->branch->num, d->channel->num, d->num,<br>- id & 0xffff, id >> 16);<br>-<br>- if ((id & 0xffff) != d->vendor || id >> 16 != d->device) {<br>- printk(BIOS_ERR, "AMB mapping failed\n");<br>- return -1;<br>- }<br>- return 0;<br>-}<br>-<br>-static int i5000_amb_postinit(struct i5000_fbdimm *d)<br>-{<br>- u32 *p32 = (u32 *)d->amb_personality_bytes;<br>- u16 *p16 = (u16 *)d->amb_personality_bytes;<br>-<br>- i5000_amb_write_config16(d, 1, 0xb6, p16[3]);<br>- i5000_amb_write_config32(d, 1, 0xb8, p32[2]);<br>- i5000_amb_write_config16(d, 1, 0xbc, p16[6]);<br>- return 0;<br>-}<br>-<br>-static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d)<br>-{<br>- struct i5000_fbd_setup *s;<br>- u32 val, tref;<br>- int refi;<br>-<br>- s = d->setup;<br>-<br>- printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n",<br>- d->branch->num, d->channel->num, d->num);<br>-<br>- val = 0x44;<br>- printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val);<br>- i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val);<br>-<br>- val = (0x0c << 24) | /* CLK control */<br>- (1 << 18) | /* ODTZ enabled */<br>- (((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */<br>- ((d->setup->t_al & 0x0f) << 4) | /* additive latency */<br>- (d->setup->t_cl & 0x0f); /* CAS latency */<br>-<br>- if (d->ranks > 1) {<br>- val |= (0x03 << 9);<br>- } else {<br>- val |= (0x01 << 9);<br>- }<br>-<br>- printk(BIOS_DEBUG, "AMB_DRC: %08x\n", val);<br>- i5000_amb_write_config32(d, 3, AMB_DRC, val);<br>-<br>- val = (d->sdram_width << 30) |<br>- ((d->ranks == 2 ? 1 : 0) << 29) |<br>- ((d->banks == 8 ? 1 : 0) << 28) |<br>- ((d->rows - 13) << 26) |<br>- ((d->columns - 10) << 24) |<br>- (1 << 16) | /* Auto refresh exit */<br>- (0x27 << 8) | /* t_xsnr */<br>- (d->setup->t_rp << 4) |<br>- (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f);<br>-<br>- printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val);<br>- i5000_amb_write_config32(d, 3, AMB_DSREFTC, val);<br>-<br>- tref = 15;<br>-<br>- switch(d->t_refi & 0x0f) {<br>- case 0:<br>- refi = 15625;<br>- break;<br>- case 1:<br>- refi = 3900;<br>- tref = 3;<br>- break;<br>- case 2:<br>- refi = 7800;<br>- tref = 7;<br>- break;<br>- case 3:<br>- refi = 31250;<br>- break;<br>- case 4:<br>- refi = 62500;<br>- break;<br>- case 5:<br>- refi = 125000;<br>- break;<br>- default:<br>- printk(BIOS_ERR, "unsupported t_refi value: %d, using 7.8us\n",<br>- d->t_refi & 0x0f);<br>- refi = 7800;<br>- break;<br>- }<br>-<br>- s->t_ref = tref;<br>- val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16);<br>-<br>- printk(BIOS_DEBUG, "\tAMB_DAREFTC: %08x\n", val);<br>- i5000_amb_write_config32(d, 3, AMB_DAREFTC, val);<br>-<br>- u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) +<br>- (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor));<br>- u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr;<br>-<br>- val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) |<br>- ((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) |<br>- ((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) |<br>- ((s->t_rtp - 2) << 27);<br>-<br>- switch(s->t_ras) {<br>- case 15:<br>- val |= (1 << 29);<br>- break;<br>- case 12:<br>- val |= (2 << 29);<br>- break;<br>- default:<br>- break;<br>- }<br>-<br>- printk(BIOS_DEBUG, "\tAMB_DRT: %08x\n", val);<br>- i5000_amb_write_config32(d, 3, AMB_DRT, val);<br>- return 0;<br>-}<br>-<br>-static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern)<br>-{<br>- printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n",<br>- d->branch->num, d->channel->num, d->num, rank, pattern);<br>-<br>- i5000_amb_write_config32(d, 3, AMB_DAREFTC,<br>- i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000);<br>-<br>- i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678);<br>- i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);<br>- i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8));<br>- return 0;<br>-}<br>-<br>-static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank)<br>-{<br>- int cnt = 1000;<br>- u32 res;<br>-<br>- while ((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--)<br>- udelay(1000);<br>-<br>- if (cnt && !(res & (1 << 30)))<br>- return 0;<br>-<br>- printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n",<br>- d->branch->num, d->channel->num, d->num, rank);<br>- return -1;<br>-}<br>-<br>-static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d)<br>-{<br>- if (i5000_do_amb_membist_start(d, 1, 0))<br>- return -1;<br>- return 0;<br>-}<br>-<br>-static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d)<br>-{<br>-<br>- if (d->ranks < 2)<br>- return 0;<br>- if (i5000_do_amb_membist_start(d, 2, 0))<br>- return -1;<br>- return 0;<br>-}<br>-<br>-static int i5000_amb_membist_status1(struct i5000_fbdimm *d)<br>-{<br>- if (i5000_do_amb_membist_status(d, 1))<br>- return -1;<br>- return 0;<br>-}<br>-<br>-static int i5000_amb_membist_status2(struct i5000_fbdimm *d)<br>-{<br>- if (d->ranks < 2)<br>- return 0;<br>-<br>- if (i5000_do_amb_membist_status(d, 2))<br>- return -1;<br>- return 0;<br>-}<br>-<br>-static int i5000_amb_membist_end(struct i5000_fbdimm *d)<br>-{<br>- printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC));<br>- return 0;<br>-}<br>-<br>-static int i5000_membist(struct i5000_fbd_setup *setup)<br>-{<br>- return i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) ||<br>- i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||<br>- i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) ||<br>- i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||<br>- i5000_for_each_dimm_present(setup, i5000_amb_membist_end);<br>-}<br>-<br>-static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d)<br>-{<br>- u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC);<br>- tmp &= ~(1 << 16);<br>- printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp);<br>- i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp);<br>- return 0;<br>-}<br>-<br>-static int i5000_amb_clear_error_status(struct i5000_fbdimm *d)<br>-{<br>- i5000_amb_write_config32(d, 1, AMB_FERR, 9);<br>- i5000_amb_write_config32(d, 1, AMB_NERR, 9);<br>- i5000_amb_write_config32(d, 1, AMB_EMASK, 0xf2);<br>- i5000_amb_write_config8(d, 3, 0x80, 0xcf);<br>- i5000_amb_write_config8(d, 3, 0x81, 0xd3);<br>- i5000_amb_write_config8(d, 3, 0x82, 0xf8);<br>- return 0;<br>-}<br>-<br>-static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)<br>-{<br>- u32 val;<br>-<br>- if (c->dimm[0].present || c->dimm[1].present) {<br>- val = (((c->columns - 10) & 3) |<br>- (((c->rows - 13) & 3) << 2) |<br>- (((c->ranks == 2) ? 1 : 0) << 4) |<br>- (((c->banks == 8) ? 1 : 0) << 5) |<br>- ((c->width ? 1 : 0) << 6) |<br>- (1 << 7) | /* Electrical Throttling enabled */<br>- (1 << 8)); /* DIMM present and compatible */<br>- printk(BIOS_DEBUG, "MTR0: %04x\n", val);<br>- pci_write_config16(c->branch->branchdev, mtr, val);<br>- }<br>-<br>- if (c->dimm[2].present || c->dimm[3].present) {<br>- val = (((c->columns - 10) & 3) |<br>- (((c->rows - 13) & 3) << 4) |<br>- ((c->ranks ? 1 : 0) << 4) |<br>- (((c->banks == 8) ? 1 : 0) << 5) |<br>- ((c->width ? 1 : 0) << 6) |<br>- (1 << 7) | /* Electrical Throttling enabled */<br>- (1 << 8)); /* DIMM present and compatible */<br>- printk(BIOS_DEBUG, "MTR1: %04x\n", val);<br>- pci_write_config16(c->branch->branchdev, mtr+2, val);<br>- }<br>-}<br>-<br>-static int get_dmir(u8 *rankmap, int *_set, int limit)<br>-{<br>- int i, dmir = 0, set = 0;<br>-<br>- for (i = 7; set < limit && i >= 0; i--) {<br>- if (!(*rankmap & (1 << i)))<br>- continue;<br>-<br>- *rankmap &= ~(1 << i);<br>-<br>- switch(limit) {<br>- case 1:<br>- dmir |= (i |<br>- (i << 3) |<br>- (i << 6) |<br>- (i << 9));<br>- break;<br>- case 2:<br>- dmir |= (i << (set * 3)) |<br>- (i << (6 + set * 3));<br>- break;<br>- case 4:<br>- dmir |= (i << (set * 3));<br>- break;<br>-<br>- default:<br>- break;<br>- }<br>- set++;<br>- }<br>- *_set = set;<br>- return dmir;<br>-}<br>-<br>-static int i5000_setup_dmir(struct i5000_fbd_branch *b)<br>-{<br>- struct i5000_fbdimm *d;<br>- pci_devfn_t dev = b->branchdev;<br>- u8 rankmap = 0, dmir = 0;<br>- u32 dmirval = 0;<br>- int i, set, rankoffset = 0, ranksize = 0, ranks = 0;<br>-<br>- if (!b->used)<br>- return 0;<br>-<br>- for (i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {<br>- rankmap >>= 2;<br>- d = b->channel[0].dimm + i;<br>-<br>- if (!d->present)<br>- continue;<br>-<br>- if (d->ranks == 2) {<br>- rankmap |= 0xc0;<br>- ranks += 2;<br>- } else {<br>- rankmap |= 0x40;<br>- ranks++;<br>- }<br>- }<br>-<br>- printk(BIOS_DEBUG, "total ranks: %d, rankmap: %02x\n", ranks, rankmap);<br>-<br>- dmir = I5000_DMIR0;<br>-<br>- ranksize = b->channel[0].dimm[0].ranksize << 8;<br>-<br>- if (!b->setup->single_channel)<br>- ranksize <<= 1;<br>-<br>- while (ranks) {<br>-<br>- if (ranks >= 4)<br>- dmirval = get_dmir(&rankmap, &set, 4);<br>- else if (ranks >= 2)<br>- dmirval = get_dmir(&rankmap, &set, 2);<br>- else<br>- dmirval = get_dmir(&rankmap, &set, 1);<br>-<br>- ranks -= set;<br>-<br>- dmirval |= rankoffset + (set * ranksize);<br>-<br>- rankoffset += (set * ranksize);<br>-<br>- printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,<br>- dmirval);<br>- pci_write_config32(dev, dmir, dmirval);<br>- dmir += 4;<br>- }<br>-<br>- for (; dmir <= I5000_DMIR4; dmir += 4) {<br>- printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,<br>- dmirval);<br>- pci_write_config32(dev, dmir, dmirval);<br>- }<br>- return rankoffset;<br>-}<br>-<br>-static void i5000_setup_interleave(struct i5000_fbd_setup *setup)<br>-{<br>- pci_devfn_t dev16 = PCI_ADDR(0, 16, 1, 0);<br>- u32 mir0, mir1, mir2, size0, size1, minsize, tmp;<br>-<br>- size0 = i5000_setup_dmir(&setup->branch[1]) >> 12;<br>- size1 = i5000_setup_dmir(&setup->branch[0]) >> 12;<br>-<br>- minsize = MIN(size0, size1);<br>-<br>- if (size0 > size1) {<br>- tmp = size1;<br>- size1 = size0;<br>- size0 = tmp;<br>- }<br>-<br>- if (size0 == size1) {<br>- mir0 = (size0 << 1) | 3;<br>- mir1 = (size0 << 1);<br>- mir2 = (size0 << 1);<br>- } else if (!size0) {<br>- mir0 = size1 | 1;<br>- mir1 = size1;<br>- mir2 = size1;<br>- } else {<br>- mir0 = (size0 << 1) | 3;<br>- mir1 = (size1 + size0) | 1;<br>- mir2 = size1 + size0;<br>- }<br>-<br>- printk(BIOS_DEBUG, "MIR0: %04x\n", mir0);<br>- printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);<br>- printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);<br>-<br>- pci_write_config16(dev16, I5000_MIR0, mir0);<br>- pci_write_config16(dev16, I5000_MIR1, mir1);<br>- pci_write_config16(dev16, I5000_MIR2, mir2);<br>-}<br>-<br>-static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)<br>-{<br>- pci_devfn_t dev16 = PCI_ADDR(0, 16, 1, 0);<br>- u32 tolm, drta, drtb, mc, mca;<br>- int t_wrc, bl2;<br>-<br>- bl2 = (setup->bl & BL_BL8) ? 4 :2;<br>- t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 +<br>- setup->t_wr + setup->t_rp;<br>-<br>- drta = (setup->t_ref & 0x0f) |<br>- ((setup->t_rrd & 0x0f) << 4) |<br>- ((setup->t_rfc & 0xff) << 8) |<br>- ((setup->t_rc & 0x3f) << 16) |<br>- ((t_wrc & 0x3f) << 22) |<br>- (setup->t_al & 0x07) << 28;<br>-<br>- drtb = (bl2) |<br>- (((1 + bl2 + setup->t_r2r) & 0x0f) << 4) |<br>- (((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) |<br>- (((2 + bl2 + setup->t_r2w) & 0x0f) << 12) |<br>- (((bl2 + setup->t_w2rdr) & 0x07) << 16);<br>-<br>- mc = (1 << 30) | /* enable retry */<br>- (3 << 25) | /* bad RAM threshold */<br>- (1 << 21) | /* INITDONE */<br>- (1 << 20) | /* FSB enable */<br>- /* Electrical throttling: 20 clocks */<br>- ((setup->ddr_speed == DDR_667MHZ ? 1 : 0) << 18) |<br>- (1 << 8) | /* enhanced scrub mode */<br>- (1 << 7) | /* enable patrol scrub */<br>- (1 << 6) | /* enable demand scrubbing */<br>- (1 << 5); /* enable northbound error detection */<br>-<br>- printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc);<br>- pci_write_config32(dev16, I5000_DRTA, drta);<br>- pci_write_config32(dev16, I5000_DRTB, drtb);<br>- pci_write_config32(dev16, I5000_MC, mc);<br>-<br>- mca = pci_read_config32(dev16, I5000_MCA);<br>-<br>- mca |= (7 << 28);<br>- if (setup->single_channel)<br>- mca |= (1 << 14);<br>- else<br>- mca &= ~(1 << 14);<br>- printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca);<br>- pci_write_config32(dev16, I5000_MCA, mca);<br>-<br>- pci_write_config32(dev16, I5000_ERRPERR, 0xffffffff);<br>-<br>- i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0);<br>- i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1);<br>- i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0);<br>- i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1);<br>-<br>- i5000_setup_interleave(setup);<br>-<br>- if ((tolm = MIN(setup->totalmem, 0xd00)) > 0xd00)<br>- tolm = 0xd00;<br>-<br>- tolm <<= 4;<br>- printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm);<br>- pci_write_config16(dev16, I5000_TOLM, tolm);<br>- return 0;<br>-}<br>-<br>-static void i5000_init_setup(struct i5000_fbd_setup *setup)<br>-{<br>- int branch, channel, dimm, i = 0;<br>- struct i5000_fbdimm *d;<br>- struct i5000_fbd_channel *c;<br>- struct i5000_fbd_branch *b;<br>-<br>- setup->bl = 3;<br>- /* default to highest memory frequency. If a module doesn't<br>- support it, it will decrease this setting in spd_read */<br>- setup->ddr_speed = DDR_667MHZ;<br>-<br>- for (branch = 0; branch < I5000_MAX_BRANCH; branch++) {<br>- b = setup->branch + branch;<br>- b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0);<br>- b->setup = setup;<br>- b->num = branch;<br>-<br>- for (channel = 0; channel < I5000_MAX_CHANNEL; channel++) {<br>- c = b->channel + channel;<br>- c->branch = b;<br>- c->setup = setup;<br>- c->num = channel;<br>-<br>- for (dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) {<br>- d = c->dimm + dimm;<br>- setup->dimms[i++] = d;<br>- d->channel = c;<br>- d->branch = b;<br>- d->setup = setup;<br>- d->num = dimm;<br>- d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11);<br>- }<br>- }<br>- }<br>-}<br>-<br>-static void i5000_reserved_register_init(struct i5000_fbd_setup *setup)<br>-{<br>- /* register write captured from vendor BIOS, but undocumented by Intel */<br>- pci_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);<br>-<br>- pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);<br>- pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80);<br>- pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08);<br>- pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d);<br>- pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d);<br>-<br>- pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000);<br>- pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000);<br>- pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff);<br>-<br>- pci_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000);<br>- pci_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000);<br>- pci_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000);<br>- pci_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000);<br>-<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000);<br>-<br>- pci_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007);<br>- pci_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f);<br>-<br>- pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10);<br>- pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10);<br>-<br>- pci_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001);<br>- pci_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042);<br>- pci_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000);<br>- pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000);<br>- pci_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002);<br>- pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800);<br>-<br>- if (setup->branch[0].channel[0].used)<br>- pci_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10);<br>-<br>- if (setup->branch[0].channel[1].used)<br>- pci_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10);<br>-<br>- if (setup->branch[1].channel[0].used)<br>- pci_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10);<br>-<br>- if (setup->branch[1].channel[1].used)<br>- pci_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10);<br>-}<br>-static void i5000_dump_error_registers(void)<br>-{<br>- pci_devfn_t dev = PCI_ADDR(0, 16, 1, 0);<br>-<br>- printk(BIOS_ERR, "Dump of FBD error registers:\n"<br>- "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n"<br>- "FERR_NF_FBD: 0x%08x NERR_NF_FBD: 0x%08x\n"<br>- "EMASK_FBD: 0x%08x\n"<br>- "ERR0_FBD: 0x%08x\n"<br>- "ERR1_FBD: 0x%08x\n"<br>- "ERR2_FBD: 0x%08x\n"<br>- "MC_ERR_FBD: 0x%08x\n",<br>- pci_read_config32(dev, I5000_FERR_FAT_FBD),<br>- pci_read_config32(dev, I5000_NERR_FAT_FBD),<br>- pci_read_config32(dev, I5000_FERR_NF_FBD),<br>- pci_read_config32(dev, I5000_NERR_NF_FBD),<br>- pci_read_config32(dev, I5000_EMASK_FBD),<br>- pci_read_config32(dev, I5000_ERR0_FBD),<br>- pci_read_config32(dev, I5000_ERR1_FBD),<br>- pci_read_config32(dev, I5000_ERR2_FBD),<br>- pci_read_config32(dev, I5000_MCERR_FBD));<br>-<br>- printk(BIOS_ERR, "Non recoverable error registers:\n"<br>- "NRECMEMA: 0x%08x NRECMEMB: 0x%08x\n"<br>- "NRECFGLOG: 0x%08x\n",<br>- pci_read_config32(dev, I5000_NRECMEMA),<br>- pci_read_config32(dev, I5000_NRECMEMB),<br>- pci_read_config32(dev, I5000_NRECFGLOG));<br>-<br>- printk(BIOS_ERR, "Packet data:\n"<br>- "NRECFBDA: 0x%08x\n"<br>- "NRECFBDB: 0x%08x\n"<br>- "NRECFBDC: 0x%08x\n"<br>- "NRECFBDD: 0x%08x\n"<br>- "NRECFBDE: 0x%08x\n",<br>- pci_read_config32(dev, I5000_NRECFBDA),<br>- pci_read_config32(dev, I5000_NRECFBDB),<br>- pci_read_config32(dev, I5000_NRECFBDC),<br>- pci_read_config32(dev, I5000_NRECFBDD),<br>- pci_read_config32(dev, I5000_NRECFBDE));<br>-<br>- printk(BIOS_ERR, "recoverable error registers:\n"<br>- "RECMEMA: 0x%08x RECMEMB: 0x%08x\n"<br>- "RECFGLOG: 0x%08x\n",<br>- pci_read_config32(dev, I5000_RECMEMA),<br>- pci_read_config32(dev, I5000_RECMEMB),<br>- pci_read_config32(dev, I5000_RECFGLOG));<br>-<br>- printk(BIOS_ERR, "Packet data:\n"<br>- "RECFBDA: 0x%08x\n"<br>- "RECFBDB: 0x%08x\n"<br>- "RECFBDC: 0x%08x\n"<br>- "RECFBDD: 0x%08x\n"<br>- "RECFBDE: 0x%08x\n",<br>- pci_read_config32(dev, I5000_RECFBDA),<br>- pci_read_config32(dev, I5000_RECFBDB),<br>- pci_read_config32(dev, I5000_RECFBDC),<br>- pci_read_config32(dev, I5000_RECFBDD),<br>- pci_read_config32(dev, I5000_RECFBDE));<br>-<br>-}<br>-<br>-static void i5000_try_restart(const char *msg)<br>-{<br>- printk(BIOS_INFO, "%s", msg);<br>- i5000_dump_error_registers();<br>- outb(0x06, 0xcf9);<br>- halt();<br>-}<br>-<br>-static void i5000_pam_setup(void)<br>-{<br>- pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30);<br>- pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33);<br>- pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33);<br>- pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33);<br>- pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33);<br>- pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33);<br>- pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33);<br>-}<br>-<br>-static int i5000_setup_clocking(struct i5000_fbd_setup *setup)<br>-{<br>- int fbd, fsb, ddrfrq, ddrfrqnow;<br>- msr_t msr;<br>- pci_devfn_t dev = PCI_ADDR(0, 16, 1, 0);<br>-<br>- switch(setup->ddr_speed) {<br>- case DDR_667MHZ:<br>- fbd = 667;<br>- break;<br>- case DDR_533MHZ:<br>- fbd = 533;<br>- break;<br>- default:<br>- printk(BIOS_ERR, "%s: unsupported FBD speed\n", __func__);<br>- return 1;<br>- }<br>-<br>- /* mainboard specific callback */<br>- if (mainboard_set_fbd_clock(fbd)) {<br>- printk(BIOS_ERR, "%s: failed to set FBD speed\n", __func__);<br>- return 1;<br>- }<br>-<br>- msr = rdmsr(MSR_FSB_FREQ);<br>-<br>- switch(msr.lo & 7) {<br>- case 1:<br>- fsb = 533;<br>- break;<br>- case 4:<br>- fsb = 667;<br>- break;<br>- default:<br>- printk(BIOS_ERR, "%s: unsupported FSB speed: %d\n", __func__, msr.lo & 7);<br>- return 1;<br>- }<br>-<br>-<br>- ddrfrq = pci_read_config8(PCI_ADDR(0, 16, 1, 0), 0x56);<br>- ddrfrqnow = ddrfrq;<br>- ddrfrq &= ~0x3;<br>-<br>- if (fsb < fbd)<br>- ddrfrq |= 2;<br>- else if (fsb > fbd)<br>- ddrfrq |= 3;<br>-<br>- switch((ddrfrq >> 4) & 3) {<br>- case 0: /* 1:1 mapping */<br>- pci_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0xffffffff);<br>- pci_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000);<br>- pci_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0xffffffff);<br>- pci_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00);<br>- pci_write_config8(dev, I5000_GRHOSTFULLCFG, 0x00);<br>- pci_write_config8(dev, I5000_GRBUBBLECFG, 0x00);<br>- pci_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00);<br>- break;<br>- case 2: /* 4:5 mapping */<br>- pci_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00002323);<br>- pci_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000400);<br>- pci_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x23023);<br>- pci_write_config8(dev, I5000_GRFBDLVLDCFG, 0x04);<br>- pci_write_config8(dev, I5000_GRHOSTFULLCFG, 0x08);<br>- pci_write_config8(dev, I5000_GRBUBBLECFG, 0x00);<br>- pci_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x04);<br>- break;<br>- case 3:<br>- /* 5:4 mapping */<br>- pci_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00023230);<br>- pci_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000);<br>- pci_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x4323);<br>- pci_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00);<br>- pci_write_config8(dev, I5000_GRHOSTFULLCFG, 0x02);<br>- pci_write_config8(dev, I5000_GRBUBBLECFG, 0x10);<br>- pci_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00);<br>- break;<br>- default:<br>- printk(BIOS_DEBUG, "invalid DDRFRQ: %02x\n", ddrfrq);<br>- return -1;<br>- }<br>-<br>- if (ddrfrq != ddrfrqnow) {<br>- printk(BIOS_DEBUG, "old DDRFRQ: 0x%02x new DDRFRQ: 0x%02x\n",<br>- ddrfrqnow, ddrfrq);<br>- pci_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq);<br>- /* FSB:FBD mapping changed, needs hard reset */<br>- outb(0x06, 0xcf9);<br>- halt();<br>- }<br>- return 0;<br>-}<br>-<br>-void i5000_fbdimm_init(void)<br>-{<br>- struct i5000_fbd_setup setup;<br>- u32 mca, mc;<br>-<br>- memset(&setup, 0, sizeof(setup));<br>-<br>- pci_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144);<br>-<br>- i5000_init_setup(&setup);<br>-<br>- pci_write_config32(PCI_DEV(0, 16, 0), 0xf0,<br>- pci_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000);<br>-<br>- i5000_clear_fbd_errors();<br>-<br>- printk(BIOS_INFO, "detecting memory modules\n");<br>- if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) {<br>- printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__);<br>- return;<br>- }<br>-<br>- if (i5000_setup_clocking(&setup)) {<br>- printk(BIOS_ERR, "%s: failed to set FBD clock\n", __func__);<br>- return;<br>- }<br>-<br>- /* posted CAS requires t_AL = t_RCD - 1 */<br>- setup.t_al = setup.t_rcd - 1;<br>-<br>- printk(BIOS_DEBUG, "global timing parameters:\n"<br>- "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n"<br>- "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n",<br>- setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc,<br>- setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r,<br>- setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd,<br>- setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al);<br>-<br>- setup.single_channel = (!(setup.branch[0].channel[1].used ||<br>- setup.branch[1].channel[0].used ||<br>- setup.branch[1].channel[1].used));<br>-<br>- pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c);<br>- pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0);<br>-<br>- /* enable or disable single channel mode */<br>- mca = pci_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA);<br>- if (setup.single_channel)<br>- mca |= (1 << 14);<br>- else<br>- mca &= ~(1 << 14);<br>- pci_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca);<br>-<br>- /*<br>- * i5000 supports burst length 8 only in single channel mode<br>- * so strip BL_BL8 if we're operating in multichannel mode<br>- */<br>-<br>- if (!setup.single_channel)<br>- setup.bl &= ~BL_BL8;<br>-<br>- if (!setup.bl)<br>- die("No supported burst length found\n");<br>-<br>- mc = pci_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC);<br>- /* disable error checking for training */<br>- pci_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20);<br>-<br>- printk(BIOS_INFO, "performing fbd link initialization...");<br>- if (i5000_for_each_branch(&setup, i5000_branch_reset) ||<br>- i5000_for_each_dimm_present(&setup, i5000_amb_preinit) ||<br>- i5000_for_each_branch(&setup, i5000_link_training0) ||<br>- i5000_for_each_dimm_present(&setup, i5000_amb_check) ||<br>- i5000_for_each_dimm_present(&setup, i5000_amb_postinit) ||<br>- i5000_for_each_branch(&setup, i5000_link_training1)) {<br>- i5000_try_restart("failed\n");<br>- }<br>- printk(BIOS_INFO, "done\n");<br>- printk(BIOS_INFO, "initializing memory...");<br>-<br>- if (i5000_for_each_dimm_present(&setup, i5000_ddr_init) ||<br>- i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) ||<br>- i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) {<br>- i5000_try_restart("failed\n");<br>- }<br>- printk(BIOS_INFO,"done\n");<br>- printk(BIOS_INFO, "clearing memory...");<br>-<br>- if (i5000_membist(&setup))<br>- i5000_try_restart("failed\n");<br>- else<br>- printk(BIOS_INFO, "done\n");<br>-<br>- if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh))<br>- i5000_try_restart("failed to enable auto refresh\n");<br>-<br>- i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_INIT);<br>- i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_INIT);<br>-<br>- if (i5000_for_each_branch(&setup, i5000_link_training0))<br>- i5000_try_restart("Channel training failed\n");<br>-<br>- if (setup.branch[0].used)<br>- i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_READY);<br>-<br>- if (setup.branch[1].used)<br>- i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_READY);<br>-<br>- i5000_clear_fbd_errors();<br>-<br>- /* enable error checking */<br>- pci_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20);<br>-<br>- i5000_dram_timing_init(&setup);<br>-<br>- i5000_reserved_register_init(&setup);<br>-<br>- i5000_pam_setup();<br>-<br>- if (i5000_for_each_dimm_present(&setup, i5000_amb_clear_error_status))<br>- i5000_try_restart("failed to clear error status\n");<br>-<br>- if (setup.branch[0].used)<br>- i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE);<br>-<br>- if (setup.branch[1].used)<br>- i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE);<br>-<br>-#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK)<br>- if (ram_check_nodie(0x000000, 0x0a0000) ||<br>- ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xd0000000))) {<br>- i5000_try_restart("RAM verification failed");<br>-<br>- }<br>-#endif<br>-<br>- printk(BIOS_INFO, "Memory initialization finished\n");<br>-}<br>diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h<br>deleted file mode 100644<br>index 0c55443..0000000<br>--- a/src/northbridge/intel/i5000/raminit.h<br>+++ /dev/null<br>@@ -1,331 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org><br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef NORTHBRIDGE_I5000_RAMINIT_H<br>-#define NORTHBRIDGE_I5000_RAMINIT_H<br>-<br>-#include <types.h><br>-#include <arch/io.h><br>-<br>-#define I5000_MAX_BRANCH 2<br>-#define I5000_MAX_CHANNEL 2<br>-#define I5000_MAX_DIMM_PER_CHANNEL 4<br>-#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL)<br>-<br>-#define I5000_FBDRST 0x53<br>-<br>-#define I5000_SPD_BUSY (1 << 12)<br>-#define I5000_SPD_SBE (1 << 13)<br>-#define I5000_SPD_WOD (1 << 14)<br>-#define I5000_SPD_RDO (1 << 15)<br>-<br>-#define I5000_SPD0 0x74<br>-#define I5000_SPD1 0x76<br>-<br>-#define I5000_SPDCMD0 0x78<br>-#define I5000_SPDCMD1 0x7c<br>-<br>-#define I5000_FBDHPC 0x4f<br>-#define I5000_FBDST 0x4b<br>-<br>-#define I5000_FBDHPC_STATE_RESET 0x00<br>-#define I5000_FBDHPC_STATE_INIT 0x10<br>-#define I5000_FBDHPC_STATE_READY 0x20<br>-#define I5000_FBDHPC_STATE_ACTIVE 0x30<br>-<br>-#define I5000_FBDISTS0 0x58<br>-#define I5000_FBDISTS1 0x5a<br>-<br>-#define I5000_FBDLVL0 0x44<br>-#define I5000_FBDLVL1 0x45<br>-<br>-#define I5000_FBDICMD0 0x46<br>-#define I5000_FBDICMD1 0x47<br>-<br>-#define I5000_FBDICMD_IDLE 0x00<br>-#define I5000_FBDICMD_TS0 0x80<br>-#define I5000_FBDICMD_TS1 0x90<br>-#define I5000_FBDICMD_TS2 0xa0<br>-#define I5000_FBDICMD_TS3 0xb0<br>-#define I5000_FBDICMD_TS2_MERGE 0xd0<br>-#define I5000_FBDICMD_TS2_NOMERGE 0xe0<br>-#define I5000_FBDICMD_ALL_ONES 0xf0<br>-<br>-#define I5000_AMBPRESENT0 0x64<br>-#define I5000_AMBPRESENT1 0x66<br>-<br>-#define I5000_FBDSBTXCFG0 0xc0<br>-#define I5000_FBDSBTXCFG1 0xc1<br>-<br>-#define I5000_PROCENABLE 0xf0<br>-#define I5000_FBD0IBPORTCTL 0x180<br>-#define I5000_FBD0IBTXPAT2EN 0x1a8<br>-#define I5000_FBD0IBRXPAT2EN 0x1ac<br>-<br>-#define I5000_FBD0IBTXMSK 0x18c<br>-#define I5000_FBD0IBRXMSK 0x190<br>-<br>-#define I5000_FBDPLLCTRL 0x1c0<br>-<br>-/* dev 16, function 1 registers */<br>-#define I5000_MC 0x40<br>-#define I5000_DRTA 0x48<br>-#define I5000_DRTB 0x4c<br>-#define I5000_ERRPERR 0x50<br>-#define I5000_MCA 0x58<br>-#define I5000_TOLM 0x6c<br>-#define I5000_MIR0 0x80<br>-#define I5000_MIR1 0x84<br>-#define I5000_MIR2 0x88<br>-#define I5000_AMIR0 0x8c<br>-#define I5000_AMIR1 0x90<br>-#define I5000_AMIR2 0x94<br>-<br>-#define I5000_FERR_FAT_FBD 0x98<br>-#define I5000_NERR_FAT_FBD 0x9c<br>-#define I5000_FERR_NF_FBD 0xa0<br>-#define I5000_NERR_NF_FBD 0xa4<br>-#define I5000_EMASK_FBD 0xa8<br>-#define I5000_ERR0_FBD 0xac<br>-#define I5000_ERR1_FBD 0xb0<br>-#define I5000_ERR2_FBD 0xb4<br>-#define I5000_MCERR_FBD 0xb8<br>-#define I5000_NRECMEMA 0xbe<br>-#define I5000_NRECMEMB 0xc0<br>-#define I5000_NRECFGLOG 0xc4<br>-#define I5000_NRECMEMA 0xbe<br>-#define I5000_NRECFBDA 0xc8<br>-#define I5000_NRECFBDB 0xcc<br>-#define I5000_NRECFBDC 0xd0<br>-#define I5000_NRECFBDD 0xd4<br>-#define I5000_NRECFBDE 0xd8<br>-<br>-#define I5000_REDMEMB 0x7c<br>-#define I5000_RECMEMA 0xe2<br>-#define I5000_RECMEMB 0xe4<br>-#define I5000_RECFGLOG 0xe8<br>-#define I5000_RECFBDA 0xec<br>-#define I5000_RECFBDB 0xf0<br>-#define I5000_RECFBDC 0xf4<br>-#define I5000_RECFBDD 0xf8<br>-#define I5000_RECFBDE 0xfc<br>-<br>-#define I5000_FBDTOHOSTGRCFG0 0x160<br>-#define I5000_FBDTOHOSTGRCFG1 0x164<br>-#define I5000_HOSTTOFBDGRCFG 0x168<br>-#define I5000_GRFBDLVLDCFG 0x16c<br>-#define I5000_GRHOSTFULLCFG 0x16d<br>-#define I5000_GRBUBBLECFG 0x16e<br>-#define I5000_GRFBDTOHOSTDBLCFG 0x16f<br>-<br>-/* dev 16, function 2 registers */<br>-#define I5000_FERR_GLOBAL 0x40<br>-#define I5000_NERR_GLOBAL 0x44<br>-<br>-/* dev 21, function 0 registers */<br>-#define I5000_MTR0 0x80<br>-#define I5000_MTR1 0x84<br>-#define I5000_MTR2 0x88<br>-#define I5000_MTR3 0x8c<br>-#define I5000_DMIR0 0x90<br>-#define I5000_DMIR1 0x94<br>-#define I5000_DMIR2 0x98<br>-#define I5000_DMIR3 0x9c<br>-#define I5000_DMIR4 0xa0<br>-<br>-#define DEFAULT_AMBASE ((u8 *)0xfe000000)<br>-<br>-/* AMB function 1 registers */<br>-#define AMB_FBDSBCFGNXT 0x54<br>-#define AMB_FBDLOCKTO 0x68<br>-#define AMB_EMASK 0x8c<br>-#define AMB_FERR 0x90<br>-#define AMB_NERR 0x94<br>-#define AMB_CMD2DATANXT 0xe8<br>-<br>-/* AMB function 3 registers */<br>-#define AMB_DAREFTC 0x70<br>-#define AMB_DSREFTC 0x74<br>-#define AMB_DRT 0x78<br>-#define AMB_DRC 0x7c<br>-<br>-#define AMB_MBCSR 0x40<br>-#define AMB_MBADDR 0x44<br>-#define AMB_MBLFSRSED 0xa4<br>-<br>-/* AMB function 4 registers */<br>-#define AMB_DCALCSR 0x40<br>-#define AMB_DCALADDR 0x44<br>-#define AMB_DCALCSR_START (1 << 31)<br>-<br>-#define AMB_DCALCSR_OPCODE_NOP 0x00<br>-#define AMB_DCALCSR_OPCODE_REFRESH 0x01<br>-#define AMB_DCALCSR_OPCODE_PRECHARGE 0x02<br>-#define AMB_DCALCSR_OPCODE_MRS_EMRS 0x03<br>-#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL 0x05<br>-#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL 0x0c<br>-#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d<br>-<br>-#define AMB_DDR2ODTC 0xfc<br>-<br>-#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04<br>-#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07<br>-#define FBDIMM_SPD_FTB 0x08<br>-#define FBDIMM_SPD_MTB_DIVIDEND 0x09<br>-#define FBDIMM_SPD_MTB_DIVISOR 0x0a<br>-#define FBDIMM_SPD_MIN_TCK 0x0b<br>-#define FBDIMM_SPD_CAS_LATENCIES 0x0d<br>-#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e<br>-#define FBDIMM_SPD_T_WR 0x10<br>-#define FBDIMM_SPD_T_RCD 0x13<br>-#define FBDIMM_SPD_T_RRD 0x14<br>-#define FBDIMM_SPD_T_RP 0x15<br>-#define FBDIMM_SPD_T_RAS_RC_MSB 0x16<br>-#define FBDIMM_SPD_T_RAS 0x17<br>-#define FBDIMM_SPD_T_RC 0x18<br>-#define FBDIMM_SPD_T_RFC 0x19<br>-#define FBDIMM_SPD_T_WTR 0x1b<br>-#define FBDIMM_SPD_T_RTP 0x1c<br>-#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d<br>-#define FBDIMM_SPD_ODT 0x4f<br>-#define FBDIMM_SPD_T_REFI 0x20<br>-#define FBDIMM_SPD_T_BB 0x83<br>-#define FBDIMM_SPD_CMD2DATA_800 0x54<br>-#define FBDIMM_SPD_CMD2DATA_667 0x55<br>-#define FBDIMM_SPD_CMD2DATA_533 0x56<br>-<br>-void i5000_fbdimm_init(void);<br>-<br>-#define I5000_BURST4 0x01<br>-#define I5000_BURST8 0x02<br>-#define I5000_BURST_CHOP 0x80<br>-<br>-#define I5000_ODT_50 4<br>-#define I5000_ODT_75 2<br>-#define I5000_ODT_150 1<br>-<br>-enum ddr_speeds {<br>- DDR_533MHZ,<br>- DDR_667MHZ,<br>- DDR_MAX,<br>-};<br>-<br>-struct i5000_fbdimm {<br>- struct i5000_fbd_branch *branch;<br>- struct i5000_fbd_channel *channel;<br>- struct i5000_fbd_setup *setup;<br>- enum ddr_speeds speed;<br>- int num;<br>- int present:1;<br>- u32 ambase;<br>-<br>- /* SPD data */<br>- u8 amb_personality_bytes[14];<br>- u8 banks;<br>- u8 rows;<br>- u8 columns;<br>- u8 ranks;<br>- u8 odt;<br>- u8 sdram_width;<br>- u8 mtb_divisor;<br>- u8 mtb_dividend;<br>- u8 t_ck_min;<br>- u8 min_cas_latency;<br>- u8 t_rrd;<br>- u16 t_rfc;<br>- u8 t_wtr;<br>- u8 t_refi;<br>- u8 cmd2datanxt[DDR_MAX];<br>-<br>- u16 vendor;<br>- u16 device;<br>-<br>- /* memory rank size in MB */<br>- int ranksize;<br>-};<br>-<br>-struct i5000_fbd_channel {<br>- struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL];<br>- struct i5000_fbd_branch *branch;<br>- struct i5000_fbd_setup *setup;<br>- int num;<br>- int used;<br>- int highest_amb;<br>- int columns;<br>- int rows;<br>- int ranks;<br>- int banks;<br>- int width;<br>- /* memory size in MB on this channel */<br>- int totalmem;<br>-};<br>-<br>-struct i5000_fbd_branch {<br>- struct i5000_fbd_channel channel[I5000_MAX_CHANNEL];<br>- struct i5000_fbd_setup *setup;<br>- pci_devfn_t branchdev;<br>- int num;<br>- int used;<br>- /* memory size in MB on this branch */<br>- int totalmem;<br>-};<br>-<br>-enum odt {<br>- ODT_150OHM=1,<br>- ODT_50OHM=4,<br>- ODT_75OHM=2,<br>-};<br>-<br>-enum bl {<br>- BL_BL4=1,<br>- BL_BL8=2,<br>-};<br>-<br>-struct i5000_fbd_setup {<br>- struct i5000_fbd_branch branch[I5000_MAX_BRANCH];<br>- struct i5000_fbdimm *dimms[I5000_MAX_DIMMS];<br>- enum bl bl;<br>- enum ddr_speeds ddr_speed;<br>-<br>- int single_channel:1;<br>- u32 tolm;<br>-<br>- /* global SDRAM timing parameters */<br>- u8 t_al;<br>- u8 t_cl;<br>- u8 t_ras;<br>- u8 t_wrc;<br>- u8 t_rc;<br>- u8 t_rfc;<br>- u8 t_rrd;<br>- u8 t_ref;<br>- u8 t_w2rdr;<br>- u8 t_r2w;<br>- u8 t_w2r;<br>- u8 t_r2r;<br>- u8 t_w2w;<br>- u8 t_wtr;<br>- u8 t_rcd;<br>- u8 t_rp;<br>- u8 t_wr;<br>- u8 t_rtp;<br>- /* memory size in MB */<br>- int totalmem;<br>-};<br>-<br>-int mainboard_set_fbd_clock(int);<br>-#define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff)))<br>-#endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/22030">change 22030</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22030"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00 </div>
<div style="display:none"> Gerrit-Change-Number: 22030 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>