<p>Bora Guvendik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22008">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/cannonlake_rvp: enable HS400<br><br>Set SCS emmc HS400 enable FSP parameter.<br><br>Change-Id: I3ef8a6740ef985a0c51115d9b0ea753b5db2c70d<br>Signed-off-by: Bora Guvendik <bora.guvendik@intel.com><br>---<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>2 files changed, 2 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/22008/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>index 00c3e00..54d2a69 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>@@ -9,6 +9,7 @@<br>  register "FspSkipMpInit" = "1"<br>    register "SmbusEnable" = "1"<br>      register "ScsEmmcEnabled" = "1"<br>+  register "ScsEmmcHs400Enabled" = "1"<br> <br>   register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"<br>        register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>index 086d650..bb75605 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>@@ -9,6 +9,7 @@<br>     register "FspSkipMpInit" = "1"<br>    register "SmbusEnable" = "1"<br>      register "ScsEmmcEnabled" = "1"<br>+  register "ScsEmmcHs400Enabled" = "1"<br> <br>   register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"<br>        register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"<br></pre><p>To view, visit <a href="https://review.coreboot.org/22008">change 22008</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22008"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3ef8a6740ef985a0c51115d9b0ea753b5db2c70d </div>
<div style="display:none"> Gerrit-Change-Number: 22008 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Bora Guvendik <bora.guvendik@intel.com> </div>