<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21984">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Refactor memory layout calculation<br><br>This patch split entire memory layout calculation into<br>two parts. 1. Generic memory layout 2. SoC specific<br>reserve memory layout.<br><br>usable memory start = TOLUD - Generic memory size -<br> - soc specific reserve memory size.<br><br>Change-Id: I56e253504a331c0663efb2b90eaa0567613aa508<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/cannonlake/memmap.c<br>1 file changed, 119 insertions(+), 48 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/21984/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c<br>index 0259cda..e5117ad 100644<br>--- a/src/soc/intel/cannonlake/memmap.c<br>+++ b/src/soc/intel/cannonlake/memmap.c<br>@@ -104,6 +104,115 @@<br> return false;<br> }<br> <br>+/* Calculate PTT size */<br>+static size_t get_ptt_size(void)<br>+{<br>+ /* Allocate 4KB for PTT if enabled */<br>+ return is_ptt_enable() ? 4*KiB : 0;<br>+}<br>+<br>+/* Calculate ME Stolen size */<br>+static size_t get_imr_size(void)<br>+{<br>+ size_t imr_size;<br>+<br>+ /* ME stolen memory */<br>+ imr_size = MCHBAR32(IMRLIMIT) - MCHBAR32(IMRBASE);<br>+<br>+ return imr_size;<br>+}<br>+<br>+/* Calculate PRMRR size based on user input PRMRR size and alignment */<br>+static size_t get_prmrr_size(uintptr_t dram_base,<br>+ const struct soc_intel_cannonlake_config *config)<br>+{<br>+ uintptr_t prmrr_base = dram_base;<br>+ size_t prmrr_size;<br>+<br>+ prmrr_size = config->PrmrrSize;<br>+<br>+ /* Allocate PRMRR memory for C6DRAM */<br>+ if (!prmrr_size) {<br>+ if (config->enable_c6dram)<br>+ prmrr_size = 1*MiB;<br>+ else<br>+ return 0;<br>+ }<br>+<br>+ /*<br>+ * PRMRR Sizes that are > 1MB and < 32MB are<br>+ * not supported and will fail out.<br>+ */<br>+ if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB))<br>+ die("PRMRR Sizes that are > 1MB and < 32MB are not"<br>+ "supported!\n");<br>+<br>+ prmrr_base -= prmrr_size;<br>+ if (prmrr_size >= 32*MiB)<br>+ prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB);<br>+ else<br>+ prmrr_base = ALIGN_DOWN(prmrr_base, 16*MiB);<br>+ /* PRMRR Area Size */<br>+ prmrr_size = dram_base - prmrr_base;<br>+<br>+ return prmrr_size;<br>+}<br>+<br>+/* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */<br>+static size_t calculate_traditional_mem_size(uintptr_t dram_base,<br>+ const struct device *dev)<br>+{<br>+ uintptr_t traditional_mem_base = dram_base;<br>+ size_t traditional_mem_size;<br>+<br>+ if (dev->enabled) {<br>+ /* Read BDSM from Host Bridge */<br>+ traditional_mem_base -= sa_get_dsm_size();<br>+<br>+ /* Read BGSM from Host Bridge */<br>+ traditional_mem_base -= sa_get_gsm_size();<br>+ }<br>+ /* Get TSEG size */<br>+ traditional_mem_base -= sa_get_tseg_size();<br>+<br>+ /* Get DPR size */<br>+ if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))<br>+ traditional_mem_base -= sa_get_dpr_size();<br>+<br>+ /* Traditional Area Size */<br>+ traditional_mem_size = dram_base - traditional_mem_base;<br>+<br>+ return traditional_mem_size;<br>+}<br>+<br>+/*<br>+ * Calculate Intel Reserved Memory size based on<br>+ * PRMRR size, Me stolen memory and PTT selection.<br>+ */<br>+static size_t calculate_reserved_mem_size(uintptr_t dram_base,<br>+ const struct device *dev)<br>+{<br>+ uintptr_t reserve_mem_base = dram_base;<br>+ size_t reserve_mem_size;<br>+ const struct soc_intel_cannonlake_config *config;<br>+<br>+ config = dev->chip_info;<br>+<br>+ /* Get PRMRR size */<br>+ reserve_mem_base -= get_prmrr_size(reserve_mem_base, config);<br>+<br>+ /* Get Tracehub size */<br>+ reserve_mem_base -= get_imr_size();<br>+<br>+ /* Get PTT size */<br>+ reserve_mem_base -= get_ptt_size();<br>+<br>+ /* Traditional Area Size */<br>+ reserve_mem_size = dram_base - reserve_mem_base;<br>+<br>+ return reserve_mem_size;<br>+}<br>+<br> /*<br> * Host Memory Map:<br> *<br>@@ -136,64 +245,25 @@<br> * the base registers from each other to determine sizes of the regions. In<br> * other words, the memory map is in a fixed order no matter what.<br> */<br>-static uintptr_t calculate_dram_base(void)<br>+static uintptr_t calculate_dram_base(size_t *reserved_mem_size)<br> {<br>- const struct soc_intel_cannonlake_config *config;<br>- const struct device *dev;<br> uintptr_t dram_base;<br>- uintptr_t prmrr_base;<br>- size_t prmrr_size;<br>- size_t imr_size;<br>+ const struct device *dev;<br> <br> dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));<br> if (!dev)<br>- die("ERROR - device not found!");<br>+ die("ERROR - IGD device not found!");<br> <br> /* Read TOLUD from Host Bridge offset */<br> dram_base = sa_get_tolud_base();<br> <br>- if (dev->enabled) {<br>- /* Read BDSM from Host Bridge */<br>- dram_base -= sa_get_dsm_size();<br>+ /* Get Intel Traditional Memory Range Size */<br>+ dram_base -= calculate_traditional_mem_size(dram_base, dev);<br> <br>- /* Read BGSM from Host Bridge */<br>- dram_base -= sa_get_gsm_size();<br>- }<br>- /* Get TSEG size */<br>- dram_base -= sa_get_tseg_size();<br>+ /* Get Intel Reserved Memory Range Size */<br>+ *reserved_mem_size = calculate_reserved_mem_size(dram_base, dev);<br> <br>- /* Get DPR size */<br>- if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))<br>- dram_base -= sa_get_dpr_size();<br>-<br>- config = dev->chip_info;<br>- prmrr_size = config->PrmrrSize;<br>-<br>- if (prmrr_size > 0) {<br>- /*<br>- * PRMRR Sizes that are > 1MB and < 32MB are<br>- * not supported and will fail out.<br>- */<br>- if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB))<br>- die("PRMRR Sizes that are > 1MB and < 32MB are not"<br>- "supported!\n");<br>-<br>- prmrr_base = dram_base - prmrr_size;<br>- if (prmrr_size >= 32*MiB)<br>- prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB);<br>- dram_base = prmrr_base;<br>- } else if (config->enable_c6dram && prmrr_size == 0) {<br>- /* Allocate PRMRR memory for C6DRAM */<br>- dram_base -= 1*MiB;<br>- }<br>-<br>- /* ME stolen memory */<br>- imr_size = MCHBAR32(IMRLIMIT) - MCHBAR32(IMRBASE);<br>- if (imr_size > 0)<br>- dram_base -= imr_size;<br>-<br>- if (is_ptt_enable())<br>- dram_base -= 4*KiB; /* Allocate 4KB for PTT if enable */<br>+ dram_base -= *reserved_mem_size;<br> <br> return dram_base;<br> }<br>@@ -201,8 +271,9 @@<br> void cbmem_top_init(void)<br> {<br> uintptr_t top;<br>+ size_t chipset_mem_size;<br> <br>- top = calculate_dram_base();<br>+ top = calculate_dram_base(&chipset_mem_size);<br> <br> write32(top_of_ram_register(), top);<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/21984">change 21984</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21984"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I56e253504a331c0663efb2b90eaa0567613aa508 </div>
<div style="display:none"> Gerrit-Change-Number: 21984 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>