<p>Youness Alaoui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21959">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">console/flashconsole: Enable support for postcar<br><br>If FSP 2.0 is used, then postcar stage is used and the flashconsole<br>as well as spi drivers needed to be added.<br><br>Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e<br>Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm><br>---<br>M src/drivers/spi/Makefile.inc<br>M src/soc/intel/common/block/gspi/Makefile.inc<br>M src/soc/intel/skylake/Makefile.inc<br>3 files changed, 8 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/21959/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc<br>index c594d4e..a7cf3a7 100644<br>--- a/src/drivers/spi/Makefile.inc<br>+++ b/src/drivers/spi/Makefile.inc<br>@@ -11,6 +11,7 @@<br> bootblock-y += flashconsole.c<br> romstage-y += flashconsole.c<br> ramstage-y += flashconsole.c<br>+postcar-y += flashconsole.c<br> smm-$(CONFIG_DEBUG_SMI) += flashconsole.c<br> <br> endif<br>@@ -98,3 +99,7 @@<br> smm-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c<br> smm-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c<br> endif<br>+<br>+postcar-y += spi-generic.c<br>+postcar-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY) += boot_device_rw_nommap.c<br>+postcar-$(CONFIG_SPI_FLASH) += spi_flash.c<br>\ No newline at end of file<br>diff --git a/src/soc/intel/common/block/gspi/Makefile.inc b/src/soc/intel/common/block/gspi/Makefile.inc<br>index 85cb18e..2eb13fa 100644<br>--- a/src/soc/intel/common/block/gspi/Makefile.inc<br>+++ b/src/soc/intel/common/block/gspi/Makefile.inc<br>@@ -2,3 +2,4 @@<br> romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c<br> ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c<br> verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c<br>+postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c<br>diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc<br>index d12ba08..9a8372b 100644<br>--- a/src/soc/intel/skylake/Makefile.inc<br>+++ b/src/soc/intel/skylake/Makefile.inc<br>@@ -82,6 +82,8 @@<br> <br> postcar-y += memmap.c<br> postcar-$(CONFIG_UART_DEBUG) += uart_debug.c<br>+postcar-y += gspi.c<br>+postcar-y += spi.c<br> <br> # cpu_microcode_bins += ???<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/21959">change 21959</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21959"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e </div>
<div style="display:none"> Gerrit-Change-Number: 21959 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Youness Alaoui <snifikino@gmail.com> </div>