<p>Pratikkumar V Prajapati has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21965">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Add GNVS variables and include SGX ASL<br><br>- add GNVS variables for SGX<br>- include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set<br><br>Change-Id: I112cad3cd871082b1884787084c4cc0ebdc7d08f<br>Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com><br>---<br>M src/soc/intel/apollolake/acpi/globalnvs.asl<br>M src/soc/intel/apollolake/acpi/southbridge.asl<br>M src/soc/intel/apollolake/include/soc/nvs.h<br>3 files changed, 12 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/21965/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl<br>index 6431fae..4aad29c 100644<br>--- a/src/soc/intel/apollolake/acpi/globalnvs.asl<br>+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl<br>@@ -42,6 +42,9 @@<br>      SCDP,   8,      // 0x29 - SD_CD GPIO portid<br>   SCDO,   8,      // 0x2A - GPIO pad offset relative to the community<br>   UIOR,   8,      // 0x2B - UART debug controller init on S3 resume<br>+    EPCS,   8,      // 0x2C - SGX Enabled status<br>+ EMNA,   64,     // 0x2D - 0x34 EPC base address<br>+      ELNG,   64,     // 0x35 - 0x3C EPC Length<br> <br>  /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */<br>  Offset (0x100),<br>diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl<br>index 823173f..97a25a2 100644<br>--- a/src/soc/intel/apollolake/acpi/southbridge.asl<br>+++ b/src/soc/intel/apollolake/acpi/southbridge.asl<br>@@ -52,3 +52,8 @@<br> <br> /* PCI _OSC */<br> #include <soc/intel/common/acpi/pci_osc.asl><br>+<br>+/* SGX */<br>+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)<br>+#include <soc/intel/common/acpi/sgx.asl><br>+#endif<br>diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h<br>index 9a09800..dd0746b 100644<br>--- a/src/soc/intel/apollolake/include/soc/nvs.h<br>+++ b/src/soc/intel/apollolake/include/soc/nvs.h<br>@@ -1,7 +1,7 @@<br> /*<br>  * This file is part of the coreboot project.<br>  *<br>- * Copyright (C) 2015 Intel Corp.<br>+ * Copyright (C) 2015-2017 Intel Corp.<br>  * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)<br>  *<br>  * This program is free software; you can redistribute it and/or modify<br>@@ -44,6 +44,9 @@<br>   uint8_t         scdo; /* 0x2A - GPIO pad offset relative to the community */<br>  uint8_t         uior; /* 0x2B - UART debug controller init on S3<br>                                       resume */<br>+   uint8_t         ecps; /* 0x2C - SGX Enabled status */<br>+        uint64_t        emna; /* 0x2D - 0x34 EPC base address */<br>+     uint64_t        elng; /* 0x35 - 0x3C EPC Length */<br>    uint8_t         unused[212];<br> <br>       /* ChromeOS specific (0x100 - 0xfff) */<br></pre><p>To view, visit <a href="https://review.coreboot.org/21965">change 21965</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21965"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I112cad3cd871082b1884787084c4cc0ebdc7d08f </div>
<div style="display:none"> Gerrit-Change-Number: 21965 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>