<p>Werner Zeh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21932">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/fsp_broadwell_de: Add timestamp functionality<br><br>Add a little code and set the Kconfig switch to enable timestamps on<br>FSP based implementation of Broadwell-DE. I have tested it by reading<br>back the timestamps with cbmem utility once the board has booted into<br>Lubuntu.<br><br>Change-Id: Idaa65a22a00382bf0c37acf2f5a1e07c6b1b42d9<br>Signed-off-by: Werner Zeh <werner.zeh@siemens.com><br>---<br>M src/soc/intel/fsp_broadwell_de/Kconfig<br>M src/soc/intel/fsp_broadwell_de/Makefile.inc<br>M src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h<br>A src/soc/intel/fsp_broadwell_de/tsc_freq.c<br>4 files changed, 35 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/21932/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig<br>index cfe3fb0..06b9ee2 100644<br>--- a/src/soc/intel/fsp_broadwell_de/Kconfig<br>+++ b/src/soc/intel/fsp_broadwell_de/Kconfig<br>@@ -25,6 +25,7 @@<br> select HAVE_INTEL_FIRMWARE<br> select SMM_TSEG<br> select HAVE_SMI_HANDLER<br>+ select COLLECT_TIMESTAMPS<br> <br> config CBFS_SIZE<br> hex<br>diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc<br>index 028c45d..38cc441 100644<br>--- a/src/soc/intel/fsp_broadwell_de/Makefile.inc<br>+++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc<br>@@ -16,6 +16,7 @@<br> ramstage-y += chip.c<br> ramstage-y += northcluster.c<br> ramstage-y += ramstage.c<br>+ramstage-y += tsc_freq.c<br> romstage-y += memmap.c<br> ramstage-y += memmap.c<br> ramstage-y += southcluster.c<br>@@ -24,11 +25,13 @@<br> ramstage-y += acpi.c<br> ramstage-y += smbus_common.c<br> ramstage-y += smbus.c<br>+romstage-y += tsc_freq.c<br> ramstage-y += smi.c<br> ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c<br> ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c<br> smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c<br> smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c<br>+smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c<br> <br> CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include<br> CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp<br>diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h<br>index 4c11f38..dc1ec19 100644<br>--- a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h<br>+++ b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h<br>@@ -26,4 +26,7 @@<br> #define TSEG_BASE 0xa8 /* TSEG base */<br> #define TSEG_LIMIT 0xac /* TSEG limit */<br> <br>+/* CPU bus clock is fixed at 100MHz */<br>+#define CPU_BCLK 100<br>+<br> #endif /* _SOC_BROADWELL_DE_H_ */<br>diff --git a/src/soc/intel/fsp_broadwell_de/tsc_freq.c b/src/soc/intel/fsp_broadwell_de/tsc_freq.c<br>new file mode 100644<br>index 0000000..4225a3a<br>--- /dev/null<br>+++ b/src/soc/intel/fsp_broadwell_de/tsc_freq.c<br>@@ -0,0 +1,28 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <stdint.h><br>+#include <cpu/x86/msr.h><br>+#include <cpu/x86/tsc.h><br>+#include <soc/msr.h><br>+#include <soc/broadwell_de.h><br>+<br>+unsigned long tsc_freq_mhz(void)<br>+{<br>+ msr_t platform_info;<br>+<br>+ platform_info = rdmsr(MSR_PLATFORM_INFO);<br>+ return CPU_BCLK * ((platform_info.lo >> 8) & 0xff);<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21932">change 21932</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21932"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idaa65a22a00382bf0c37acf2f5a1e07c6b1b42d9 </div>
<div style="display:none"> Gerrit-Change-Number: 21932 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Werner Zeh <werner.zeh@siemens.com> </div>