<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21912">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPI<br><br>Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all<br>skylake boards to use common gpio driver. Common gpio code<br>defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for<br>skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This<br>resulted in Linux kernel failing to configure all GPIO IRQs since the<br>ownership was not set correctly. (Observed error in dmesg: "genirq:<br>Setting trigger mode 3 for irq 201<br>failed (intel_gpio_irq_type+0x0/0x110)")<br><br>This change fixes the above issue by replacing all uses of PAD_CFG_GPI<br>in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.<br><br>BUG=b:67507004<br>TEST=Verified on soraka that the genirq error is no longer observed in<br>dmesg. Also, cat /proc/interrupts has the interrupts configured<br>correctly.<br><br>Change-Id: I7dab302f372e56864432100a56462b92d43060ee<br>Signed-off-by: Furquan Shaikh <furquan@chromium.org><br>---<br>M src/mainboard/google/chell/gpio.h<br>M src/mainboard/google/eve/gpio.h<br>M src/mainboard/google/fizz/gpio.h<br>M src/mainboard/google/glados/gpio.h<br>M src/mainboard/google/lars/gpio.h<br>M src/mainboard/google/poppy/variants/baseboard/gpio.c<br>M src/mainboard/google/poppy/variants/soraka/gpio.c<br>M src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h<br>M src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h<br>M src/mainboard/intel/kunimitsu/gpio.h<br>M src/mainboard/purism/librem13v2/gpio.h<br>11 files changed, 156 insertions(+), 127 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/21912/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h<br>index 6f30e1e..76b2d09 100644<br>--- a/src/mainboard/google/chell/gpio.h<br>+++ b/src/mainboard/google/chell/gpio.h<br>@@ -106,23 +106,23 @@<br> /* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),<br> /* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),<br> /* GSPI1_MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP),<br>-/* SM1ALERT# */ PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* UNUSED */<br>+/* SM1ALERT# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B23, NONE, DEEP), /* UNUSED */<br> /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */<br> /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */<br> /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),<br>-/* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* UNUSED */<br>-/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* UNUSED */<br>-/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* UNUSED */<br>-/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */<br>-/* SM1DATA */ PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* UNUSED */<br>+/* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* UNUSED */<br>+/* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* UNUSED */<br>+/* SML0ALERT# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C5, NONE, DEEP), /* UNUSED */<br>+/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */<br>+/* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), /* UNUSED */<br> /* UART0_RXD */ PAD_CFG_NC(GPP_C8),<br> /* UART0_TXD */ PAD_CFG_NC(GPP_C9),<br> /* UART0_RTS# */ PAD_CFG_NC(GPP_C10),<br> /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */<br>-/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */<br>-/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */<br>-/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */<br>-/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */<br>+/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */<br>+/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */<br>+/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */<br>+/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */<br> /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */<br> /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */<br> /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */<br>@@ -130,7 +130,7 @@<br> /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */<br> /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */<br> /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */<br>-/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */<br>+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */<br> /* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP),<br> /* SPI1_CLK */ PAD_CFG_GPO(GPP_D1, 0, DEEP),<br> /* SPI1_MISO */ PAD_CFG_GPO(GPP_D2, 0, DEEP),<br>@@ -184,10 +184,10 @@<br> * together with i2s0 signals. For default behavior of i2s make these<br> * gpio inupts.<br> */<br>-/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),<br>-/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),<br>-/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),<br>-/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),<br>+/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),<br>+/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),<br>+/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),<br>+/* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),<br> /* I2C2_SDA */ PAD_CFG_NC(GPP_F4),<br> /* I2C2_SCL */ PAD_CFG_NC(GPP_F5),<br> /* I2C3_SDA */ PAD_CFG_NC(GPP_F6),<br>@@ -234,7 +234,7 @@<br> static const struct pad_config early_gpio_table[] = {<br> /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */<br> /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */<br>-/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */<br>+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */<br> };<br> <br> #endif<br>diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h<br>index b885069..b9b37a0 100644<br>--- a/src/mainboard/google/eve/gpio.h<br>+++ b/src/mainboard/google/eve/gpio.h<br>@@ -100,16 +100,21 @@<br> /* SML0CLK */ PAD_CFG_NC(GPP_C3),<br> /* SML0DATA */ PAD_CFG_NC(GPP_C4),<br> /* SML0ALERT# */ PAD_CFG_NC(GPP_C5),<br>-/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */<br>+/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,<br>+ DEEP), /* EC_IN_RW */<br> /* SM1DATA */ PAD_CFG_NC(GPP_C7),<br> /* UART0_RXD */ PAD_CFG_NC(GPP_C8),<br> /* UART0_TXD */ PAD_CFG_NC(GPP_C9),<br> /* UART0_RTS# */ PAD_CFG_NC(GPP_C10),<br> /* UART0_CTS# */ PAD_CFG_NC(GPP_C11),<br>-/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */<br>-/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */<br>-/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */<br>-/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */<br>+/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,<br>+ DEEP), /* MEM_CONFIG[0] */<br>+/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,<br>+ DEEP), /* MEM_CONFIG[1] */<br>+/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,<br>+ DEEP), /* MEM_CONFIG[2] */<br>+/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,<br>+ DEEP), /* MEM_CONFIG[3] */<br> /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */<br> /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */<br> /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */<br>@@ -117,10 +122,12 @@<br> /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */<br> /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */<br> /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */<br>-/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */<br>+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU,<br>+ DEEP), /* PCH_WP */<br> <br> /* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* TOUCHPAD_BOOT */<br>-/* SPI1_CLK */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), /* TOUCHPAD_RESET */<br>+/* SPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D1, NONE,<br>+ DEEP), /* TOUCHPAD_RESET */<br> /* SPI1_MISO */ PAD_CFG_NC(GPP_D2),<br> /* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),<br> /* FASHTRIG */ PAD_CFG_NC(GPP_D4),<br>@@ -155,7 +162,8 @@<br> /* SATALED# */ PAD_CFG_NC(GPP_E8),<br> /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */<br> /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_C1_OC_ODL */<br>-/* USB2_OC2# */ PAD_CFG_GPI(GPP_E11, NONE, DEEP), /* TOUCHSCREEN_STOP_L */<br>+/* USB2_OC2# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E11, NONE,<br>+ DEEP), /* TOUCHSCREEN_STOP_L */<br> /* USB2_OC3# */ PAD_CFG_NC(GPP_E12),<br> /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), /* USB_C0_DP_HPD */<br> /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), /* USB_C1_DP_HPD */<br>@@ -170,14 +178,16 @@<br> /* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),<br> <br> /* The next 4 pads are for bit banging the amplifiers, default to I2S */<br>-/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),<br>-/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),<br>-/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),<br>-/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),<br>+/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),<br>+/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),<br>+/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),<br>+/* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),<br> /* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* TOUCHPAD */<br> /* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* TOUCHPAD */<br>-/* I2C3_SDA */ PAD_CFG_GPI(GPP_F6, NONE, DEEP), /* DISPLAY is master */<br>-/* I2C3_SCL */ PAD_CFG_GPI(GPP_F7, NONE, DEEP), /* DISPLAY is master */<br>+/* I2C3_SDA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F6, NONE,<br>+ DEEP), /* DISPLAY is master */<br>+/* I2C3_SCL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F7, NONE,<br>+ DEEP), /* DISPLAY is master */<br> /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */<br> /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */<br> /* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */<br>@@ -222,7 +232,8 @@<br> static const struct pad_config early_gpio_table[] = {<br> /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */<br> /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */<br>-/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */<br>+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU,<br>+ DEEP), /* PCH_WP */<br> /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */<br> <br> /* Ensure UART pins are in native mode for H1 */<br>diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h<br>index ae95286..330ba4e 100644<br>--- a/src/mainboard/google/fizz/gpio.h<br>+++ b/src/mainboard/google/fizz/gpio.h<br>@@ -49,13 +49,14 @@<br> /* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */<br> /* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */<br> /* BM_BUSY# */ PAD_CFG_NC(GPP_A12),<br>-/* SUSWARN# */ PAD_CFG_GPI(GPP_A13, NONE, DEEP), /* eSPI mode */<br>+/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE,<br>+ DEEP), /* eSPI mode */<br> /* ESPI_RESET# */<br> /* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */<br> /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),<br> /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),<br> /* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */<br>-/* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP), /* HDPO */<br>+/* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */<br> /* ISH_GP2 */ PAD_CFG_NC(GPP_A20),<br> /* ISH_GP3 */ PAD_CFG_NC(GPP_A21),<br> /* ISH_GP4 */ PAD_CFG_NC(GPP_A22),<br>@@ -96,8 +97,10 @@<br> /* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),<br> #endif<br> /* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */<br>-/* GSPI1_CLK */ PAD_CFG_GPI(GPP_B20, 20K_PU, DEEP), /* VR_DISABLE_L */<br>-/* GSPI1_MISO */ PAD_CFG_GPI(GPP_B21, 20K_PU, DEEP), /* HWA_TRST_N */<br>+/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU,<br>+ DEEP), /* VR_DISABLE_L */<br>+/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU,<br>+ DEEP), /* HWA_TRST_N */<br> /* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */<br> /* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */<br> <br>@@ -107,16 +110,25 @@<br> /* SML0CLK */ PAD_CFG_NC(GPP_C3),<br> /* SML0DATA */ PAD_CFG_NC(GPP_C4),<br> /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),<br>-/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */<br>+/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,<br>+ DEEP), /* EC_IN_RW */<br> /* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */<br>-/* UART0_RXD */ PAD_CFG_GPI(GPP_C8, 20K_PU, DEEP), /* GPIO1 */<br>-/* UART0_TXD */ PAD_CFG_GPI(GPP_C9, 20K_PU, DEEP), /* GPIO2 */<br>-/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, 20K_PU, DEEP), /* GPIO3 */<br>-/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, 20K_PU, DEEP), /* GPIO4 */<br>-/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* SKU_ID0 */<br>-/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* SKU_ID1 */<br>-/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* SKU_ID2 */<br>-/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* SKU_ID3 */<br>+/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU,<br>+ DEEP), /* GPIO1 */<br>+/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU,<br>+ DEEP), /* GPIO2 */<br>+/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU,<br>+ DEEP), /* GPIO3 */<br>+/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU,<br>+ DEEP), /* GPIO4 */<br>+/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,<br>+ DEEP), /* SKU_ID0 */<br>+/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,<br>+ DEEP), /* SKU_ID1 */<br>+/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,<br>+ DEEP), /* SKU_ID2 */<br>+/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,<br>+ DEEP), /* SKU_ID3 */<br> /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),<br> /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),<br> #if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM)<br>@@ -131,7 +143,7 @@<br> /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */<br> /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */<br> /* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */<br>-/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, NONE,<br>+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,<br> DEEP), /* SCREW_SPI_WP_STATUS */<br> <br> /* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */<br>@@ -270,7 +282,7 @@<br> /* Ensure UART pins are in native mode for H1. */<br> /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */<br> /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */<br>-/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, NONE,<br>+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,<br> DEEP), /* SCREW_SPI_WP_STATUS */<br> };<br> <br>diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h<br>index 8e5e162..acd0ead 100644<br>--- a/src/mainboard/google/glados/gpio.h<br>+++ b/src/mainboard/google/glados/gpio.h<br>@@ -107,19 +107,24 @@<br> /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */<br> /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */<br> /* SMBALERT# */ /* GPP_C2 */<br>-/* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP),<br>-/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP),<br>+/* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP),<br>+/* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP),<br> /* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP),<br>-/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */<br>-/* SM1DATA */ PAD_CFG_GPI(GPP_C7, NONE, DEEP),<br>+/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,<br>+ DEEP), /* EC_IN_RW */<br>+/* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP),<br> /* UART0_RXD */ /* GPP_C8 */<br> /* UART0_TXD */ /* GPP_C9 */<br> /* UART0_RTS# */ /* GPP_C10 */<br> /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */<br>-/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */<br>-/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */<br>-/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */<br>-/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */<br>+/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,<br>+ DEEP), /* MEM_CONFIG[0] */<br>+/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,<br>+ DEEP), /* MEM_CONFIG[1] */<br>+/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,<br>+ DEEP), /* MEM_CONFIG[2] */<br>+/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,<br>+ DEEP), /* MEM_CONFIG[3] */<br> /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */<br> /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */<br> /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */<br>@@ -127,7 +132,8 @@<br> /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */<br> /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */<br> /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */<br>-/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */<br>+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU,<br>+ DEEP), /* PCH_WP */<br> /* GPP_D0 */<br> /* GPP_D1 */<br> /* GPP_D2 */<br>@@ -181,10 +187,10 @@<br> * together with i2s0 signals. For default behavior of i2s make these<br> * gpio inupts.<br> */<br>-/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),<br>-/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),<br>-/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),<br>-/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),<br>+/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),<br>+/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),<br>+/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),<br>+/* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),<br> /* I2C2_SDA */ /* GPP_F4 */<br> /* I2C2_SCL */ /* GPP_F5 */<br> /* I2C3_SDA */ /* GPP_F6 */<br>diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h<br>index 40960a7..77151a4 100644<br>--- a/src/mainboard/google/lars/gpio.h<br>+++ b/src/mainboard/google/lars/gpio.h<br>@@ -94,10 +94,10 @@<br> /* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),<br> /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),<br> /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),<br>-/* GPP_B_14_SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP),<br>+/* GPP_B_14_SPKR */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP),<br> /* GSPI0_CS# */ /* GPP_B15 */<br> /* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),<br>-/* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP),<br>+/* SSD_PCIE_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B17, NONE, DEEP),<br> /* GSPI0_MOSI */ /* GPP_B18 */<br> /* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),<br> /* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),<br>@@ -108,18 +108,18 @@<br> /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),<br> /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),<br> /* M2_WWAN_PWREN */ PAD_CFG_GPO(GPP_C3, 0, DEEP),<br>-/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP),<br>+/* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP),<br> /* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP),<br>-/* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP),<br>+/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP),<br> /* USB_CTL */ PAD_CFG_GPO(GPP_C7, 1, DEEP),<br> /* UART0_RXD */ /* GPP_C8 */<br> /* UART0_TXD */ /* GPP_C9 */<br> /* NFC_RST* */ PAD_CFG_GPO(GPP_C10, 0, DEEP),<br> /* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP),<br>-/* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP),<br>-/* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP),<br>-/* PCH_MEM_CFG2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),<br>-/* PCH_MEM_CFG3 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP),<br>+/* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),<br>+/* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),<br>+/* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),<br>+/* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),<br> /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),<br> /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),<br> /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),<br>@@ -127,7 +127,7 @@<br> /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),<br> /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),<br> /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP),<br>-/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),<br>+/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),<br> /* ITCH_SPI_CS */ /* GPP_D0 */<br> /* ITCH_SPI_CLK */ /* GPP_D1 */<br> /* ITCH_SPI_MISO_1 */ /* GPP_D2 */<br>@@ -174,12 +174,12 @@<br> /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),<br> /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),<br> /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),<br>-/* DDPD_CTRLCLK */ PAD_CFG_GPI(GPP_E22, NONE, DEEP),<br>+/* DDPD_CTRLCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E22, NONE, DEEP),<br> /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),<br>-/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),<br>-/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),<br>-/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),<br>-/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),<br>+/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),<br>+/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),<br>+/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),<br>+/* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),<br> /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),<br> /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),<br> /* I2C3_SDA */ /* GPP_F6 */<br>@@ -226,7 +226,7 @@<br> static const struct pad_config early_gpio_table[] = {<br> /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */<br> /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */<br>-/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),<br>+/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),<br> };<br> <br> #endif<br>diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c<br>index e74e4af..90a1611 100644<br>--- a/src/mainboard/google/poppy/variants/baseboard/gpio.c<br>+++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c<br>@@ -135,7 +135,7 @@<br> /* C5 : SML0ALERT# ==> NC */<br> PAD_CFG_NC(GPP_C5),<br> /* C6 : SM1CLK ==> EC_IN_RW_OD */<br>- PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),<br> /* C7 : SM1DATA ==> NC */<br> PAD_CFG_NC(GPP_C7),<br> /* C8 : UART0_RXD ==> FP_INT */<br>@@ -147,13 +147,13 @@<br> /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */<br> PAD_CFG_GPO(GPP_C11, 0, DEEP),<br> /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */<br>- PAD_CFG_GPI(GPP_C12, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),<br> /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */<br>- PAD_CFG_GPI(GPP_C13, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),<br> /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */<br>- PAD_CFG_GPI(GPP_C14, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),<br> /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */<br>- PAD_CFG_GPI(GPP_C15, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),<br> /* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */<br> PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),<br> /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */<br>@@ -176,14 +176,14 @@<br> /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */<br> PAD_CFG_GPO(GPP_C22, 0, DEEP),<br> /* C23 : UART2_CTS# ==> PCH_WP */<br>- PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),<br> <br> /* D0 : SPI1_CS# ==> NC */<br> PAD_CFG_NC(GPP_D0),<br> /* D1 : SPI1_CLK ==> PEN_IRQ_L */<br> PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST),<br> /* D2 : SPI1_MISO ==> PEN_PDCT_L */<br>- PAD_CFG_GPI(GPP_D2, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D2, NONE, DEEP),<br> /* D3 : SPI1_MOSI ==> NC */<br> PAD_CFG_NC(GPP_D3),<br> /* D4 : FASHTRIG ==> NC */<br>@@ -197,7 +197,7 @@<br> /* D8 : ISH_I2C1_SCL ==> NC */<br> PAD_CFG_NC(GPP_D8),<br> /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */<br>- PAD_CFG_GPI(GPP_D9, NONE, PLTRST),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST),<br> /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */<br> PAD_CFG_GPO(GPP_D10, 1, DEEP),<br> /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */<br>@@ -258,7 +258,7 @@<br> /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */<br> PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),<br> /* E15 : DDPD_HPD2 ==> SD_CD# */<br>- PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP),<br> /* E16 : DDPE_HPD3 ==> NC(TP244) */<br> PAD_CFG_NC(GPP_E16),<br> /* E17 : EDP_HPD */<br>@@ -278,13 +278,13 @@<br> <br> /* The next 4 pads are for bit banging the amplifiers, default to I2S */<br> /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */<br>- PAD_CFG_GPI(GPP_F0, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),<br> /* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */<br>- PAD_CFG_GPI(GPP_F1, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),<br> /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */<br>- PAD_CFG_GPI(GPP_F2, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),<br> /* F3 : I2S2_RXD */<br>- PAD_CFG_GPI(GPP_F3, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),<br> /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */<br> PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),<br> /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */<br>@@ -396,7 +396,7 @@<br> PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),<br> <br> /* C23 : UART2_CTS# ==> PCH_WP */<br>- PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),<br> <br> /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */<br> PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),<br>diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c<br>index cd1258d..92f866f 100644<br>--- a/src/mainboard/google/poppy/variants/soraka/gpio.c<br>+++ b/src/mainboard/google/poppy/variants/soraka/gpio.c<br>@@ -133,7 +133,7 @@<br> /* C5 : SML0ALERT# ==> NC */<br> PAD_CFG_NC(GPP_C5),<br> /* C6 : SM1CLK ==> EC_IN_RW_OD */<br>- PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),<br> /* C7 : SM1DATA ==> NC */<br> PAD_CFG_NC(GPP_C7),<br> /* C8 : UART0_RXD ==> FP_INT */<br>@@ -145,13 +145,13 @@<br> /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */<br> PAD_CFG_GPO(GPP_C11, 0, DEEP),<br> /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */<br>- PAD_CFG_GPI(GPP_C12, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),<br> /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */<br>- PAD_CFG_GPI(GPP_C13, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),<br> /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */<br>- PAD_CFG_GPI(GPP_C14, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),<br> /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */<br>- PAD_CFG_GPI(GPP_C15, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),<br> /* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */<br> PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),<br> /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */<br>@@ -174,7 +174,7 @@<br> /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */<br> PAD_CFG_GPO(GPP_C22, 0, DEEP),<br> /* C23 : UART2_CTS# ==> PCH_WP */<br>- PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),<br> <br> /* D0 : SPI1_CS# ==> NC */<br> PAD_CFG_NC(GPP_D0),<br>@@ -195,7 +195,7 @@<br> /* D8 : ISH_I2C1_SCL ==> NC */<br> PAD_CFG_NC(GPP_D8),<br> /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */<br>- PAD_CFG_GPI(GPP_D9, NONE, PLTRST),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST),<br> /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */<br> PAD_CFG_GPO(GPP_D10, 1, DEEP),<br> /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */<br>@@ -256,7 +256,7 @@<br> /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */<br> PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),<br> /* E15 : DDPD_HPD2 ==> SD_CD# */<br>- PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP),<br> /* E16 : DDPE_HPD3 ==> NC(TP244) */<br> PAD_CFG_NC(GPP_E16),<br> /* E17 : EDP_HPD */<br>@@ -276,13 +276,13 @@<br> <br> /* The next 4 pads are for bit banging the amplifiers, default to I2S */<br> /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */<br>- PAD_CFG_GPI(GPP_F0, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),<br> /* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */<br>- PAD_CFG_GPI(GPP_F1, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),<br> /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */<br>- PAD_CFG_GPI(GPP_F2, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),<br> /* F3 : I2S2_RXD */<br>- PAD_CFG_GPI(GPP_F3, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),<br> /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */<br> PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),<br> /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */<br>@@ -397,7 +397,7 @@<br> PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),<br> <br> /* C23 : UART2_CTS# ==> PCH_WP */<br>- PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),<br> <br> /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */<br> PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),<br>diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h<br>index c6f4123..64d0259 100644<br>--- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h<br>+++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h<br>@@ -48,7 +48,7 @@<br> /* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1),<br> /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),<br> /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),<br>-/* PM_SLP_S0ix_N */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),<br>+/* PM_SLP_S0ix_N */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP),<br> /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),<br> /* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),<br> /* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),<br>@@ -67,7 +67,7 @@<br> /* ISH_GP5 */ PAD_CFG_NC(GPP_A23),<br> /* V0.85A_VID0 */ PAD_CFG_NC(GPP_B0),<br> /* V0.85A_VID1 */ PAD_CFG_NC(GPP_B1),<br>-/* GP_VRALERTB */ PAD_CFG_GPI(GPP_B2, NONE, DEEP),<br>+/* GP_VRALERTB */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP),<br> /* TCH_PAD_INTR */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),<br> /* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP),<br> /* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5),<br>@@ -122,10 +122,10 @@<br> /* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),<br> /* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),<br> /* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),<br>-/* HOME_BTN */ PAD_CFG_GPI(GPP_D9, NONE, DEEP),<br>-/* SCREEN_LOCK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),<br>-/* VOL_UP_PCH */ PAD_CFG_GPI(GPP_D11, NONE, DEEP),<br>-/* VOL_DOWN_PCH */ PAD_CFG_GPI(GPP_D12, NONE, DEEP),<br>+/* HOME_BTN */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, DEEP),<br>+/* SCREEN_LOCK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP),<br>+/* VOL_UP_PCH */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP),<br>+/* VOL_DOWN_PCH */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP),<br> /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),<br> /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),<br> /* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),<br>@@ -139,7 +139,7 @@<br> /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),<br> /* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),<br> /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),<br>-/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),<br>+/* SSD_PEDET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E2, NONE, DEEP),<br> /* EINK_SSR_DFU_N */ PAD_CFG_GPO(GPP_E3, 1, DEEP),<br> /* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP),<br> /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),<br>diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h<br>index 2233339..07b52d3 100644<br>--- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h<br>+++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h<br>@@ -126,10 +126,10 @@<br> /* EN_PP1800_DX_EMMC */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),<br> /* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),<br> /* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),<br>- PAD_CFG_GPI(GPP_D9, NONE, DEEP),<br>-/* SD_D3_WAKE */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),<br>-/* USB_A1_ILIM_SEL */ PAD_CFG_GPI(GPP_D11, NONE, DEEP),<br>-/* EN_PP3300_DX_CAM */ PAD_CFG_GPI(GPP_D12, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, DEEP),<br>+/* SD_D3_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP),<br>+/* USB_A1_ILIM_SEL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP),<br>+/* EN_PP3300_DX_CAM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP),<br> /* EN_PP1800_DX_AUDIO */PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),<br> /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),<br> /* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),<br>@@ -143,7 +143,7 @@<br> /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),<br> /* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, 20K_PD, DEEP),<br> /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),<br>-/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),<br>+/* SSD_PEDET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E2, NONE, DEEP),<br> /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, RSMRST),<br> /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),<br> /* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),<br>diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h<br>index 473d9a0..721c74c 100644<br>--- a/src/mainboard/intel/kunimitsu/gpio.h<br>+++ b/src/mainboard/intel/kunimitsu/gpio.h<br>@@ -71,7 +71,7 @@<br> /* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),<br> /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),<br> /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),<br>-/* SD_CD_WAKE */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),<br>+/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP),<br> /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),<br> /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),<br> /* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10),<br>@@ -90,7 +90,7 @@<br> /* ISH_GP5 */ PAD_CFG_NC(GPP_A23),<br> /* CORE_VID0 */ PAD_CFG_NC(GPP_B0),<br> /* CORE_VID1 */ PAD_CFG_NC(GPP_B1),<br>-/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP),<br>+/* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP),<br> /* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),<br> /* BT_RF_KILL */ PAD_CFG_NC(GPP_B4),<br> /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */<br>@@ -102,7 +102,7 @@<br> /* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11),<br> /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),<br> /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),<br>-/* PCH_BUZZER */ PAD_CFG_GPI(GPP_B14, NONE, DEEP),<br>+/* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP),<br> /* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),<br> /* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),<br> /* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17),<br>@@ -118,16 +118,16 @@<br> /* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3),<br> /* SML0DATA */ PAD_CFG_NC(GPP_C4),<br> /* SML0ALERT# */ PAD_CFG_NC(GPP_C5),<br>-/* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP),<br>+/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP),<br> /* USB_CTL */ PAD_CFG_NC(GPP_C7),<br> /* UART0_RXD */ PAD_CFG_NC(GPP_C8),<br> /* UART0_TXD */ PAD_CFG_NC(GPP_C9),<br> /* NFC_RST* */ PAD_CFG_NC(GPP_C10),<br> /* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP),<br>-/* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP),<br>-/* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP),<br>-/* PCH_MEM_CFG2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),<br>-/* PCH_MEM_CFG3 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP),<br>+/* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),<br>+/* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),<br>+/* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),<br>+/* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),<br> /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),<br> /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),<br> /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),<br>@@ -135,7 +135,7 @@<br> /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),<br> /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),<br> /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP),<br>-/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),<br>+/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),<br> /* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0),<br> /* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1),<br> /* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2),<br>@@ -163,7 +163,7 @@<br> /* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),<br> /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),<br> /* SSD_PEDET */ PAD_CFG_NC(GPP_E2),<br>-/* AUDIO_DB_ID */ PAD_CFG_GPI(GPP_E3, NONE, DEEP),<br>+/* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),<br> /* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4),<br> /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),<br> /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),<br>@@ -234,7 +234,7 @@<br> /* Early pad configuration in romstage. */<br> static const struct pad_config early_gpio_table[] = {<br> /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */<br>-/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),<br>+/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),<br> /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */<br> };<br> <br>diff --git a/src/mainboard/purism/librem13v2/gpio.h b/src/mainboard/purism/librem13v2/gpio.h<br>index e126a42..148e40b 100644<br>--- a/src/mainboard/purism/librem13v2/gpio.h<br>+++ b/src/mainboard/purism/librem13v2/gpio.h<br>@@ -90,9 +90,9 @@<br> /* UART1_TXD */ PAD_CFG_NC(GPP_C13),<br> /* UART1_RTS# */ PAD_CFG_NC(GPP_C14),<br> /* UART1_CTS# */ PAD_CFG_NC(GPP_C15),<br>-/* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP),<br>-/* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP),<br>-/* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP),<br>+/* I2C0_SDA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C16, NONE, DEEP),<br>+/* I2C0_SCL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C17, NONE, DEEP),<br>+/* I2C1_SDA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C18, NONE, DEEP),<br> /* I2C1_SCL */ PAD_CFG_NC(GPP_C19),<br> /* UART2_RXD */ PAD_CFG_NC(GPP_C20),<br> /* UART2_TXD */ PAD_CFG_NC(GPP_C21),<br></pre><p>To view, visit <a href="https://review.coreboot.org/21912">change 21912</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21912"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7dab302f372e56864432100a56462b92d43060ee </div>
<div style="display:none"> Gerrit-Change-Number: 21912 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>