<p>Jonathan Neuschäfer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21894">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP] nb/via/cn700: Switch to early cbmem init<br><br>This patch currently has one very big and non-obvious (from looking at<br>the source) problem: If EARLY_CBMEM_INIT is enabled, I don't see *any*<br>output on the serial console, not even "coreboot-[...] romstage<br>starting..."<br><br>The stylistic problems of this patch are more obvious.<br><br>Change-Id: I9bffa2e11f07c0ed3232fb5a3e165ab81029beee<br>Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>M src/mainboard/winnet/g170/romstage.c<br>M src/northbridge/via/cn700/Kconfig<br>M src/northbridge/via/cn700/Makefile.inc<br>M src/northbridge/via/cn700/northbridge.c<br>M src/northbridge/via/cn700/ram_calc.c<br>5 files changed, 25 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/21894/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/winnet/g170/romstage.c b/src/mainboard/winnet/g170/romstage.c<br>index 0703ba6..e288feb 100644<br>--- a/src/mainboard/winnet/g170/romstage.c<br>+++ b/src/mainboard/winnet/g170/romstage.c<br>@@ -20,6 +20,7 @@<br> #include <device/pci_ids.h><br> #include <arch/io.h><br> #include <device/pnp_def.h><br>+#include <cbmem.h><br> #include <console/console.h><br> #include <northbridge/via/cn700/raminit.h><br> #include <cpu/x86/bist.h><br>@@ -91,4 +92,6 @@<br> enable_mainboard_devices();<br> <br> ddr_ram_setup(&ctrl);<br>+<br>+ cbmem_initialize_empty();<br> }<br>diff --git a/src/northbridge/via/cn700/Kconfig b/src/northbridge/via/cn700/Kconfig<br>index 1619ff1..6e656e7 100644<br>--- a/src/northbridge/via/cn700/Kconfig<br>+++ b/src/northbridge/via/cn700/Kconfig<br>@@ -2,7 +2,6 @@<br> bool<br> select NO_MMCONF_SUPPORT<br> select HAVE_DEBUG_RAM_SETUP<br>- select LATE_CBMEM_INIT<br> <br> # TODO: Values are from the CX700 datasheet, not sure if this matches CN700.<br> # TODO: What should be the per-chipset default value here?<br>diff --git a/src/northbridge/via/cn700/Makefile.inc b/src/northbridge/via/cn700/Makefile.inc<br>index 977460b..ac10da8 100644<br>--- a/src/northbridge/via/cn700/Makefile.inc<br>+++ b/src/northbridge/via/cn700/Makefile.inc<br>@@ -21,5 +21,6 @@<br> ramstage-y += vga.c<br> ramstage-y += ram_calc.c<br> romstage-y += raminit.c<br>+romstage-y += ram_calc.c<br> <br> endif<br>diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c<br>index 1ea4e51..c4cccd8 100644<br>--- a/src/northbridge/via/cn700/northbridge.c<br>+++ b/src/northbridge/via/cn700/northbridge.c<br>@@ -103,8 +103,6 @@<br> <br> tolmk = cn700_get_tolmk(dev);<br> <br>- set_late_cbmem_top((tolmk - CONFIG_VIDEO_MB * 1024) * 1024);<br>-<br> /* Report the memory regions. */<br> idx = 10;<br> /* TODO: Hole needed? */<br>diff --git a/src/northbridge/via/cn700/ram_calc.c b/src/northbridge/via/cn700/ram_calc.c<br>index 3686bf4..371d6cb 100644<br>--- a/src/northbridge/via/cn700/ram_calc.c<br>+++ b/src/northbridge/via/cn700/ram_calc.c<br>@@ -16,6 +16,7 @@<br> * GNU General Public License for more details.<br> */<br> <br>+#include <cbmem.h><br> #include <console/console.h><br> #include <device/device.h><br> #include <device/pci.h><br>@@ -33,11 +34,19 @@<br> unsigned char rambits;<br> int i;<br> device_t mc_dev;<br>- u32 pci_tolm;<br> <br>+ printk(BIOS_DEBUG, "%s entered\n", __func__);<br>+<br>+#ifndef __SIMPLE_DEVICE__<br>+ u32 pci_tolm;<br> pci_tolm = find_pci_tolm(dev->link_list);<br>+#endif<br>+#ifdef __SIMPLE_DEVICE__<br>+ mc_dev = PCI_DEVFN(3, 0);<br>+#else<br> mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,<br> PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);<br>+#endif<br> <br> if (!mc_dev)<br> die("Error: Memory controller device not found!\n");<br>@@ -55,7 +64,11 @@<br> tomk = rambits * 64 * 1024;<br> printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk);<br> /* Compute the Top Of Low Memory (TOLM), in Kb. */<br>+#ifdef __SIMPLE_DEVICE__<br>+ tolmk = ~0;<br>+#else<br> tolmk = pci_tolm >> 10;<br>+#endif<br> if (tolmk >= tomk) {<br> /* The PCI hole does does not overlap the memory. */<br> tolmk = tomk;<br>@@ -63,3 +76,10 @@<br> <br> return tolmk;<br> }<br>+<br>+void *cbmem_top(void)<br>+{<br>+ unsigned long top = cn700_get_tolmk(0) - CONFIG_VIDEO_MB * 1024;<br>+<br>+ return (void *)(top * 1024);<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21894">change 21894</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21894"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9bffa2e11f07c0ed3232fb5a3e165ab81029beee </div>
<div style="display:none"> Gerrit-Change-Number: 21894 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>