<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21888">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/cannonlake_rvp: Enabale Audio DSP<br><br>Enable Audio DSP by default on cannonlake rvp platform.<br><br>TEST=Boot up into OS and check Audio driver debug print.<br><br>Change-Id: I6892c6d349019550c967ef30b84d385f396fc388<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>2 files changed, 6 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/21888/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>index 119af48..13c721b 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>@@ -32,6 +32,9 @@<br>        register "SataPortsEnable[0]" = "1"<br>       register "SataPortsEnable[1]" = "1"<br> <br>+   register "PchHdaDspEnable" = "1"<br>+ register "PchHdaAudioLinkHda" = "1"<br>+<br>    device domain 0 on<br>            device pci 00.0 on  end # Host Bridge<br>                 device pci 02.0 on  end # Integrated Graphics Device<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>index 6e7c535..b1e7c66 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>@@ -32,6 +32,9 @@<br>  register "SataPortsEnable[0]" = "1"<br>       register "SataPortsEnable[1]" = "1"<br> <br>+   register "PchHdaDspEnable" = "1"<br>+ register "PchHdaAudioLinkHda" = "1"<br>+<br>    device domain 0 on<br>            device pci 00.0 on  end # Host Bridge<br>                 device pci 02.0 on  end # Integrated Graphics Device<br></pre><p>To view, visit <a href="https://review.coreboot.org/21888">change 21888</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21888"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6892c6d349019550c967ef30b84d385f396fc388 </div>
<div style="display:none"> Gerrit-Change-Number: 21888 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>