<p>Chris Wang would like Chris Wang to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/21895">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/poppy/variants/nautilus: add nautilus board<br><br>Create Nautilus board which derives from Poppy, a KBL reference board.<br><br>BRANCH=master<br>BUG=b:66458931<br>TEST=Build (as initial setup)<br><br>Change-Id: I6ca5ab821a7ba1746b37dfd3ea1ed367094d4f52<br>Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com><br>---<br>M src/mainboard/google/poppy/Kconfig<br>M src/mainboard/google/poppy/Kconfig.name<br>A src/mainboard/google/poppy/variants/nautilus/Makefile.inc<br>A src/mainboard/google/poppy/variants/nautilus/devicetree.cb<br>A src/mainboard/google/poppy/variants/nautilus/gpio.c<br>A src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl<br>A src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h<br>A src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h<br>8 files changed, 893 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/21895/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig<br>index 7eb4398..0ed65d0 100644<br>--- a/src/mainboard/google/poppy/Kconfig<br>+++ b/src/mainboard/google/poppy/Kconfig<br>@@ -23,6 +23,7 @@<br> config DEVICETREE<br> string<br> default "variants/soraka/devicetree.cb" if BOARD_GOOGLE_SORAKA<br>+ default "variants/nautilus/devicetree.cb" if BOARD_GOOGLE_NAUTILUS<br> default "variants/baseboard/devicetree.cb"<br> <br> config DRIVER_TPM_I2C_BUS<br>@@ -42,6 +43,7 @@<br> depends on CHROMEOS<br> default "POPPY TEST 8294" if BOARD_GOOGLE_POPPY<br> default "SORAKA TEST 1869" if BOARD_GOOGLE_SORAKA<br>+ default "NAUTILUS TEST 3010" if BOARD_GOOGLE_NAUTILUS<br> <br> config INCLUDE_NHLT_BLOBS<br> bool "Include blobs for audio."<br>@@ -58,11 +60,13 @@<br> string<br> default "Google_Poppy" if BOARD_GOOGLE_POPPY<br> default "Google_Soraka" if BOARD_GOOGLE_SORAKA<br>+ default "Google_Nautilus" if BOARD_GOOGLE_NAUTILUS<br> <br> config MAINBOARD_PART_NUMBER<br> string<br> default "Poppy" if BOARD_GOOGLE_POPPY<br> default "Soraka" if BOARD_GOOGLE_SORAKA<br>+ default "Nautilus" if BOARD_GOOGLE_NAUTILUS<br> <br> config MAX_CPUS<br> int<br>@@ -93,6 +97,7 @@<br> string<br> default "poppy" if BOARD_GOOGLE_POPPY<br> default "soraka" if BOARD_GOOGLE_SORAKA<br>+ default "nautilus" if BOARD_GOOGLE_NAUTILUS<br> <br> config VBOOT<br> select EC_GOOGLE_CHROMEEC_SWITCHES<br>diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name<br>index e8c6cdc..181fad4 100644<br>--- a/src/mainboard/google/poppy/Kconfig.name<br>+++ b/src/mainboard/google/poppy/Kconfig.name<br>@@ -5,3 +5,7 @@<br> config BOARD_GOOGLE_SORAKA<br> bool "Soraka"<br> select BOARD_GOOGLE_BASEBOARD_POPPY<br>+<br>+config BOARD_GOOGLE_NAUTILUS<br>+ bool "Nautilus"<br>+ select BOARD_GOOGLE_BASEBOARD_POPPY<br>diff --git a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc<br>new file mode 100644<br>index 0000000..9b14da6<br>--- /dev/null<br>+++ b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc<br>@@ -0,0 +1,14 @@<br>+<br>+SPD_SOURCES = empty # 0b0000<br>+SPD_SOURCES += micron_dimm_MT52L256M64D2PP-107 # 0b0001<br>+SPD_SOURCES += hynix_dimm_H9CCNNNBKTALBR-NUD # 0b0010<br>+SPD_SOURCES += micron_dimm_MT52L512M64D4PQ-107 # 0b0011<br>+SPD_SOURCES += hynix_dimm_H9CCNNNCPTALBR-NUD # 0b0100<br>+SPD_SOURCES += micron_dimm_MT52L1G64D8QC-107 # 0b0101<br>+SPD_SOURCES += hynix_dimm_H9CCNNNFAGMLLR-NUD # 0b0110<br>+SPD_SOURCES += samsung_dimm_K3QF3F30BM-AGCF # 0b0111<br>+SPD_SOURCES += samsung_dimm_K3QF4F40BM-AGCF # 0b1000<br>+SPD_SOURCES += samsung_dimm_K3QFAFA0CM-AGCF # 0b1001<br>+<br>+bootblock-y += gpio.c<br>+ramstage-y += gpio.c<br>diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb<br>new file mode 100644<br>index 0000000..b39092b<br>--- /dev/null<br>+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb<br>@@ -0,0 +1,385 @@<br>+chip soc/intel/skylake<br>+<br>+ # Deep Sx states<br>+ register "deep_s3_enable_ac" = "0"<br>+ register "deep_s3_enable_dc" = "1"<br>+ register "deep_s5_enable_ac" = "1"<br>+ register "deep_s5_enable_dc" = "1"<br>+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"<br>+<br>+ # GPE configuration<br>+ # Note that GPE events called out in ASL code rely on this<br>+ # route. i.e. If this route changes then the affected GPE<br>+ # offset bits also need to be changed.<br>+ register "gpe0_dw0" = "GPP_B"<br>+ register "gpe0_dw1" = "GPP_D"<br>+ register "gpe0_dw2" = "GPP_E"<br>+<br>+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f<br>+ register "gen1_dec" = "0x00fc0801"<br>+ register "gen2_dec" = "0x000c0201"<br>+ # EC memory map range is 0x900-0x9ff<br>+ register "gen3_dec" = "0x00fc0901"<br>+<br>+ # Enable DPTF<br>+ register "dptf_enable" = "1"<br>+<br>+ # Enable S0ix<br>+ register "s0ix_enable" = "1"<br>+<br>+ # FSP Configuration<br>+ register "ProbelessTrace" = "0"<br>+ register "EnableLan" = "0"<br>+ register "EnableSata" = "0"<br>+ register "SataSalpSupport" = "0"<br>+ register "SataMode" = "0"<br>+ register "SataPortsEnable[0]" = "0"<br>+ register "EnableAzalia" = "1"<br>+ register "DspEnable" = "1"<br>+ register "IoBufferOwnership" = "3"<br>+ register "EnableTraceHub" = "0"<br>+ register "XdciEnable" = "0"<br>+ register "SsicPortEnable" = "0"<br>+ register "SmbusEnable" = "1"<br>+ register "Cio2Enable" = "1"<br>+ register "SaImguEnable" = "1"<br>+ register "ScsEmmcEnabled" = "1"<br>+ register "ScsEmmcHs400Enabled" = "1"<br>+ register "ScsSdCardEnabled" = "2"<br>+ register "IshEnable" = "0"<br>+ register "PttSwitch" = "0"<br>+ register "InternalGfx" = "1"<br>+ register "SkipExtGfxScan" = "1"<br>+ register "Device4Enable" = "1"<br>+ register "HeciEnabled" = "0"<br>+ register "FspSkipMpInit" = "1"<br>+ register "SaGv" = "3"<br>+ register "SerialIrqConfigSirqEnable" = "1"<br>+ register "PmConfigSlpS3MinAssert" = "2" # 50ms<br>+ register "PmConfigSlpS4MinAssert" = "1" # 1s<br>+ register "PmConfigSlpSusMinAssert" = "1" # 500ms<br>+ register "PmConfigSlpAMinAssert" = "3" # 2s<br>+ register "PmTimerDisabled" = "1"<br>+<br>+ register "pirqa_routing" = "PCH_IRQ11"<br>+ register "pirqb_routing" = "PCH_IRQ10"<br>+ register "pirqc_routing" = "PCH_IRQ11"<br>+ register "pirqd_routing" = "PCH_IRQ11"<br>+ register "pirqe_routing" = "PCH_IRQ11"<br>+ register "pirqf_routing" = "PCH_IRQ11"<br>+ register "pirqg_routing" = "PCH_IRQ11"<br>+ register "pirqh_routing" = "PCH_IRQ11"<br>+<br>+ # VR Settings Configuration for 4 Domains<br>+ #+----------------+-------+-------+-------+-------+<br>+ #| Domain/Setting | SA | IA | GTUS | GTS |<br>+ #+----------------+-------+-------+-------+-------+<br>+ #| Psi1Threshold | 20A | 20A | 20A | 20A |<br>+ #| Psi2Threshold | 2A | 2A | 2A | 2A |<br>+ #| Psi3Threshold | 1A | 1A | 1A | 1A |<br>+ #| Psi3Enable | 1 | 1 | 1 | 1 |<br>+ #| Psi4Enable | 1 | 1 | 1 | 1 |<br>+ #| ImonSlope | 0 | 0 | 0 | 0 |<br>+ #| ImonOffset | 0 | 0 | 0 | 0 |<br>+ #| IccMax | 5A | 24A | 24A | 24A |<br>+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |<br>+ #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 |<br>+ #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 |<br>+ #+----------------+-------+-------+-------+-------+<br>+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{<br>+ .vr_config_enable = 1,<br>+ .psi1threshold = VR_CFG_AMP(20),<br>+ .psi2threshold = VR_CFG_AMP(2),<br>+ .psi3threshold = VR_CFG_AMP(1),<br>+ .psi3enable = 1,<br>+ .psi4enable = 1,<br>+ .imon_slope = 0x0,<br>+ .imon_offset = 0x0,<br>+ .icc_max = VR_CFG_AMP(5),<br>+ .voltage_limit = 1520,<br>+ .ac_loadline = 1500,<br>+ .dc_loadline = 1430,<br>+ }"<br>+<br>+ register "domain_vr_config[VR_IA_CORE]" = "{<br>+ .vr_config_enable = 1,<br>+ .psi1threshold = VR_CFG_AMP(20),<br>+ .psi2threshold = VR_CFG_AMP(2),<br>+ .psi3threshold = VR_CFG_AMP(1),<br>+ .psi3enable = 1,<br>+ .psi4enable = 1,<br>+ .imon_slope = 0x0,<br>+ .imon_offset = 0x0,<br>+ .icc_max = VR_CFG_AMP(24),<br>+ .voltage_limit = 1520,<br>+ .ac_loadline = 570,<br>+ .dc_loadline = 483,<br>+ }"<br>+<br>+ register "domain_vr_config[VR_GT_UNSLICED]" = "{<br>+ .vr_config_enable = 1,<br>+ .psi1threshold = VR_CFG_AMP(20),<br>+ .psi2threshold = VR_CFG_AMP(2),<br>+ .psi3threshold = VR_CFG_AMP(1),<br>+ .psi3enable = 1,<br>+ .psi4enable = 1,<br>+ .imon_slope = 0x0,<br>+ .imon_offset = 0x0,<br>+ .icc_max = VR_CFG_AMP(24),<br>+ .voltage_limit = 1520,<br>+ .ac_loadline = 550,<br>+ .dc_loadline = 420,<br>+ }"<br>+<br>+ register "domain_vr_config[VR_GT_SLICED]" = "{<br>+ .vr_config_enable = 1,<br>+ .psi1threshold = VR_CFG_AMP(20),<br>+ .psi2threshold = VR_CFG_AMP(2),<br>+ .psi3threshold = VR_CFG_AMP(1),<br>+ .psi3enable = 1,<br>+ .psi4enable = 1,<br>+ .imon_slope = 0x0,<br>+ .imon_offset = 0x0,<br>+ .icc_max = VR_CFG_AMP(24),<br>+ .voltage_limit = 1520,<br>+ .ac_loadline = 550,<br>+ .dc_loadline = 420,<br>+ }"<br>+<br>+ # Enable Root port 1.<br>+ register "PcieRpEnable[0]" = "1"<br>+ # Enable CLKREQ#<br>+ register "PcieRpClkReqSupport[0]" = "1"<br>+ # RP 1 uses SRCCLKREQ1#<br>+ register "PcieRpClkReqNumber[0]" = "1"<br>+<br>+ register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1<br>+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port<br>+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth<br>+ register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2<br>+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port<br>+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port<br>+<br>+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1<br>+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2<br>+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port<br>+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty<br>+<br>+ # Touchscreen<br>+ register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"<br>+ register "i2c[0]" = "{<br>+ .speed = I2C_SPEED_FAST,<br>+ .speed_config[0] = {<br>+ .speed = I2C_SPEED_FAST,<br>+ .scl_lcnt = 180,<br>+ .scl_hcnt = 85,<br>+ .sda_hold = 36,<br>+ },<br>+ }"<br>+<br>+ # H1<br>+ register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"<br>+ # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR<br>+ # for TPM communication before memory is up.<br>+ register "i2c[1]" = "{<br>+ .early_init = 1,<br>+ .speed = I2C_SPEED_FAST,<br>+ .speed_config[0] = {<br>+ .speed = I2C_SPEED_FAST,<br>+ .scl_lcnt = 190,<br>+ .scl_hcnt = 90,<br>+ .sda_hold = 36,<br>+ },<br>+ }"<br>+<br>+ # Camera<br>+ register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"<br>+ register "i2c[2]" = "{<br>+ .speed = I2C_SPEED_FAST,<br>+ .speed_config[0] = {<br>+ .speed = I2C_SPEED_FAST,<br>+ .scl_lcnt = 192,<br>+ .scl_hcnt = 90,<br>+ .sda_hold = 36,<br>+ },<br>+ }"<br>+<br>+ # Pen<br>+ register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"<br>+<br>+ # Camera<br>+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"<br>+ register "i2c[4]" = "{<br>+ .speed = I2C_SPEED_FAST,<br>+ .speed_config[0] = {<br>+ .speed = I2C_SPEED_FAST,<br>+ .scl_lcnt = 190,<br>+ .scl_hcnt = 90,<br>+ .sda_hold = 36,<br>+ },<br>+ }"<br>+<br>+ # Audio<br>+ register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"<br>+ register "i2c[5]" = "{<br>+ .speed = I2C_SPEED_FAST,<br>+ .speed_config[0] = {<br>+ .speed = I2C_SPEED_FAST,<br>+ .scl_lcnt = 180,<br>+ .scl_hcnt = 80,<br>+ .sda_hold = 36,<br>+ },<br>+ }"<br>+<br>+ # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM<br>+ # communication before memory is up.<br>+ register "gspi[0]" = "{<br>+ .speed_mhz = 1,<br>+ .early_init = 1,<br>+ }"<br>+<br>+ # Must leave UART0 enabled or SD/eMMC will not work as PCI<br>+ register "SerialIoDevMode" = "{<br>+ [PchSerialIoIndexI2C0] = PchSerialIoPci,<br>+ [PchSerialIoIndexI2C1] = PchSerialIoPci,<br>+ [PchSerialIoIndexI2C2] = PchSerialIoPci,<br>+ [PchSerialIoIndexI2C3] = PchSerialIoPci,<br>+ [PchSerialIoIndexI2C4] = PchSerialIoPci,<br>+ [PchSerialIoIndexI2C5] = PchSerialIoPci,<br>+ [PchSerialIoIndexSpi0] = PchSerialIoPci,<br>+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,<br>+ [PchSerialIoIndexUart0] = PchSerialIoPci,<br>+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,<br>+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,<br>+ }"<br>+<br>+ register "speed_shift_enable" = "1"<br>+ # PL2 override 15W for KBL-Y<br>+ register "tdp_pl2_override" = "15"<br>+ register "tcc_offset" = "10" # TCC of 90C<br>+<br>+ # Use default SD card detect GPIO configuration<br>+ register "sdcard_cd_gpio_default" = "GPP_E15"<br>+<br>+ # Lock Down<br>+ register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"<br>+<br>+ device cpu_cluster 0 on<br>+ device lapic 0 on end<br>+ end<br>+ device domain 0 on<br>+ device pci 00.0 on end # Host Bridge<br>+ device pci 02.0 on end # Integrated Graphics Device<br>+ device pci 14.0 on end # USB xHCI<br>+ device pci 14.1 off end # USB xDCI (OTG)<br>+ device pci 14.2 on end # Thermal Subsystem<br>+ device pci 15.0 on<br>+ chip drivers/i2c/hid<br>+ register "generic.hid" = ""WCOMCOHO""<br>+ register "generic.desc" = ""WCOM Touchscreen""<br>+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"<br>+ register "generic.probed" = "1"<br>+ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)"<br>+ register "generic.reset_delay_ms" = "110"<br>+ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"<br>+ register "generic.enable_delay_ms" = "1"<br>+ register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)"<br>+ register "generic.has_power_resource" = "1"<br>+ register "generic.disable_gpio_export_in_crs" = "1"<br>+ register "hid_desc_reg_offset" = "0x1"<br>+ device i2c 0xA on end<br>+ end<br>+ end # I2C #0<br>+ device pci 15.1 on<br>+ chip drivers/i2c/tpm<br>+ register "hid" = ""GOOG0005""<br>+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"<br>+ device i2c 50 on end<br>+ end<br>+ end # I2C #1<br>+ device pci 15.2 on end # I2C #2<br>+ device pci 15.3 on<br>+ chip drivers/i2c/hid<br>+ register "generic.hid" = ""WCOM50C1""<br>+ register "generic.desc" = ""WCOM Digitizer""<br>+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)"<br>+ register "hid_desc_reg_offset" = "0x1"<br>+ device i2c 0x9 on end<br>+ end<br>+ end # I2C #3<br>+ device pci 16.0 on end # Management Engine Interface 1<br>+ device pci 16.1 off end # Management Engine Interface 2<br>+ device pci 16.2 off end # Management Engine IDE-R<br>+ device pci 16.3 off end # Management Engine KT Redirection<br>+ device pci 16.4 off end # Management Engine Interface 3<br>+ device pci 17.0 off end # SATA<br>+ device pci 19.0 on end # UART #2<br>+ device pci 19.1 on<br>+ chip drivers/i2c/max98927<br>+ register "interleave_mode" = "1"<br>+ register "uid" = "0"<br>+ register "desc" = ""SSM4567 Right Speaker Amp""<br>+ register "name" = ""MAXR""<br>+ device i2c 39 on end<br>+ end<br>+ chip drivers/i2c/max98927<br>+ register "interleave_mode" = "1"<br>+ register "uid" = "1"<br>+ register "desc" = ""SSM4567 Left Speaker Amp""<br>+ register "name" = ""MAXL""<br>+ device i2c 3A on end<br>+ end<br>+ chip drivers/i2c/generic<br>+ register "hid" = ""10EC5663""<br>+ register "name" = ""RT53""<br>+ register "desc" = ""Realtek RT5663""<br>+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"<br>+ register "probed" = "1"<br>+ device i2c 13 on end<br>+ end<br>+ end # I2C #5<br>+ device pci 19.2 on end # I2C #4<br>+ device pci 1c.0 on<br>+ chip drivers/intel/wifi<br>+ register "wake" = "GPE0_PCI_EXP"<br>+ device pci 00.0 on end<br>+ end<br>+ end # PCI Express Port 1<br>+ device pci 1c.1 off end # PCI Express Port 2<br>+ device pci 1c.2 off end # PCI Express Port 3<br>+ device pci 1c.3 off end # PCI Express Port 4<br>+ device pci 1c.4 off end # PCI Express Port 5<br>+ device pci 1c.5 off end # PCI Express Port 6<br>+ device pci 1c.6 off end # PCI Express Port 7<br>+ device pci 1c.7 off end # PCI Express Port 8<br>+ device pci 1d.0 off end # PCI Express Port 9<br>+ device pci 1d.1 off end # PCI Express Port 10<br>+ device pci 1d.2 off end # PCI Express Port 11<br>+ device pci 1d.3 off end # PCI Express Port 12<br>+ device pci 1e.0 on end # UART #0<br>+ device pci 1e.1 off end # UART #1<br>+ device pci 1e.2 on<br>+ chip drivers/spi/acpi<br>+ register "hid" = "ACPI_DT_NAMESPACE_HID"<br>+ register "compat_string" = ""google,cr50""<br>+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"<br>+ device spi 0 on end<br>+ end<br>+ end # GSPI #0<br>+ device pci 1e.3 off end # GSPI #1<br>+ device pci 1e.4 on end # eMMC<br>+ device pci 1e.5 off end # SDIO<br>+ device pci 1e.6 on end # SDCard<br>+ device pci 1f.0 on<br>+ chip ec/google/chromeec<br>+ device pnp 0c09.0 on end<br>+ end<br>+ end # LPC Interface<br>+ device pci 1f.1 on end # P2SB<br>+ device pci 1f.2 on end # Power Management Controller<br>+ device pci 1f.3 on end # Intel HDA<br>+ device pci 1f.4 on end # SMBus<br>+ device pci 1f.5 on end # PCH SPI<br>+ device pci 1f.6 off end # GbE<br>+ end<br>+end<br>diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c<br>new file mode 100644<br>index 0000000..6f7a3e7<br>--- /dev/null<br>+++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c<br>@@ -0,0 +1,427 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <baseboard/gpio.h><br>+#include <baseboard/variants.h><br>+#include <commonlib/helpers.h><br>+<br>+/* Pad configuration in ramstage */<br>+/* Leave eSPI pins untouched from default settings */<br>+static const struct pad_config gpio_table[] = {<br>+ /* A0 : RCIN# ==> NC(TP41) */<br>+ PAD_CFG_NC(GPP_A0),<br>+ /* A1 : ESPI_IO0 */<br>+ /* A2 : ESPI_IO1 */<br>+ /* A3 : ESPI_IO2 */<br>+ /* A4 : ESPI_IO3 */<br>+ /* A5 : ESPI_CS# */<br>+ /* A6 : SERIRQ ==> NC(TP44) */<br>+ PAD_CFG_NC(GPP_A6),<br>+ /* A7 : PIRQA# ==> NC(TP29) */<br>+ PAD_CFG_NC(GPP_A7),<br>+ /* A8 : CLKRUN# ==> NC(TP45) */<br>+ PAD_CFG_NC(GPP_A8),<br>+ /* A9 : ESPI_CLK */<br>+ /* A10 : CLKOUT_LPC1 ==> NC */<br>+ PAD_CFG_NC(GPP_A10),<br>+ /* A11 : PME# ==> NC(TP67) */<br>+ PAD_CFG_NC(GPP_A11),<br>+ /* A12 : BM_BUSY# ==> NC */<br>+ PAD_CFG_NC(GPP_A12),<br>+ /* A13 : SUSWARN# ==> SUSWARN_L */<br>+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),<br>+ /* A14 : ESPI_RESET# */<br>+ /* A15 : SUSACK# ==> SUSACK_L */<br>+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),<br>+ /* A16 : SD_1P8_SEL ==> SD_PWR_1800_SEL */<br>+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),<br>+ /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */<br>+ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),<br>+ /* A18 : ISH_GP0 ==> NC */<br>+ PAD_CFG_NC(GPP_A18),<br>+ /* A19 : ISH_GP1 ==> NC */<br>+ PAD_CFG_NC(GPP_A19),<br>+ /* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */<br>+ PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST),<br>+ /* A21 : ISH_GP3 ==> NC */<br>+ PAD_CFG_NC(GPP_A21),<br>+ /* A22 : ISH_GP4 ==> NC */<br>+ PAD_CFG_NC(GPP_A22),<br>+ /* A23 : ISH_GP5 ==> NC */<br>+ PAD_CFG_NC(GPP_A23),<br>+<br>+ /* B0 : CORE_VID0 ==> NC(TP42) */<br>+ PAD_CFG_NC(GPP_B0),<br>+ /* B1 : CORE_VID1 ==> NC(TP43) */<br>+ PAD_CFG_NC(GPP_B1),<br>+ /* B2 : VRALERT# ==> NC */<br>+ PAD_CFG_NC(GPP_B2),<br>+ /* B3 : CPU_GP2 ==> NC */<br>+ PAD_CFG_NC(GPP_B3),<br>+ /* B4 : CPU_GP3 ==> NC */<br>+ PAD_CFG_NC(GPP_B4),<br>+ /* B5 : SRCCLKREQ0# ==> NC */<br>+ PAD_CFG_NC(GPP_B5),<br>+ /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */<br>+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),<br>+ /* B7 : SRCCLKREQ2# ==> NC */<br>+ PAD_CFG_NC(GPP_B7),<br>+ /* B9 : SRCCLKREQ4# ==> NC */<br>+ PAD_CFG_NC(GPP_B9),<br>+ /* B10 : SRCCLKREQ5# ==> NC */<br>+ PAD_CFG_NC(GPP_B10),<br>+ /* B11 : EXT_PWR_GATE# ==> NC */<br>+ PAD_CFG_NC(GPP_B11),<br>+ /* B12 : SLP_S0# ==> SLP_S0_L_G */<br>+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),<br>+ /* B13 : PLTRST# ==> PLT_RST_L */<br>+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),<br>+ /* B14 : SPKR ==> NC */<br>+ PAD_CFG_NC(GPP_B14),<br>+#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)<br>+ /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */<br>+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),<br>+ /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */<br>+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),<br>+ /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */<br>+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),<br>+ /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */<br>+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),<br>+#else<br>+ /* B15 : GSPI0_CS# ==> NC */<br>+ PAD_CFG_NC(GPP_B15),<br>+ /* B16 : GSPI0_CLK ==> NC */<br>+ PAD_CFG_NC(GPP_B16),<br>+ /* B17 : GSPI0_MISO ==> NC */<br>+ PAD_CFG_NC(GPP_B17),<br>+ /* B18 : GSPI0_MOSI ==> NC */<br>+ PAD_CFG_NC(GPP_B18),<br>+#endif<br>+ /* B19 : GSPI1_CS# ==> NC */<br>+ PAD_CFG_NC(GPP_B19),<br>+ /* B20 : GSPI1_CLK ==> NC */<br>+ PAD_CFG_NC(GPP_B20),<br>+ /* B21 : GSPI1_MISO ==> NC */<br>+ PAD_CFG_NC(GPP_B21),<br>+ /* B22 : GSPI1_MOSI ==> NC */<br>+ PAD_CFG_NC(GPP_B22),<br>+ /* B23 : SM1ALERT# ==> NC */<br>+ PAD_CFG_NC(GPP_B23),<br>+<br>+ /* C0 : SMBCLK ==> NC */<br>+ PAD_CFG_NC(GPP_C0),<br>+ /* C1 : SMBDATA ==> NC */<br>+ PAD_CFG_NC(GPP_C1),<br>+ /* C2 : SMBALERT# ==> NC */<br>+ PAD_CFG_NC(GPP_C2),<br>+ /* C3 : SML0CLK ==> NC */<br>+ PAD_CFG_NC(GPP_C3),<br>+ /* C4 : SML0DATA ==> NC */<br>+ PAD_CFG_NC(GPP_C4),<br>+ /* C5 : SML0ALERT# ==> NC */<br>+ PAD_CFG_NC(GPP_C5),<br>+ /* C6 : SM1CLK ==> EC_IN_RW_OD */<br>+ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),<br>+ /* C7 : SM1DATA ==> NC */<br>+ PAD_CFG_NC(GPP_C7),<br>+ /* C8 : UART0_RXD ==> FP_INT */<br>+ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST),<br>+ /* C9 : UART0_TXD ==> FP_RST_ODL */<br>+ PAD_CFG_GPO(GPP_C9, 0, DEEP),<br>+ /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */<br>+ PAD_CFG_GPO(GPP_C10, 1, DEEP),<br>+ /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */<br>+ PAD_CFG_GPO(GPP_C11, 1, DEEP),<br>+ /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */<br>+ PAD_CFG_GPI(GPP_C12, NONE, DEEP),<br>+ /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */<br>+ PAD_CFG_GPI(GPP_C13, NONE, DEEP),<br>+ /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */<br>+ PAD_CFG_GPI(GPP_C14, NONE, DEEP),<br>+ /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */<br>+ PAD_CFG_GPI(GPP_C15, NONE, DEEP),<br>+ /* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */<br>+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),<br>+ /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */<br>+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),<br>+#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)<br>+ /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */<br>+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),<br>+ /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */<br>+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),<br>+#else<br>+ /* C18 : I2C1_SDA ==> NC */<br>+ PAD_CFG_NC(GPP_C18),<br>+ /* C19 : I2C1_SCL ==> NC */<br>+ PAD_CFG_NC(GPP_C19),<br>+#endif<br>+ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */<br>+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),<br>+ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */<br>+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),<br>+ /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */<br>+ PAD_CFG_GPO(GPP_C22, 0, DEEP),<br>+ /* C23 : UART2_CTS# ==> PCH_WP */<br>+ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),<br>+<br>+ /* D0 : SPI1_CS# ==> NC */<br>+ PAD_CFG_NC(GPP_D0),<br>+ /* D1 : SPI1_CLK ==> NC */<br>+ PAD_CFG_NC(GPP_D1),<br>+ /* D2 : SPI1_MISO ==> NC */<br>+ PAD_CFG_NC(GPP_D2),<br>+ /* D3 : SPI1_MOSI ==> NC */<br>+ PAD_CFG_NC(GPP_D3),<br>+ /* D4 : FASHTRIG ==> NC */<br>+ PAD_CFG_NC(GPP_D4),<br>+ /* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */<br>+ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),<br>+ /* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */<br>+ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1),<br>+ /* D7 : ISH_I2C1_SDA ==> NC */<br>+ PAD_CFG_NC(GPP_D7),<br>+ /* D8 : ISH_I2C1_SCL ==> NC */<br>+ PAD_CFG_NC(GPP_D8),<br>+ /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */<br>+ PAD_CFG_GPI(GPP_D9, NONE, PLTRST),<br>+ /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */<br>+ PAD_CFG_GPO(GPP_D10, 1, DEEP),<br>+ /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */<br>+ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST),<br>+ /* D12 : ISH_SPI_MOSI ==> NC */<br>+ PAD_CFG_NC(GPP_D12),<br>+ /* D13 : ISH_UART0_RXD ==> NC */<br>+ PAD_CFG_NC(GPP_D13),<br>+ /* D14 : ISH_UART0_TXD ==> NC */<br>+ PAD_CFG_NC(GPP_D14),<br>+ /* D15 : ISH_UART0_RTS# ==> NC */<br>+ PAD_CFG_NC(GPP_D15),<br>+ /* D16 : ISH_UART0_CTS# ==> NC */<br>+ PAD_CFG_NC(GPP_D16),<br>+ /* D17 : DMIC_CLK1 */<br>+ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),<br>+ /* D18 : DMIC_DATA1 */<br>+ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),<br>+ /* D19 : DMIC_CLK0 */<br>+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),<br>+ /* D20 : DMIC_DATA0 */<br>+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),<br>+ /* D21 : SPI1_IO2 ==> NC */<br>+ PAD_CFG_NC(GPP_D21),<br>+ /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */<br>+ PAD_CFG_GPO(GPP_D22, 1, DEEP),<br>+ /* D23 : I2S_MCLK ==> I2S_MCLK_R */<br>+ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),<br>+<br>+ /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */<br>+ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),<br>+ /* E1 : SATAXPCIE1 ==> NC */<br>+ PAD_CFG_NC(GPP_E1),<br>+ /* E2 : SATAXPCIE2 ==> NC */<br>+ PAD_CFG_NC(GPP_E2),<br>+ /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */<br>+ PAD_CFG_GPO(GPP_E3, 0, DEEP),<br>+ /* E4 : SATA_DEVSLP0 ==> NC */<br>+ PAD_CFG_NC(GPP_E4),<br>+ /* E5 : SATA_DEVSLP1 ==> NC */<br>+ PAD_CFG_NC(GPP_E5),<br>+ /* E6 : SATA_DEVSLP2 ==> NC */<br>+ PAD_CFG_NC(GPP_E6),<br>+ /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */<br>+ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),<br>+ /* E8 : SATALED# ==> NC */<br>+ PAD_CFG_NC(GPP_E8),<br>+ /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */<br>+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),<br>+ /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */<br>+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),<br>+ /* E11 : USB2_OC2# ==> TOUCHSCREEN_STOP_L */<br>+ PAD_CFG_GPO(GPP_E11, 0, DEEP),<br>+ /* E12 : USB2_OC3# ==> USB2_OC3_L */<br>+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),<br>+ /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */<br>+ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),<br>+ /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */<br>+ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),<br>+ /* E15 : DDPD_HPD2 ==> SD_CD# */<br>+ PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),<br>+ /* E16 : DDPE_HPD3 ==> NC(TP244) */<br>+ PAD_CFG_NC(GPP_E16),<br>+ /* E17 : EDP_HPD */<br>+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),<br>+ /* E18 : DDPB_CTRLCLK ==> NC */<br>+ PAD_CFG_NC(GPP_E18),<br>+ /* E19 : DDPB_CTRLDATA ==> NC */<br>+ PAD_CFG_NC(GPP_E19),<br>+ /* E20 : DDPC_CTRLCLK ==> NC */<br>+ PAD_CFG_NC(GPP_E20),<br>+ /* E21 : DDPC_CTRLDATA ==> NC */<br>+ PAD_CFG_NC(GPP_E21),<br>+ /* E22 : DDPD_CTRLCLK ==> NC */<br>+ PAD_CFG_NC(GPP_E22),<br>+ /* E23 : DDPD_CTRLDATA ==> NC */<br>+ PAD_CFG_NC(GPP_E23),<br>+<br>+ /* The next 4 pads are for bit banging the amplifiers, default to I2S */<br>+ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */<br>+ PAD_CFG_GPI(GPP_F0, NONE, DEEP),<br>+ /* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */<br>+ PAD_CFG_GPI(GPP_F1, NONE, DEEP),<br>+ /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */<br>+ PAD_CFG_GPI(GPP_F2, NONE, DEEP),<br>+ /* F3 : I2S2_RXD */<br>+ PAD_CFG_GPI(GPP_F3, NONE, DEEP),<br>+ /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */<br>+ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),<br>+ /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */<br>+ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),<br>+ /* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */<br>+ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),<br>+ /* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */<br>+ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),<br>+ /* F8 : I2C4_SDA ==> PCH_I2C4_UFCAM_1V8_SDA */<br>+ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),<br>+ /* F9 : I2C4_SCL ==> PCH_I2C4_UFCAM_1V8_SCL */<br>+ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),<br>+ /* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */<br>+ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1),<br>+ /* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */<br>+ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1),<br>+ /* F12 : EMMC_CMD */<br>+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),<br>+ /* F13 : EMMC_DATA0 */<br>+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),<br>+ /* F14 : EMMC_DATA1 */<br>+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),<br>+ /* F15 : EMMC_DATA2 */<br>+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),<br>+ /* F16 : EMMC_DATA3 */<br>+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),<br>+ /* F17 : EMMC_DATA4 */<br>+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),<br>+ /* F18 : EMMC_DATA5 */<br>+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),<br>+ /* F19 : EMMC_DATA6 */<br>+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),<br>+ /* F20 : EMMC_DATA7 */<br>+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),<br>+ /* F21 : EMMC_RCLK */<br>+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),<br>+ /* F22 : EMMC_CLK */<br>+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),<br>+ /* F23 : RSVD ==> NC */<br>+ PAD_CFG_NC(GPP_F23),<br>+<br>+ /* G0 : SD_CMD */<br>+ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),<br>+ /* G1 : SD_DATA0 */<br>+ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),<br>+ /* G2 : SD_DATA1 */<br>+ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),<br>+ /* G3 : SD_DATA2 */<br>+ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),<br>+ /* G4 : SD_DATA3 */<br>+ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),<br>+ /* G5 : SD_CD# */<br>+ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),<br>+ /* G6 : SD_CLK */<br>+ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),<br>+ /* G7 : SD_WP */<br>+ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),<br>+<br>+ /* GPD0: BATLOW# ==> PCH_BATLOW_L */<br>+ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),<br>+ /* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */<br>+ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),<br>+ /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */<br>+ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),<br>+ /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */<br>+ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),<br>+ /* GPD4: SLP_S3# ==> SLP_S3_L */<br>+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),<br>+ /* GPD5: SLP_S4# ==> SLP_S4_L */<br>+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),<br>+ /* GPD6: SLP_A# ==> NC(TP26) */<br>+ PAD_CFG_NC(GPD6),<br>+ /* GPD7: RSVD ==> NC */<br>+ PAD_CFG_NC(GPD7),<br>+ /* GPD8: SUSCLK ==> PCH_SUSCLK */<br>+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),<br>+ /* GPD9: SLP_WLAN# ==> NC(TP25) */<br>+ PAD_CFG_NC(GPD9),<br>+ /* GPD10: SLP_S5# ==> NC(TP15) */<br>+ PAD_CFG_NC(GPD10),<br>+ /* GPD11: LANPHYC ==> NC */<br>+ PAD_CFG_NC(GPD11),<br>+};<br>+<br>+/* Early pad configuration in bootblock */<br>+static const struct pad_config early_gpio_table[] = {<br>+ /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */<br>+ PAD_CFG_GPO(GPP_B8, 0, DEEP),<br>+<br>+#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)<br>+ /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */<br>+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),<br>+ /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */<br>+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),<br>+ /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */<br>+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),<br>+ /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */<br>+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),<br>+#endif<br>+<br>+#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)<br>+ /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */<br>+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),<br>+ /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */<br>+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),<br>+#endif<br>+<br>+ /* Ensure UART pins are in native mode for H1. */<br>+ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */<br>+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),<br>+ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */<br>+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),<br>+<br>+ /* C23 : UART2_CTS# ==> PCH_WP */<br>+ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),<br>+<br>+ /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */<br>+ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),<br>+};<br>+<br>+const struct pad_config *variant_gpio_table(size_t *num)<br>+{<br>+ *num = ARRAY_SIZE(gpio_table);<br>+ return gpio_table;<br>+}<br>+<br>+const struct pad_config *variant_early_gpio_table(size_t *num)<br>+{<br>+ *num = ARRAY_SIZE(early_gpio_table);<br>+ return early_gpio_table;<br>+}<br>+<br>+static const struct cros_gpio cros_gpios[] = {<br>+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),<br>+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),<br>+};<br>+<br>+const struct cros_gpio *variant_cros_gpios(size_t *num)<br>+{<br>+ *num = ARRAY_SIZE(cros_gpios);<br>+ return cros_gpios;<br>+}<br>diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl<br>new file mode 100644<br>index 0000000..a9ec742<br>--- /dev/null<br>+++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl<br>@@ -0,0 +1,16 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <baseboard/acpi/dptf.asl><br>diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h b/src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h<br>new file mode 100644<br>index 0000000..047abb6<br>--- /dev/null<br>+++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h<br>@@ -0,0 +1,21 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __MAINBOARD_EC_H__<br>+#define __MAINBOARD_EC_H__<br>+<br>+#include <baseboard/ec.h><br>+<br>+#endif /* __MAINBOARD_EC_H__ */<br>diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h<br>new file mode 100644<br>index 0000000..4f79495<br>--- /dev/null<br>+++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h<br>@@ -0,0 +1,21 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __MAINBOARD_GPIO_H__<br>+#define __MAINBOARD_GPIO_H__<br>+<br>+#include <baseboard/gpio.h><br>+<br>+#endif /* __MAINBOARD_GPIO_H__ */<br></pre><p>To view, visit <a href="https://review.coreboot.org/21895">change 21895</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21895"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6ca5ab821a7ba1746b37dfd3ea1ed367094d4f52 </div>
<div style="display:none"> Gerrit-Change-Number: 21895 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Chris Wang <chriswang@ami.com.tw> </div>
<div style="display:none"> Gerrit-Reviewer: Chris Wang <chriswang@ami.corp-partner.google.com> </div>