<p>Damien Zammit has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21871">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">biostar/a68n_5200: Clone of amd/olivehill<br><br>Altered Kconfig board names to make it pass lint<br><br>Change-Id: I9ccfe014a0e3a70148463fc9f8de02b500fac69e<br>Signed-off-by: Damien Zammit <damien@zamaudio.com><br>---<br>A src/mainboard/biostar/a68n_5200/BiosCallOuts.c<br>A src/mainboard/biostar/a68n_5200/Kconfig<br>A src/mainboard/biostar/a68n_5200/Kconfig.name<br>A src/mainboard/biostar/a68n_5200/Makefile.inc<br>A src/mainboard/biostar/a68n_5200/OemCustomize.c<br>A src/mainboard/biostar/a68n_5200/OptionsIds.h<br>A src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl<br>A src/mainboard/biostar/a68n_5200/acpi/gpe.asl<br>A src/mainboard/biostar/a68n_5200/acpi/ide.asl<br>A src/mainboard/biostar/a68n_5200/acpi/mainboard.asl<br>A src/mainboard/biostar/a68n_5200/acpi/routing.asl<br>A src/mainboard/biostar/a68n_5200/acpi/sata.asl<br>A src/mainboard/biostar/a68n_5200/acpi/si.asl<br>A src/mainboard/biostar/a68n_5200/acpi/sleep.asl<br>A src/mainboard/biostar/a68n_5200/acpi/superio.asl<br>A src/mainboard/biostar/a68n_5200/acpi/thermal.asl<br>A src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl<br>A src/mainboard/biostar/a68n_5200/acpi_tables.c<br>A src/mainboard/biostar/a68n_5200/board_info.txt<br>A src/mainboard/biostar/a68n_5200/buildOpts.c<br>A src/mainboard/biostar/a68n_5200/cmos.layout<br>A src/mainboard/biostar/a68n_5200/devicetree.cb<br>A src/mainboard/biostar/a68n_5200/dsdt.asl<br>A src/mainboard/biostar/a68n_5200/irq_tables.c<br>A src/mainboard/biostar/a68n_5200/mainboard.c<br>A src/mainboard/biostar/a68n_5200/mptable.c<br>A src/mainboard/biostar/a68n_5200/romstage.c<br>27 files changed, 2,559 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21871/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c<br>new file mode 100644<br>index 0000000..0ff1e9a<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c<br>@@ -0,0 +1,182 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include "AGESA.h"<br>+#include <northbridge/amd/agesa/BiosCallOuts.h><br>+#include <northbridge/amd/agesa/state_machine.h><br>+#include "FchPlatform.h"<br>+#include "cbfs.h"<br>+#include "imc.h"<br>+#include <stdlib.h><br>+<br>+const BIOS_CALLOUT_STRUCT BiosCallouts[] =<br>+{<br>+ {AGESA_DO_RESET, agesa_Reset },<br>+ {AGESA_READ_SPD, agesa_ReadSpd },<br>+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },<br>+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },<br>+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },<br>+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },<br>+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },<br>+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }<br>+};<br>+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);<br>+<br>+/**<br>+ * AMD Olivehill Platform ALC272 Verb Table<br>+ */<br>+static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = {<br>+ {0x11, 0x411111F0}, // - SPDIF_OUT2<br>+ {0x12, 0x411111F0}, // - DMIC_1/2<br>+ {0x13, 0x411111F0}, // - DMIC_3/4<br>+ {0x14, 0x411111F0}, // Port D - LOUT1<br>+ {0x15, 0x411111F0}, // Port A - LOUT2<br>+ {0x16, 0x411111F0}, //<br>+ {0x17, 0x411111F0}, // Port H - MONO<br>+ {0x18, 0x01a19840}, // Port B - MIC1<br>+ {0x19, 0x411111F0}, // Port F - MIC2<br>+ {0x1a, 0x01813030}, // Port C - LINE1<br>+ {0x1b, 0x411111F0}, // Port E - LINE2<br>+ {0x1d, 0x40130605}, // - PCBEEP<br>+ {0x1e, 0x01441120}, // - SPDIF_OUT1<br>+ {0x21, 0x01214010}, // Port I - HPOUT<br>+ {0xff, 0xffffffff}<br>+};<br>+<br>+static const CODEC_TBL_LIST OlivehillCodecTableList[] =<br>+{<br>+ {0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]},<br>+ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}<br>+};<br>+<br>+#define FAN_INPUT_INTERNAL_DIODE 0<br>+#define FAN_INPUT_TEMP0 1<br>+#define FAN_INPUT_TEMP1 2<br>+#define FAN_INPUT_TEMP2 3<br>+#define FAN_INPUT_TEMP3 4<br>+#define FAN_INPUT_TEMP0_FILTER 5<br>+#define FAN_INPUT_ZERO 6<br>+#define FAN_INPUT_DISABLED 7<br>+<br>+#define FAN_AUTOMODE (1 << 0)<br>+#define FAN_LINEARMODE (1 << 1)<br>+#define FAN_STEPMODE ~(1 << 1)<br>+#define FAN_POLARITY_HIGH (1 << 2)<br>+#define FAN_POLARITY_LOW ~(1 << 2)<br>+<br>+/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */<br>+#define FREQ_28KHZ 0x0<br>+#define FREQ_25KHZ 0x1<br>+#define FREQ_23KHZ 0x2<br>+#define FREQ_21KHZ 0x3<br>+#define FREQ_29KHZ 0x4<br>+#define FREQ_18KHZ 0x5<br>+#define FREQ_100HZ 0xF7<br>+#define FREQ_87HZ 0xF8<br>+#define FREQ_58HZ 0xF9<br>+#define FREQ_44HZ 0xFA<br>+#define FREQ_35HZ 0xFB<br>+#define FREQ_29HZ 0xFC<br>+#define FREQ_22HZ 0xFD<br>+#define FREQ_14HZ 0xFE<br>+#define FREQ_11HZ 0xFF<br>+<br>+/* Olivehill Hardware Monitor Fan Control<br>+ * Hardware limitation:<br>+ * HWM failed to read the input temperture vi I2C,<br>+ * if other software switch the I2C switch by mistake or intention.<br>+ * We recommend to using IMC to control Fans, instead of HWM.<br>+ */<br>+static void oem_fan_control(FCH_DATA_BLOCK *FchParams)<br>+{<br>+ /* Enable IMC fan control. the recommand way */<br>+ if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {<br>+ imc_reg_init();<br>+<br>+ /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */<br>+ FchParams->Hwm.HwMonitorEnable = TRUE;<br>+ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */<br>+<br>+ FchParams->Imc.ImcEnable = TRUE;<br>+ FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */<br>+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */<br>+<br>+ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);<br>+<br>+ /* Thermal Zone Parameter */<br>+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;<br>+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */<br>+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;<br>+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3;<br>+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;<br>+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;<br>+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */<br>+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;<br>+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */<br>+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;<br>+<br>+ /* IMC Fan Policy temperature thresholds */<br>+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;<br>+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */<br>+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */<br>+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */<br>+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */<br>+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */<br>+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */<br>+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */<br>+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */<br>+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */<br>+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */<br>+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;<br>+<br>+ /* IMC Fan Policy PWM Settings */<br>+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;<br>+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */<br>+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */<br>+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */<br>+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */<br>+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */<br>+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */<br>+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */<br>+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */<br>+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */<br>+<br>+ FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;<br>+<br>+ /* NOTE:<br>+ * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,<br>+ * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.<br>+ * so we remove it from AGESA code. Please Seee FchInitLateHwm.<br>+ */<br>+ } else {<br>+ /* HWM fan control, the way not recommand */<br>+ FchParams->Imc.ImcEnable = FALSE;<br>+ FchParams->Hwm.HwMonitorEnable = TRUE;<br>+ FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */<br>+ }<br>+}<br>+<br>+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)<br>+{<br>+}<br>+<br>+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)<br>+{<br>+ /* Azalia Controller OEM Codec Table Pointer */<br>+ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]);<br>+<br>+ /* Fan Control */<br>+ oem_fan_control(FchParams_env);<br>+}<br>diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig<br>new file mode 100644<br>index 0000000..55dfb11<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/Kconfig<br>@@ -0,0 +1,62 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+if BOARD_BIOSTAR_A68N5200<br>+<br>+config BOARD_SPECIFIC_OPTIONS # dummy<br>+ def_bool y<br>+ select CPU_AMD_AGESA_FAMILY16_KB<br>+ select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB<br>+ select SOUTHBRIDGE_AMD_AGESA_YANGTZE<br>+ select HAVE_OPTION_TABLE<br>+ select HAVE_PIRQ_TABLE<br>+ select HAVE_MP_TABLE<br>+ select HAVE_ACPI_TABLES<br>+ select BOARD_ROMSIZE_KB_4096<br>+ select GFXUMA<br>+<br>+config MAINBOARD_DIR<br>+ string<br>+ default biostar/a68n_5200<br>+<br>+config MAINBOARD_PART_NUMBER<br>+ string<br>+ default "A68N5200"<br>+<br>+config HW_MEM_HOLE_SIZEK<br>+ hex<br>+ default 0x200000<br>+<br>+config MAX_CPUS<br>+ int<br>+ default 4<br>+<br>+config HW_MEM_HOLE_SIZE_AUTO_INC<br>+ bool<br>+ default n<br>+<br>+config IRQ_SLOT_COUNT<br>+ int<br>+ default 11<br>+<br>+config ONBOARD_VGA_IS_PRIMARY<br>+ bool<br>+ default y<br>+<br>+config HUDSON_LEGACY_FREE<br>+ bool<br>+ default y<br>+<br>+endif # BOARD_BIOSTAR_A68N5200<br>diff --git a/src/mainboard/biostar/a68n_5200/Kconfig.name b/src/mainboard/biostar/a68n_5200/Kconfig.name<br>new file mode 100644<br>index 0000000..52a7f15<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/Kconfig.name<br>@@ -0,0 +1,2 @@<br>+config BOARD_BIOSTAR_A68N5200<br>+ bool "A68N-5200"<br>diff --git a/src/mainboard/biostar/a68n_5200/Makefile.inc b/src/mainboard/biostar/a68n_5200/Makefile.inc<br>new file mode 100644<br>index 0000000..f8895fa<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/Makefile.inc<br>@@ -0,0 +1,22 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+romstage-y += buildOpts.c<br>+romstage-y += BiosCallOuts.c<br>+romstage-y += OemCustomize.c<br>+<br>+ramstage-y += buildOpts.c<br>+ramstage-y += BiosCallOuts.c<br>+ramstage-y += OemCustomize.c<br>diff --git a/src/mainboard/biostar/a68n_5200/OemCustomize.c b/src/mainboard/biostar/a68n_5200/OemCustomize.c<br>new file mode 100644<br>index 0000000..9ed7cee<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/OemCustomize.c<br>@@ -0,0 +1,152 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include "AGESA.h"<br>+#include <PlatformMemoryConfiguration.h><br>+<br>+#include <northbridge/amd/agesa/state_machine.h><br>+<br>+static const PCIe_PORT_DESCRIPTOR PortList[] = {<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,<br>+ HotplugDisabled,<br>+ PcieGenMaxSupported,<br>+ PcieGenMaxSupported,<br>+ AspmDisabled, 0x01, 0)<br>+ },<br>+ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,<br>+ HotplugDisabled,<br>+ PcieGenMaxSupported,<br>+ PcieGenMaxSupported,<br>+ AspmDisabled, 0x02, 0)<br>+ },<br>+ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,<br>+ HotplugDisabled,<br>+ PcieGenMaxSupported,<br>+ PcieGenMaxSupported,<br>+ AspmDisabled, 0x03, 0)<br>+ },<br>+ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,<br>+ HotplugDisabled,<br>+ PcieGenMaxSupported,<br>+ PcieGenMaxSupported,<br>+ AspmDisabled, 0x04, 0)<br>+ },<br>+ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */<br>+ {<br>+ DESCRIPTOR_TERMINATE_LIST,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,<br>+ HotplugDisabled,<br>+ PcieGenMaxSupported,<br>+ PcieGenMaxSupported,<br>+ AspmDisabled, 0x05, 0)<br>+ }<br>+};<br>+<br>+static const PCIe_DDI_DESCRIPTOR DdiList[] = {<br>+ /* DP0 to HDMI0/DP */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),<br>+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)<br>+ },<br>+ /* DP1 to FCH */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),<br>+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)<br>+ },<br>+ /* DP2 to HDMI1/DP */<br>+ {<br>+ DESCRIPTOR_TERMINATE_LIST,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),<br>+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)<br>+ },<br>+};<br>+<br>+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {<br>+ .Flags = DESCRIPTOR_TERMINATE_LIST,<br>+ .SocketId = 0,<br>+ .PciePortList = PortList,<br>+ .DdiLinkList = DdiList<br>+};<br>+<br>+void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)<br>+{<br>+ FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;<br>+ FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);<br>+ FchReset->Xhci1Enable = FALSE;<br>+}<br>+<br>+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)<br>+{<br>+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;<br>+}<br>+<br>+/*----------------------------------------------------------------------------------------<br>+ * CUSTOMER OVERIDES MEMORY TABLE<br>+ *----------------------------------------------------------------------------------------<br>+ */<br>+<br>+/*<br>+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA<br>+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable<br>+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will<br>+ * use its default conservative settings.<br>+ */<br>+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {<br>+ #define SEED_A 0x12<br>+ HW_RXEN_SEED(<br>+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,<br>+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,<br>+ SEED_A),<br>+<br>+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),<br>+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),<br>+ MOTHER_BOARD_LAYERS(LAYERS_4),<br>+<br>+ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),<br>+ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */<br>+ ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),<br>+ CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),<br>+<br>+ PSO_END<br>+};<br>+<br>+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)<br>+{<br>+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;<br>+}<br>+<br>+void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)<br>+{<br>+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */<br>+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;<br>+}<br>diff --git a/src/mainboard/biostar/a68n_5200/OptionsIds.h b/src/mainboard/biostar/a68n_5200/OptionsIds.h<br>new file mode 100644<br>index 0000000..eaf2442<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/OptionsIds.h<br>@@ -0,0 +1,59 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/**<br>+ * @file<br>+ *<br>+ * IDS Option File<br>+ *<br>+ * This file is used to switch on/off IDS features.<br>+ *<br>+ */<br>+#ifndef _OPTION_IDS_H_<br>+#define _OPTION_IDS_H_<br>+<br>+/**<br>+ *<br>+ * This file generates the defaults tables for the Integrated Debug Support<br>+ * Module. The documented build options are imported from a user controlled<br>+ * file for processing. The build options for the Integrated Debug Support<br>+ * Module are listed below:<br>+ *<br>+ * IDSOPT_IDS_ENABLED<br>+ * IDSOPT_ERROR_TRAP_ENABLED<br>+ * IDSOPT_CONTROL_ENABLED<br>+ * IDSOPT_TRACING_ENABLED<br>+ * IDSOPT_PERF_ANALYSIS<br>+ * IDSOPT_ASSERT_ENABLED<br>+ * IDS_DEBUG_PORT<br>+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED<br>+ *<br>+ **/<br>+<br>+#define IDSOPT_IDS_ENABLED TRUE<br>+//#define IDSOPT_CONTROL_ENABLED TRUE<br>+//#define IDSOPT_TRACING_ENABLED TRUE<br>+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE<br>+//#define IDSOPT_PERF_ANALYSIS TRUE<br>+#define IDSOPT_ASSERT_ENABLED TRUE<br>+//#undef IDSOPT_DEBUG_ENABLED<br>+//#define IDSOPT_DEBUG_ENABLED FALSE<br>+//#undef IDSOPT_HOST_SIMNOW<br>+//#define IDSOPT_HOST_SIMNOW FALSE<br>+//#undef IDSOPT_HOST_HDT<br>+//#define IDSOPT_HOST_HDT FALSE<br>+//#define IDS_DEBUG_PORT 0x80<br>+<br>+#endif<br>diff --git a/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl b/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl<br>new file mode 100644<br>index 0000000..aa941ba<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl<br>@@ -0,0 +1,110 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+//BTDC Due to IMC Fan, ACPI control codes<br>+OperationRegion(IMIO, SystemIO, 0x3E, 0x02)<br>+Field(IMIO , ByteAcc, NoLock, Preserve) {<br>+ IMCX,8,<br>+ IMCA,8<br>+}<br>+<br>+IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {<br>+ Offset(0x80),<br>+ MSTI, 8,<br>+ MITS, 8,<br>+ MRG0, 8,<br>+ MRG1, 8,<br>+ MRG2, 8,<br>+ MRG3, 8,<br>+}<br>+<br>+Method(WACK, 0)<br>+{<br>+ Store(0, Local0)<br>+ While (LNotEqual(Local0, 0xFA)) {<br>+ Store(MRG0, Local0)<br>+ Sleep(10)<br>+ }<br>+}<br>+<br>+//Init<br>+Method (ITZE, 0)<br>+{<br>+ Store(0, MRG0)<br>+ Store(0xB5, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x96, MSTI)<br>+ WACK()<br>+<br>+ Store(0, MRG0)<br>+ Store(0, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x80, MSTI)<br>+ WACK()<br>+<br>+ Or(MRG2, 0x01, Local0)<br>+<br>+ Store(0, MRG0)<br>+ Store(0, MRG1)<br>+ Store(Local0, MRG2)<br>+ Store(0x81, MSTI)<br>+ WACK()<br>+}<br>+<br>+//Sleep<br>+Method (IMSP, 0)<br>+{<br>+ Store(0, MRG0)<br>+ Store(0xB5, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x96, MSTI)<br>+ WACK()<br>+<br>+ Store(0, MRG0)<br>+ Store(1, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x98, MSTI)<br>+ WACK()<br>+<br>+ Store(0, MRG0)<br>+ Store(0xB4, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x96, MSTI)<br>+ WACK()<br>+}<br>+<br>+//Wake<br>+Method (IMWK, 0)<br>+{<br>+ Store(0, MRG0)<br>+ Store(0xB5, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x96, MSTI)<br>+ WACK()<br>+<br>+ Store(0, MRG0)<br>+ Store(0, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x80, MSTI)<br>+ WACK()<br>+<br>+ Or(MRG2, 0x01, Local0)<br>+<br>+ Store(0, MRG0)<br>+ Store(0, MRG1)<br>+ Store(Local0, MRG2)<br>+ Store(0x81, MSTI)<br>+ WACK()<br>+}<br>diff --git a/src/mainboard/biostar/a68n_5200/acpi/gpe.asl b/src/mainboard/biostar/a68n_5200/acpi/gpe.asl<br>new file mode 100644<br>index 0000000..9a84698<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/acpi/gpe.asl<br>@@ -0,0 +1,74 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+Scope(\_GPE) { /* Start Scope GPE */<br>+<br>+ /* General event 3 */<br>+ Method(_L03) {<br>+ /* DBGO("\\_GPE\\_L00\n") */<br>+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ }<br>+<br>+ /* Legacy PM event */<br>+ Method(_L08) {<br>+ /* DBGO("\\_GPE\\_L08\n") */<br>+ }<br>+<br>+ /* Temp warning (TWarn) event */<br>+ Method(_L09) {<br>+ /* DBGO("\\_GPE\\_L09\n") */<br>+ /* Notify (\_TZ.TZ00, 0x80) */<br>+ }<br>+<br>+ /* USB controller PME# */<br>+ Method(_L0B) {<br>+ /* DBGO("\\_GPE\\_L0B\n") */<br>+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ }<br>+<br>+ /* ExtEvent0 SCI event */<br>+ Method(_L10) {<br>+ /* DBGO("\\_GPE\\_L10\n") */<br>+ }<br>+<br>+ /* ExtEvent1 SCI event */<br>+ Method(_L11) {<br>+ /* DBGO("\\_GPE\\_L11\n") */<br>+ }<br>+<br>+ /* GPIO0 or GEvent8 event */<br>+ Method(_L18) {<br>+ /* DBGO("\\_GPE\\_L18\n") */<br>+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ }<br>+<br>+ /* Azalia SCI event */<br>+ Method(_L1B) {<br>+ /* DBGO("\\_GPE\\_L1B\n") */<br>+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ }<br>+} /* End Scope GPE */<br>diff --git a/src/mainboard/biostar/a68n_5200/acpi/ide.asl b/src/mainboard/biostar/a68n_5200/acpi/ide.asl<br>new file mode 100644<br>index 0000000..e7f4625<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/acpi/ide.asl<br>@@ -0,0 +1,246 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012-2013 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* No IDE functionality */<br>+<br>+#if 0<br>+/*<br>+Scope (_SB) {<br>+ Device(PCI0) {<br>+ Device(IDEC) {<br>+ Name(_ADR, 0x00140001)<br>+ #include "ide.asl"<br>+ }<br>+ }<br>+}<br>+*/<br>+<br>+/* Some timing tables */<br>+Name(UDTT, Package(){ /* Udma timing table */<br>+ 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */<br>+})<br>+<br>+Name(MDTT, Package(){ /* MWDma timing table */<br>+ 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */<br>+})<br>+<br>+Name(POTT, Package(){ /* Pio timing table */<br>+ 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */<br>+})<br>+<br>+/* Some timing register value tables */<br>+Name(MDRT, Package(){ /* MWDma timing register table */<br>+ 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */<br>+})<br>+<br>+Name(PORT, Package(){<br>+ 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */<br>+})<br>+<br>+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */<br>+ Field(ICRG, AnyAcc, NoLock, Preserve)<br>+{<br>+ PPTS, 8, /* Primary PIO Slave Timing */<br>+ PPTM, 8, /* Primary PIO Master Timing */<br>+ OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */<br>+ PMTM, 8, /* Primary MWDMA Master Timing */<br>+ OFFSET(0x08), PPCR, 8, /* Primary PIO Control */<br>+ OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */<br>+ PPSM, 4, /* Primary PIO slave Mode */<br>+ OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */<br>+ OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */<br>+ PDSM, 4, /* Primary UltraDMA Mode */<br>+}<br>+<br>+Method(GTTM, 1) /* get total time*/<br>+{<br>+ Store(And(Arg0, 0x0F), Local0) /* Recovery Width */<br>+ Increment(Local0)<br>+ Store(ShiftRight(Arg0, 4), Local1) /* Command Width */<br>+ Increment(Local1)<br>+ Return(Multiply(30, Add(Local0, Local1)))<br>+}<br>+<br>+Device(PRID)<br>+{<br>+ Name (_ADR, Zero)<br>+ Method(_GTM, 0)<br>+ {<br>+ NAME(OTBF, Buffer(20) { /* out buffer */<br>+ 0xFF, 0xFF, 0xFF, 0xFF,<br>+ 0xFF, 0xFF, 0xFF, 0xFF,<br>+ 0xFF, 0xFF, 0xFF, 0xFF,<br>+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00<br>+ })<br>+<br>+ CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */<br>+ CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */<br>+ CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */<br>+ CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */<br>+ CreateDwordField(OTBF, 16, BFFG) /* buffer flags */<br>+<br>+ /* Just return if the channel is disabled */<br>+ If(And(PPCR, 0x01)) { /* primary PIO control */<br>+ Return(OTBF)<br>+ }<br>+<br>+ /* Always tell them independent timing available and IOChannelReady used on both drives */<br>+ Or(BFFG, 0x1A, BFFG)<br>+<br>+ /* save total time of primary PIO master timing to PIO spd0 */<br>+ Store(GTTM(PPTM), PSD0)<br>+ /* save total time of primary PIO slave Timing to PIO spd1 */<br>+ Store(GTTM(PPTS), PSD1)<br>+<br>+ If(And(PDCR, 0x01)) { /* It's under UDMA mode */<br>+ Or(BFFG, 0x01, BFFG)<br>+ Store(DerefOf(Index(UDTT, PDMM)), DSD0)<br>+ }<br>+ Else {<br>+ Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */<br>+ }<br>+<br>+ If(And(PDCR, 0x02)) { /* It's under UDMA mode */<br>+ Or(BFFG, 0x04, BFFG)<br>+ Store(DerefOf(Index(UDTT, PDSM)), DSD1)<br>+ }<br>+ Else {<br>+ Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */<br>+ }<br>+<br>+ Return(OTBF) /* out buffer */<br>+ } /* End Method(_GTM) */<br>+<br>+ Method(_STM, 3, NotSerialized)<br>+ {<br>+ NAME(INBF, Buffer(20) { /* in buffer */<br>+ 0xFF, 0xFF, 0xFF, 0xFF,<br>+ 0xFF, 0xFF, 0xFF, 0xFF,<br>+ 0xFF, 0xFF, 0xFF, 0xFF,<br>+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00<br>+ })<br>+<br>+ CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */<br>+ CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */<br>+ CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */<br>+ CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */<br>+ CreateDwordField(INBF, 16, BFFG) /*buffer flag */<br>+<br>+ Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)<br>+ Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */<br>+ Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)<br>+ Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */<br>+<br>+ Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */<br>+ Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */<br>+<br>+ If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */<br>+ Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)<br>+ Divide(Local0, 7, PDMM,)<br>+ Or(PDCR, 0x01, PDCR)<br>+ }<br>+ Else {<br>+ If(LNotEqual(DSD0, 0xFFFFFFFF)) {<br>+ Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)<br>+ Store(DerefOf(Index(MDRT, Local0)), PMTM)<br>+ }<br>+ }<br>+<br>+ If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */<br>+ Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)<br>+ Divide(Local0, 7, PDSM,)<br>+ Or(PDCR, 0x02, PDCR)<br>+ }<br>+ Else {<br>+ If(LNotEqual(DSD1, 0xFFFFFFFF)) {<br>+ Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)<br>+ Store(DerefOf(Index(MDRT, Local0)), PMTS)<br>+ }<br>+ }<br>+ /* Return(INBF) */<br>+ } /*End Method(_STM) */<br>+ Device(MST)<br>+ {<br>+ Name(_ADR, 0)<br>+ Method(_GTF) {<br>+ Name(CMBF, Buffer(21) {<br>+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,<br>+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,<br>+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5<br>+ })<br>+ CreateByteField(CMBF, 1, POMD)<br>+ CreateByteField(CMBF, 8, DMMD)<br>+ CreateByteField(CMBF, 5, CMDA)<br>+ CreateByteField(CMBF, 12, CMDB)<br>+ CreateByteField(CMBF, 19, CMDC)<br>+<br>+ Store(0xA0, CMDA)<br>+ Store(0xA0, CMDB)<br>+ Store(0xA0, CMDC)<br>+<br>+ Or(PPMM, 0x08, POMD)<br>+<br>+ If(And(PDCR, 0x01)) {<br>+ Or(PDMM, 0x40, DMMD)<br>+ }<br>+ Else {<br>+ Store(Match<br>+ (MDTT, MLE, GTTM(PMTM),<br>+ MTR, 0, 0), Local0)<br>+ If(LLess(Local0, 3)) {<br>+ Or(0x20, Local0, DMMD)<br>+ }<br>+ }<br>+ Return(CMBF)<br>+ }<br>+ } /* End Device(MST) */<br>+<br>+ Device(SLAV)<br>+ {<br>+ Name(_ADR, 1)<br>+ Method(_GTF) {<br>+ Name(CMBF, Buffer(21) {<br>+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,<br>+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,<br>+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5<br>+ })<br>+ CreateByteField(CMBF, 1, POMD)<br>+ CreateByteField(CMBF, 8, DMMD)<br>+ CreateByteField(CMBF, 5, CMDA)<br>+ CreateByteField(CMBF, 12, CMDB)<br>+ CreateByteField(CMBF, 19, CMDC)<br>+<br>+ Store(0xB0, CMDA)<br>+ Store(0xB0, CMDB)<br>+ Store(0xB0, CMDC)<br>+<br>+ Or(PPSM, 0x08, POMD)<br>+<br>+ If(And(PDCR, 0x02)) {<br>+ Or(PDSM, 0x40, DMMD)<br>+ }<br>+ Else {<br>+ Store(Match<br>+ (MDTT, MLE, GTTM(PMTS),<br>+ MTR, 0, 0), Local0)<br>+ If(LLess(Local0, 3)) {<br>+ Or(0x20, Local0, DMMD)<br>+ }<br>+ }<br>+ Return(CMBF)<br>+ }<br>+ } /* End Device(SLAV) */<br>+}<br>+#endif<br>diff --git a/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl b/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl<br>new file mode 100644<br>index 0000000..68609d8<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl<br>@@ -0,0 +1,35 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* Memory related values */<br>+Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */<br>+Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */<br>+Name(PBLN, 0x0) /* Length of BIOS area */<br>+<br>+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */<br>+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */<br>+Name(HPBA, 0xFED00000) /* Base address of HPET table */<br>+<br>+/* Some global data */<br>+Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */<br>+Name(OSV, Ones) /* Assume nothing */<br>+Name(PMOD, One) /* Assume APIC */<br>+<br>+/* AcpiGpe0Blk */<br>+OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)<br>+ Field(GP0B, ByteAcc, NoLock, Preserve) {<br>+ , 11,<br>+ USBS, 1,<br>+}<br>diff --git a/src/mainboard/biostar/a68n_5200/acpi/routing.asl b/src/mainboard/biostar/a68n_5200/acpi/routing.asl<br>new file mode 100644<br>index 0000000..7cb7a2f<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/acpi/routing.asl<br>@@ -0,0 +1,193 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/*<br>+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001<br>+ )<br>+ {<br>+ #include "routing.asl"<br>+ }<br>+*/<br>+<br>+/* Routing is in System Bus scope */<br>+Name(PR0, Package(){<br>+ /* NB devices */<br>+ /* Bus 0, Dev 0 - F16 Host Controller */<br>+<br>+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */<br>+ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */<br>+ Package(){0x0001FFFF, 0, INTB, 0 },<br>+ Package(){0x0001FFFF, 1, INTC, 0 },<br>+<br>+<br>+ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */<br>+ Package(){0x0002FFFF, 0, INTC, 0 },<br>+ Package(){0x0002FFFF, 1, INTD, 0 },<br>+ Package(){0x0002FFFF, 2, INTA, 0 },<br>+ Package(){0x0002FFFF, 3, INTB, 0 },<br>+<br>+ /* FCH devices */<br>+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */<br>+ Package(){0x0014FFFF, 0, INTA, 0 },<br>+ Package(){0x0014FFFF, 1, INTB, 0 },<br>+ Package(){0x0014FFFF, 2, INTC, 0 },<br>+ Package(){0x0014FFFF, 3, INTD, 0 },<br>+<br>+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */<br>+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */<br>+ Package(){0x0012FFFF, 0, INTC, 0 },<br>+ Package(){0x0012FFFF, 1, INTB, 0 },<br>+<br>+ Package(){0x0013FFFF, 0, INTC, 0 },<br>+ Package(){0x0013FFFF, 1, INTB, 0 },<br>+<br>+ Package(){0x0016FFFF, 0, INTC, 0 },<br>+ Package(){0x0016FFFF, 1, INTB, 0 },<br>+<br>+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */<br>+ Package(){0x0010FFFF, 0, INTC, 0 },<br>+ Package(){0x0010FFFF, 1, INTB, 0 },<br>+<br>+ /* Bus 0, Dev 17 - SATA controller */<br>+ Package(){0x0011FFFF, 0, INTD, 0 },<br>+<br>+})<br>+<br>+Name(APR0, Package(){<br>+ /* NB devices in APIC mode */<br>+ /* Bus 0, Dev 0 - F15 Host Controller */<br>+<br>+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */<br>+ Package(){0x0001FFFF, 0, 0, 44 },<br>+ Package(){0x0001FFFF, 1, 0, 45 },<br>+<br>+ /* Bus 0, Dev 2 - PCIe Bridges */<br>+ Package(){0x0002FFFF, 0, 0, 24 },<br>+ Package(){0x0002FFFF, 1, 0, 25 },<br>+ Package(){0x0002FFFF, 2, 0, 26 },<br>+ Package(){0x0002FFFF, 3, 0, 27 },<br>+<br>+<br>+ /* SB devices in APIC mode */<br>+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */<br>+ Package(){0x0014FFFF, 0, 0, 16 },<br>+ Package(){0x0014FFFF, 1, 0, 17 },<br>+ Package(){0x0014FFFF, 2, 0, 18 },<br>+ Package(){0x0014FFFF, 3, 0, 19 },<br>+<br>+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */<br>+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */<br>+ Package(){0x0012FFFF, 0, 0, 18 },<br>+ Package(){0x0012FFFF, 1, 0, 17 },<br>+<br>+ Package(){0x0013FFFF, 0, 0, 18 },<br>+ Package(){0x0013FFFF, 1, 0, 17 },<br>+<br>+ Package(){0x0016FFFF, 0, 0, 18 },<br>+ Package(){0x0016FFFF, 1, 0, 17 },<br>+<br>+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */<br>+ Package(){0x0010FFFF, 0, 0, 0x12},<br>+ Package(){0x0010FFFF, 1, 0, 0x11},<br>+<br>+ /* Bus 0, Dev 17 - SATA controller */<br>+ Package(){0x0011FFFF, 0, 0, 19 },<br>+<br>+})<br>+<br>+Name(PS2, Package(){<br>+ Package(){0x0000FFFF, 0, INTC, 0 },<br>+ Package(){0x0000FFFF, 1, INTD, 0 },<br>+ Package(){0x0000FFFF, 2, INTA, 0 },<br>+ Package(){0x0000FFFF, 3, INTB, 0 },<br>+})<br>+Name(APS2, Package(){<br>+ Package(){0x0000FFFF, 0, 0, 18 },<br>+ Package(){0x0000FFFF, 1, 0, 19 },<br>+ Package(){0x0000FFFF, 2, 0, 16 },<br>+ Package(){0x0000FFFF, 3, 0, 17 },<br>+})<br>+<br>+/* GFX */<br>+Name(PS4, Package(){<br>+ Package(){0x0000FFFF, 0, INTA, 0 },<br>+ Package(){0x0000FFFF, 1, INTB, 0 },<br>+ Package(){0x0000FFFF, 2, INTC, 0 },<br>+ Package(){0x0000FFFF, 3, INTD, 0 },<br>+})<br>+Name(APS4, Package(){<br>+ /* PCIe slot - Hooked to PCIe slot 4 */<br>+ Package(){0x0000FFFF, 0, 0, 24 },<br>+ Package(){0x0000FFFF, 1, 0, 25 },<br>+ Package(){0x0000FFFF, 2, 0, 26 },<br>+ Package(){0x0000FFFF, 3, 0, 27 },<br>+})<br>+<br>+/* GPP 0 */<br>+Name(PS5, Package(){<br>+ Package(){0x0000FFFF, 0, INTB, 0 },<br>+ Package(){0x0000FFFF, 1, INTC, 0 },<br>+ Package(){0x0000FFFF, 2, INTD, 0 },<br>+ Package(){0x0000FFFF, 3, INTA, 0 },<br>+})<br>+Name(APS5, Package(){<br>+ Package(){0x0000FFFF, 0, 0, 28 },<br>+ Package(){0x0000FFFF, 1, 0, 29 },<br>+ Package(){0x0000FFFF, 2, 0, 30 },<br>+ Package(){0x0000FFFF, 3, 0, 31 },<br>+})<br>+<br>+/* GPP 1 */<br>+Name(PS6, Package(){<br>+ Package(){0x0000FFFF, 0, INTC, 0 },<br>+ Package(){0x0000FFFF, 1, INTD, 0 },<br>+ Package(){0x0000FFFF, 2, INTA, 0 },<br>+ Package(){0x0000FFFF, 3, INTB, 0 },<br>+})<br>+Name(APS6, Package(){<br>+ Package(){0x0000FFFF, 0, 0, 32 },<br>+ Package(){0x0000FFFF, 1, 0, 33 },<br>+ Package(){0x0000FFFF, 2, 0, 34 },<br>+ Package(){0x0000FFFF, 3, 0, 35 },<br>+})<br>+<br>+/* GPP 2 */<br>+Name(PS7, Package(){<br>+ Package(){0x0000FFFF, 0, INTD, 0 },<br>+ Package(){0x0000FFFF, 1, INTA, 0 },<br>+ Package(){0x0000FFFF, 2, INTB, 0 },<br>+ Package(){0x0000FFFF, 3, INTC, 0 },<br>+})<br>+Name(APS7, Package(){<br>+ Package(){0x0000FFFF, 0, 0, 36 },<br>+ Package(){0x0000FFFF, 1, 0, 37 },<br>+ Package(){0x0000FFFF, 2, 0, 38 },<br>+ Package(){0x0000FFFF, 3, 0, 39 },<br>+})<br>+<br>+/* GPP 3 */<br>+Name(PS8, Package(){<br>+ Package(){0x0000FFFF, 0, INTA, 0 },<br>+ Package(){0x0000FFFF, 1, INTB, 0 },<br>+ Package(){0x0000FFFF, 2, INTC, 0 },<br>+ Package(){0x0000FFFF, 3, INTD, 0 },<br>+})<br>+Name(APS8, Package(){<br>+ Package(){0x0000FFFF, 0, 0, 40 },<br>+ Package(){0x0000FFFF, 1, 0, 41 },<br>+ Package(){0x0000FFFF, 2, 0, 42 },<br>+ Package(){0x0000FFFF, 3, 0, 43 },<br>+})<br>diff --git a/src/mainboard/biostar/a68n_5200/acpi/sata.asl b/src/mainboard/biostar/a68n_5200/acpi/sata.asl<br>new file mode 100644<br>index 0000000..6755258<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/acpi/sata.asl<br>@@ -0,0 +1,146 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012-2013 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* No SATA functionality */<br>+<br>+#if 0<br>+/*<br>+Scope (_SB) {<br>+ Device(PCI0) {<br>+ Device(SATA) {<br>+ Name(_ADR, 0x00110000)<br>+ #include "sata.asl"<br>+ }<br>+ }<br>+}<br>+*/<br>+<br>+Name(STTM, Buffer(20) {<br>+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,<br>+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,<br>+ 0x1f, 0x00, 0x00, 0x00<br>+})<br>+<br>+/* Start by clearing the PhyRdyChg bits */<br>+Method(_INI) {<br>+ \_GPE._L1F()<br>+}<br>+<br>+Device(PMRY)<br>+{<br>+ Name(_ADR, 0)<br>+ Method(_GTM, 0x0, NotSerialized) {<br>+ Return(STTM)<br>+ }<br>+ Method(_STM, 0x3, NotSerialized) {}<br>+<br>+ Device(PMST) {<br>+ Name(_ADR, 0)<br>+ Method(_STA,0) {<br>+ if (LGreater(P0IS,0)) {<br>+ return (0x0F) /* sata is visible */<br>+ }<br>+ else {<br>+ return (0x00) /* sata is missing */<br>+ }<br>+ }<br>+ }/* end of PMST */<br>+<br>+ Device(PSLA)<br>+ {<br>+ Name(_ADR, 1)<br>+ Method(_STA,0) {<br>+ if (LGreater(P1IS,0)) {<br>+ return (0x0F) /* sata is visible */<br>+ }<br>+ else {<br>+ return (0x00) /* sata is missing */<br>+ }<br>+ }<br>+ } /* end of PSLA */<br>+} /* end of PMRY */<br>+<br>+Device(SEDY)<br>+{<br>+ Name(_ADR, 1) /* IDE Scondary Channel */<br>+ Method(_GTM, 0x0, NotSerialized) {<br>+ Return(STTM)<br>+ }<br>+ Method(_STM, 0x3, NotSerialized) {}<br>+<br>+ Device(SMST)<br>+ {<br>+ Name(_ADR, 0)<br>+ Method(_STA,0) {<br>+ if (LGreater(P2IS,0)) {<br>+ return (0x0F) /* sata is visible */<br>+ }<br>+ else {<br>+ return (0x00) /* sata is missing */<br>+ }<br>+ }<br>+ } /* end of SMST */<br>+<br>+ Device(SSLA)<br>+ {<br>+ Name(_ADR, 1)<br>+ Method(_STA,0) {<br>+ if (LGreater(P3IS,0)) {<br>+ return (0x0F) /* sata is visible */<br>+ }<br>+ else {<br>+ return (0x00) /* sata is missing */<br>+ }<br>+ }<br>+ } /* end of SSLA */<br>+} /* end of SEDY */<br>+<br>+/* SATA Hot Plug Support */<br>+Scope(\_GPE) {<br>+ Method(_L1F,0x0,NotSerialized) {<br>+ if (\_SB.P0PR) {<br>+ if (LGreater(\_SB.P0IS,0)) {<br>+ sleep(32)<br>+ }<br>+ Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */<br>+ store(one, \_SB.P0PR)<br>+ }<br>+<br>+ if (\_SB.P1PR) {<br>+ if (LGreater(\_SB.P1IS,0)) {<br>+ sleep(32)<br>+ }<br>+ Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */<br>+ store(one, \_SB.P1PR)<br>+ }<br>+<br>+ if (\_SB.P2PR) {<br>+ if (LGreater(\_SB.P2IS,0)) {<br>+ sleep(32)<br>+ }<br>+ Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */<br>+ store(one, \_SB.P2PR)<br>+ }<br>+<br>+ if (\_SB.P3PR) {<br>+ if (LGreater(\_SB.P3IS,0)) {<br>+ sleep(32)<br>+ }<br>+ Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */<br>+ store(one, \_SB.P3PR)<br>+ }<br>+ }<br>+}<br>+#endif<br>diff --git a/src/mainboard/biostar/a68n_5200/acpi/si.asl b/src/mainboard/biostar/a68n_5200/acpi/si.asl<br>new file mode 100644<br>index 0000000..2923471<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/acpi/si.asl<br>@@ -0,0 +1,23 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+Scope(\_SI) {<br>+ Method(_SST, 1) {<br>+ /* DBGO("\\_SI\\_SST\n") */<br>+ /* DBGO(" New Indicator state: ") */<br>+ /* DBGO(Arg0) */<br>+ /* DBGO("\n") */<br>+ }<br>+} /* End Scope SI */<br>diff --git a/src/mainboard/biostar/a68n_5200/acpi/sleep.asl b/src/mainboard/biostar/a68n_5200/acpi/sleep.asl<br>new file mode 100644<br>index 0000000..1225a62<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/acpi/sleep.asl<br>@@ -0,0 +1,93 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* Wake status package */<br>+Name(WKST,Package(){Zero, Zero})<br>+<br>+/*<br>+* \_PTS - Prepare to Sleep method<br>+*<br>+* Entry:<br>+* Arg0=The value of the sleeping state S1=1, S2=2, etc<br>+*<br>+* Exit:<br>+* -none-<br>+*<br>+* The _PTS control method is executed at the beginning of the sleep process<br>+* for S1-S5. The sleeping value is passed to the _PTS control method. This<br>+* control method may be executed a relatively long time before entering the<br>+* sleep state and the OS may abort the operation without notification to<br>+* the ACPI driver. This method cannot modify the configuration or power<br>+* state of any device in the system.<br>+*/<br>+<br>+External(\_SB.APTS, MethodObj)<br>+External(\_SB.AWAK, MethodObj)<br>+<br>+Method(_PTS, 1) {<br>+ /* DBGO("\\_PTS\n") */<br>+ /* DBGO("From S0 to S") */<br>+ /* DBGO(Arg0) */<br>+ /* DBGO("\n") */<br>+<br>+ /* Clear wake status structure. */<br>+ Store(0, Index(WKST,0))<br>+ Store(0, Index(WKST,1))<br>+ Store(7, UPWS)<br>+ \_SB.APTS(Arg0)<br>+} /* End Method(\_PTS) */<br>+<br>+/*<br>+* \_BFS OEM Back From Sleep method<br>+*<br>+* Entry:<br>+* Arg0=The value of the sleeping state S1=1, S2=2<br>+*<br>+* Exit:<br>+* -none-<br>+*/<br>+Method(\_BFS, 1) {<br>+ /* DBGO("\\_BFS\n") */<br>+ /* DBGO("From S") */<br>+ /* DBGO(Arg0) */<br>+ /* DBGO(" to S0\n") */<br>+}<br>+<br>+/*<br>+* \_WAK System Wake method<br>+*<br>+* Entry:<br>+* Arg0=The value of the sleeping state S1=1, S2=2<br>+*<br>+* Exit:<br>+* Return package of 2 DWords<br>+* Dword 1 - Status<br>+* 0x00000000 wake succeeded<br>+* 0x00000001 Wake was signaled but failed due to lack of power<br>+* 0x00000002 Wake was signaled but failed due to thermal condition<br>+* Dword 2 - Power Supply state<br>+* if non-zero the effective S-state the power supply entered<br>+*/<br>+Method(\_WAK, 1) {<br>+ /* DBGO("\\_WAK\n") */<br>+ /* DBGO("From S") */<br>+ /* DBGO(Arg0) */<br>+ /* DBGO(" to S0\n") */<br>+ Store(1,USBS)<br>+<br>+ \_SB.AWAK(Arg0)<br>+<br>+ Return(WKST)<br>+} /* End Method(\_WAK) */<br>diff --git a/src/mainboard/biostar/a68n_5200/acpi/superio.asl b/src/mainboard/biostar/a68n_5200/acpi/superio.asl<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/acpi/superio.asl<br>diff --git a/src/mainboard/biostar/a68n_5200/acpi/thermal.asl b/src/mainboard/biostar/a68n_5200/acpi/thermal.asl<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/acpi/thermal.asl<br>diff --git a/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl b/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl<br>new file mode 100644<br>index 0000000..acdc8f8<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl<br>@@ -0,0 +1,128 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* simple name description */<br>+/*<br>+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001<br>+ )<br>+ {<br>+ #include "usb.asl"<br>+ }<br>+*/<br>+<br>+/* USB overcurrent mapping pins. */<br>+Name(UOM0, 0)<br>+Name(UOM1, 2)<br>+Name(UOM2, 0)<br>+Name(UOM3, 7)<br>+Name(UOM4, 2)<br>+Name(UOM5, 2)<br>+Name(UOM6, 6)<br>+Name(UOM7, 2)<br>+Name(UOM8, 6)<br>+Name(UOM9, 6)<br>+<br>+/* USB Overcurrent GPEs */<br>+<br>+#if 0 /* TODO: Update for Olivehill */<br>+Method(UCOC, 0) {<br>+ Sleep(20)<br>+ Store(0x13,CMTI)<br>+ Store(0,GPSL)<br>+}<br>+<br>+/* USB Port 0 overcurrent uses Gpm 0 */<br>+If(LLessEqual(UOM0,9)) {<br>+ Scope (\_GPE) {<br>+ Method (_L13) {<br>+ }<br>+ }<br>+}<br>+<br>+/* USB Port 1 overcurrent uses Gpm 1 */<br>+If (LLessEqual(UOM1,9)) {<br>+ Scope (\_GPE) {<br>+ Method (_L14) {<br>+ }<br>+ }<br>+}<br>+<br>+/* USB Port 2 overcurrent uses Gpm 2 */<br>+If (LLessEqual(UOM2,9)) {<br>+ Scope (\_GPE) {<br>+ Method (_L15) {<br>+ }<br>+ }<br>+}<br>+<br>+/* USB Port 3 overcurrent uses Gpm 3 */<br>+If (LLessEqual(UOM3,9)) {<br>+ Scope (\_GPE) {<br>+ Method (_L16) {<br>+ }<br>+ }<br>+}<br>+<br>+/* USB Port 4 overcurrent uses Gpm 4 */<br>+If (LLessEqual(UOM4,9)) {<br>+ Scope (\_GPE) {<br>+ Method (_L19) {<br>+ }<br>+ }<br>+}<br>+<br>+/* USB Port 5 overcurrent uses Gpm 5 */<br>+If (LLessEqual(UOM5,9)) {<br>+ Scope (\_GPE) {<br>+ Method (_L1A) {<br>+ }<br>+ }<br>+}<br>+<br>+/* USB Port 6 overcurrent uses Gpm 6 */<br>+If (LLessEqual(UOM6,9)) {<br>+ Scope (\_GPE) {<br>+ /* Method (_L1C) { */<br>+ Method (_L06) {<br>+ }<br>+ }<br>+}<br>+<br>+/* USB Port 7 overcurrent uses Gpm 7 */<br>+If (LLessEqual(UOM7,9)) {<br>+ Scope (\_GPE) {<br>+ /* Method (_L1D) { */<br>+ Method (_L07) {<br>+ }<br>+ }<br>+}<br>+<br>+/* USB Port 8 overcurrent uses Gpm 8 */<br>+If (LLessEqual(UOM8,9)) {<br>+ Scope (\_GPE) {<br>+ Method (_L17) {<br>+ }<br>+ }<br>+}<br>+<br>+/* USB Port 9 overcurrent uses Gpm 9 */<br>+If (LLessEqual(UOM9,9)) {<br>+ Scope (\_GPE) {<br>+ Method (_L0E) {<br>+ }<br>+ }<br>+}<br>+#endif<br>diff --git a/src/mainboard/biostar/a68n_5200/acpi_tables.c b/src/mainboard/biostar/a68n_5200/acpi_tables.c<br>new file mode 100644<br>index 0000000..73f305a<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/acpi_tables.c<br>@@ -0,0 +1,52 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <string.h><br>+#include <arch/acpi.h><br>+#include <arch/acpigen.h><br>+#include <arch/ioapic.h><br>+#include <device/pci.h><br>+#include <device/pci_ids.h><br>+<br>+<br>+unsigned long acpi_fill_madt(unsigned long current)<br>+{<br>+ /* create all subtables for processors */<br>+ current = acpi_create_madt_lapics(current);<br>+<br>+ /* Write SB800 IOAPIC, only one */<br>+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,<br>+ IO_APIC_ADDR, 0);<br>+<br>+ /* TODO: Remove the hardcode */<br>+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,<br>+ 0xFEC20000, 24);<br>+<br>+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)<br>+ current, 0, 0, 2, 0);<br>+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)<br>+ current, 0, 9, 9, 0xF);<br>+ /* 0: mean bus 0--->ISA */<br>+ /* 0: PIC 0 */<br>+ /* 2: APIC 2 */<br>+ /* 5 mean: 0101 --> Edge-triggered, Active high */<br>+<br>+ /* create all subtables for processors */<br>+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);<br>+ /* 1: LINT1 connect to NMI */<br>+<br>+ return current;<br>+}<br>diff --git a/src/mainboard/biostar/a68n_5200/board_info.txt b/src/mainboard/biostar/a68n_5200/board_info.txt<br>new file mode 100644<br>index 0000000..b351b8e<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/board_info.txt<br>@@ -0,0 +1 @@<br>+Category: eval<br>diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c<br>new file mode 100644<br>index 0000000..171aa48<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/buildOpts.c<br>@@ -0,0 +1,342 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/**<br>+ * @file<br>+ *<br>+ * AMD User options selection for a Brazos platform solution system<br>+ *<br>+ * This file is placed in the user's platform directory and contains the<br>+ * build option selections desired for that platform.<br>+ *<br>+ * For Information about this file, see @ref platforminstall.<br>+ *<br>+ */<br>+<br>+#include <stdlib.h><br>+#include "AGESA.h"<br>+<br>+#define INSTALL_FT3_SOCKET_SUPPORT TRUE<br>+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE<br>+<br>+#define INSTALL_G34_SOCKET_SUPPORT FALSE<br>+#define INSTALL_C32_SOCKET_SUPPORT FALSE<br>+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE<br>+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE<br>+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE<br>+#define INSTALL_FS1_SOCKET_SUPPORT FALSE<br>+#define INSTALL_FM1_SOCKET_SUPPORT FALSE<br>+#define INSTALL_FP2_SOCKET_SUPPORT FALSE<br>+#define INSTALL_FT1_SOCKET_SUPPORT FALSE<br>+#define INSTALL_AM3_SOCKET_SUPPORT FALSE<br>+#define INSTALL_FM2_SOCKET_SUPPORT FALSE<br>+<br>+<br>+#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT<br>+ #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE<br>+ #undef INSTALL_FT3_SOCKET_SUPPORT<br>+ #define INSTALL_FT3_SOCKET_SUPPORT FALSE<br>+ #endif<br>+#endif<br>+<br>+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE<br>+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE<br>+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE<br>+//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE<br>+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE<br>+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE<br>+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE<br>+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE<br>+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE<br>+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE<br>+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE<br>+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE<br>+#define BLDOPT_REMOVE_SRAT FALSE //TRUE<br>+#define BLDOPT_REMOVE_SLIT FALSE //TRUE<br>+#define BLDOPT_REMOVE_WHEA FALSE //TRUE<br>+#define BLDOPT_REMOVE_CRAT TRUE<br>+#define BLDOPT_REMOVE_CDIT TRUE<br>+#define BLDOPT_REMOVE_DMI TRUE<br>+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE<br>+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE<br>+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE<br>+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE<br>+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE<br>+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE<br>+<br>+//This element selects whether P-States should be forced to be independent,<br>+// as reported by the ACPI _PSD object. For single-link processors,<br>+// setting TRUE for OS to support this feature.<br>+<br>+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE<br>+<br>+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS<br>+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER<br>+/* Build configuration values here.<br>+ */<br>+#define BLDCFG_VRM_CURRENT_LIMIT 15000<br>+#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000<br>+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000<br>+#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT<br>+#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000<br>+#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT<br>+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0<br>+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0<br>+#define BLDCFG_VRM_SLEW_RATE 10000<br>+#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE<br>+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE<br>+<br>+#define BLDCFG_PLAT_NUM_IO_APICS 3<br>+#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000<br>+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST<br>+#define BLDCFG_MEM_INIT_PSTATE 0<br>+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the<br>+ // core for C-state entry requests. A value<br>+ // of 0 in this field specifies that the core<br>+ // does not trap any IO addresses for C-state entry.<br>+ // Values greater than 0xFFF8 results in undefined behavior.<br>+#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770<br>+<br>+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE<br>+<br>+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY<br>+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE<br>+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE<br>+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED<br>+#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE<br>+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE<br>+#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE<br>+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE<br>+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE<br>+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE<br>+#define BLDCFG_MEMORY_POWER_DOWN TRUE<br>+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT<br>+#define BLDCFG_ONLINE_SPARE FALSE<br>+#define BLDCFG_BANK_SWIZZLE TRUE<br>+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO<br>+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY<br>+#define BLDCFG_DQS_TRAINING_CONTROL TRUE<br>+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE<br>+#define BLDCFG_USE_BURST_MODE FALSE<br>+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE<br>+#define BLDCFG_ENABLE_ECC_FEATURE TRUE<br>+#define BLDCFG_ECC_REDIRECTION FALSE<br>+#define BLDCFG_SCRUB_DRAM_RATE 0<br>+#define BLDCFG_SCRUB_L2_RATE 0<br>+#define BLDCFG_SCRUB_L3_RATE 0<br>+#define BLDCFG_SCRUB_IC_RATE 0<br>+#define BLDCFG_SCRUB_DC_RATE 0<br>+#define BLDCFG_ECC_SYNC_FLOOD TRUE<br>+#define BLDCFG_ECC_SYMBOL_SIZE 4<br>+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul<br>+#define BLDCFG_1GB_ALIGN FALSE<br>+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED<br>+#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO<br>+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled<br>+#define BLDCFG_IOMMU_SUPPORT FALSE<br>+#define OPTION_GFX_INIT_SVIEW FALSE<br>+//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife<br>+<br>+//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL<br>+#define BLDCFG_CFG_ABM_SUPPORT TRUE<br>+<br>+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE<br>+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID<br>+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID<br>+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID<br>+<br>+#ifdef PCIEX_BASE_ADDRESS<br>+#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS<br>+#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)<br>+#endif<br>+<br>+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'<br>+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'<br>+#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed<br>+<br>+/* Process the options...<br>+ * This file include MUST occur AFTER the user option selection settings<br>+ */<br>+/*<br>+ * Customized OEM build configurations for FCH component<br>+ */<br>+// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00<br>+// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20<br>+// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00<br>+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400<br>+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404<br>+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408<br>+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410<br>+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420<br>+// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000<br>+// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000<br>+// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000<br>+// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0<br>+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00<br>+// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000<br>+// #define BLDCFG_AZALIA_SSID 0x780D1022<br>+// #define BLDCFG_SMBUS_SSID 0x780B1022<br>+// #define BLDCFG_IDE_SSID 0x780C1022<br>+// #define BLDCFG_SATA_AHCI_SSID 0x78011022<br>+// #define BLDCFG_SATA_IDE_SSID 0x78001022<br>+// #define BLDCFG_SATA_RAID5_SSID 0x78031022<br>+// #define BLDCFG_SATA_RAID_SSID 0x78021022<br>+// #define BLDCFG_EHCI_SSID 0x78081022<br>+// #define BLDCFG_OHCI_SSID 0x78071022<br>+// #define BLDCFG_LPC_SSID 0x780E1022<br>+// #define BLDCFG_SD_SSID 0x78061022<br>+// #define BLDCFG_XHCI_SSID 0x78121022<br>+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE<br>+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE<br>+// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4<br>+// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE<br>+// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE<br>+// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE<br>+// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE<br>+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE<br>+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE<br>+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE<br>+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE<br>+<br>+CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =<br>+{<br>+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },<br>+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },<br>+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },<br>+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },<br>+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },<br>+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },<br>+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },<br>+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },<br>+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },<br>+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },<br>+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },<br>+ { CPU_LIST_TERMINAL }<br>+};<br>+<br>+#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList<br>+<br>+<br>+/* Include the files that instantiate the configuration definitions. */<br>+#include "cpuRegisters.h"<br>+#include "cpuFamRegisters.h"<br>+#include "cpuFamilyTranslation.h"<br>+#include "AdvancedApi.h"<br>+#include "heapManager.h"<br>+#include "CreateStruct.h"<br>+#include "cpuFeatures.h"<br>+#include "Table.h"<br>+#include "cpuEarlyInit.h"<br>+#include "cpuLateInit.h"<br>+#include "GnbInterface.h"<br>+<br>+ // This is the delivery package title, "BrazosPI"<br>+ // This string MUST be exactly 8 characters long<br>+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}<br>+<br>+ // This is the release version number of the AGESA component<br>+ // This string MUST be exactly 12 characters long<br>+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}<br>+<br>+/* MEMORY_BUS_SPEED */<br>+//#define DDR400_FREQUENCY 200 ///< DDR 400<br>+//#define DDR533_FREQUENCY 266 ///< DDR 533<br>+//#define DDR667_FREQUENCY 333 ///< DDR 667<br>+//#define DDR800_FREQUENCY 400 ///< DDR 800<br>+//#define DDR1066_FREQUENCY 533 ///< DDR 1066<br>+//#define DDR1333_FREQUENCY 667 ///< DDR 1333<br>+//#define DDR1600_FREQUENCY 800 ///< DDR 1600<br>+//#define DDR1866_FREQUENCY 933 ///< DDR 1866<br>+//#define DDR2100_FREQUENCY 1050 ///< DDR 2100<br>+//#define DDR2133_FREQUENCY 1066 ///< DDR 2133<br>+//#define DDR2400_FREQUENCY 1200 ///< DDR 2400<br>+//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency<br>+//<br>+///* QUANDRANK_TYPE*/<br>+//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM<br>+//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM<br>+//<br>+///* USER_MEMORY_TIMING_MODE */<br>+//#define TIMING_MODE_AUTO 0 ///< Use best rate possible<br>+//#define TIMING_MODE_LIMITED 1 ///< Set user top limit<br>+//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed<br>+//<br>+///* POWER_DOWN_MODE */<br>+//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode<br>+//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode<br>+<br>+/*<br>+ * Agesa optional capabilities selection.<br>+ * Uncomment and mark FALSE those features you wish to include in the build.<br>+ * Comment out or mark TRUE those features you want to REMOVE from the build.<br>+ */<br>+<br>+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00<br>+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20<br>+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00<br>+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800<br>+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804<br>+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808<br>+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810<br>+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820<br>+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000<br>+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0<br>+#define DFLT_HPET_BASE_ADDRESS 0xFED00000<br>+#define DFLT_SMI_CMD_PORT 0xB0<br>+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00<br>+#define DFLT_GEC_BASE_ADDRESS 0xFED61000<br>+#define DFLT_AZALIA_SSID 0x780D1022<br>+#define DFLT_SMBUS_SSID 0x780B1022<br>+#define DFLT_IDE_SSID 0x780C1022<br>+#define DFLT_SATA_AHCI_SSID 0x78011022<br>+#define DFLT_SATA_IDE_SSID 0x78001022<br>+#define DFLT_SATA_RAID5_SSID 0x78031022<br>+#define DFLT_SATA_RAID_SSID 0x78021022<br>+#define DFLT_EHCI_SSID 0x78081022<br>+#define DFLT_OHCI_SSID 0x78071022<br>+#define DFLT_LPC_SSID 0x780E1022<br>+#define DFLT_SD_SSID 0x78061022<br>+#define DFLT_XHCI_SSID 0x78121022<br>+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE<br>+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE<br>+#define DFLT_FCH_GPP_LINK_CONFIG PortA4<br>+#define DFLT_FCH_GPP_PORT0_PRESENT FALSE<br>+#define DFLT_FCH_GPP_PORT1_PRESENT FALSE<br>+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE<br>+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE<br>+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE<br>+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE<br>+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE<br>+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE<br>+//#define BLDCFG_IR_PIN_CONTROL 0x33<br>+<br>+GPIO_CONTROL olivehill_gpio[] = {<br>+ {183, Function1, GpioIn | GpioOutEnB | PullUpB},<br>+ {-1}<br>+};<br>+//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0])<br>+<br>+// The following definitions specify the default values for various parameters in which there are<br>+// no clearly defined defaults to be used in the common file. The values below are based on product<br>+// and BKDG content, please consult the AGESA Memory team for consultation.<br>+#define DFLT_SCRUB_DRAM_RATE (0)<br>+#define DFLT_SCRUB_L2_RATE (0)<br>+#define DFLT_SCRUB_L3_RATE (0)<br>+#define DFLT_SCRUB_IC_RATE (0)<br>+#define DFLT_SCRUB_DC_RATE (0)<br>+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED<br>+#define DFLT_VRM_SLEW_RATE (5000)<br>+<br>+#include <PlatformInstall.h><br>diff --git a/src/mainboard/biostar/a68n_5200/cmos.layout b/src/mainboard/biostar/a68n_5200/cmos.layout<br>new file mode 100644<br>index 0000000..25860f6<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/cmos.layout<br>@@ -0,0 +1,66 @@<br>+#*****************************************************************************<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#*****************************************************************************<br>+<br>+entries<br>+<br>+0 384 r 0 reserved_memory<br>+384 1 e 4 boot_option<br>+388 4 h 0 reboot_counter<br>+#392 3 r 0 unused<br>+395 1 e 1 hw_scrubber<br>+396 1 e 1 interleave_chip_selects<br>+397 2 e 8 max_mem_clock<br>+399 1 e 2 multi_core<br>+400 1 e 1 power_on_after_fail<br>+412 4 e 6 debug_level<br>+440 4 e 9 slow_cpu<br>+444 1 e 1 nmi<br>+445 1 e 1 iommu<br>+456 1 e 1 ECC_memory<br>+728 256 h 0 user_data<br>+984 16 h 0 check_sum<br>+# Reserve the extended AMD configuration registers<br>+1000 24 r 0 amd_reserved<br>+<br>+enumerations<br>+<br>+#ID value text<br>+1 0 Disable<br>+1 1 Enable<br>+2 0 Enable<br>+2 1 Disable<br>+4 0 Fallback<br>+4 1 Normal<br>+6 6 Notice<br>+6 7 Info<br>+6 8 Debug<br>+6 9 Spew<br>+8 0 400Mhz<br>+8 1 333Mhz<br>+8 2 266Mhz<br>+8 3 200Mhz<br>+9 0 off<br>+9 1 87.5%<br>+9 2 75.0%<br>+9 3 62.5%<br>+9 4 50.0%<br>+9 5 37.5%<br>+9 6 25.0%<br>+9 7 12.5%<br>+<br>+checksums<br>+<br>+checksum 392 983 984<br>diff --git a/src/mainboard/biostar/a68n_5200/devicetree.cb b/src/mainboard/biostar/a68n_5200/devicetree.cb<br>new file mode 100644<br>index 0000000..a027db9<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/devicetree.cb<br>@@ -0,0 +1,72 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2013 Advanced Micro Devices, Inc.<br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+chip northbridge/amd/agesa/family16kb/root_complex<br>+ device cpu_cluster 0 on<br>+ chip cpu/amd/agesa/family16kb<br>+ device lapic 0 on end<br>+ end<br>+ end<br>+<br>+ device domain 0 on<br>+ subsystemid 0x1022 0x1410 inherit<br>+ chip northbridge/amd/agesa/family16kb # CPU side of HT root complex<br>+<br>+ chip northbridge/amd/agesa/family16kb # PCI side of HT root complex<br>+ device pci 0.0 on end # Root Complex<br>+ device pci 1.0 on end # Internal Graphics P2P bridge 0x9804<br>+ device pci 1.1 on end # Internal Multimedia<br>+ device pci 2.0 on end # PCIe Host Bridge<br>+ device pci 2.1 on end # x4 PCIe slot<br>+ device pci 2.2 on end # mPCIe slot<br>+ device pci 2.3 on end # Realtek NIC<br>+ device pci 2.4 on end # Edge Connector<br>+ device pci 2.5 on end # Edge Connector<br>+ end #chip northbridge/amd/agesa/family16kb<br>+<br>+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus<br>+ device pci 10.0 on end # XHCI HC0<br>+ device pci 11.0 on end # SATA<br>+ device pci 12.0 on end # USB<br>+ device pci 12.2 on end # USB<br>+ device pci 13.0 on end # USB<br>+ device pci 13.2 on end # USB<br>+ device pci 14.0 on # SM<br>+ chip drivers/generic/generic #dimm 0-0-0<br>+ device i2c 50 on end<br>+ end<br>+ chip drivers/generic/generic #dimm 0-0-1<br>+ device i2c 51 on end<br>+ end<br>+ end # SM<br>+ device pci 14.2 on end # HDA 0x4383<br>+ device pci 14.3 on end # LPC 0x439d<br>+ device pci 14.7 on end # SD<br>+ end #chip southbridge/amd/agesa/hudson<br>+<br>+ device pci 18.0 on end<br>+ device pci 18.1 on end<br>+ device pci 18.2 on end<br>+ device pci 18.3 on end<br>+ device pci 18.4 on end<br>+ device pci 18.5 on end<br>+ register "spdAddrLookup" = "<br>+ {<br>+ { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses<br>+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses<br>+ }"<br>+<br>+ end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex<br>+ end #domain<br>+end #northbridge/amd/agesa/family16kb/root_complex<br>diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl<br>new file mode 100644<br>index 0000000..e709989<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/dsdt.asl<br>@@ -0,0 +1,87 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* DefinitionBlock Statement */<br>+DefinitionBlock (<br>+ "DSDT.AML", /* Output filename */<br>+ "DSDT", /* Signature */<br>+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */<br>+ "AMD ", /* OEMID */<br>+ "COREBOOT", /* TABLE ID */<br>+ 0x00010001 /* OEM Revision */<br>+ )<br>+{ /* Start of ASL file */<br>+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */<br>+<br>+ /* Globals for the platform */<br>+ #include "acpi/mainboard.asl"<br>+<br>+ /* Describe the USB Overcurrent pins */<br>+ #include "acpi/usb_oc.asl"<br>+<br>+ /* PCI IRQ mapping for the Southbridge */<br>+ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl><br>+<br>+ /* Describe the processor tree (\_PR) */<br>+ #include <cpu/amd/agesa/family16kb/acpi/cpu.asl><br>+<br>+ /* Contains the supported sleep states for this chipset */<br>+ #include <southbridge/amd/common/acpi/sleepstates.asl><br>+<br>+ /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */<br>+ #include "acpi/sleep.asl"<br>+<br>+ /* System Bus */<br>+ Scope(\_SB) { /* Start \_SB scope */<br>+ /* global utility methods expected within the \_SB scope */<br>+ #include <arch/x86/acpi/globutil.asl><br>+<br>+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */<br>+ #include "acpi/routing.asl"<br>+<br>+ Device(PWRB) {<br>+ Name(_HID, EISAID("PNP0C0C"))<br>+ Name(_UID, 0xAA)<br>+ Name(_PRW, Package () {3, 0x04})<br>+ Name(_STA, 0x0B)<br>+ }<br>+<br>+ Device(PCI0) {<br>+ /* Describe the AMD Northbridge */<br>+ #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl><br>+<br>+ /* Describe the AMD Fusion Controller Hub Southbridge */<br>+ #include <southbridge/amd/agesa/hudson/acpi/fch.asl><br>+ }<br>+<br>+ /* Describe PCI INT[A-H] for the Southbridge */<br>+ #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl><br>+<br>+ } /* End \_SB scope */<br>+<br>+ /* Describe SMBUS for the Southbridge */<br>+ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl><br>+<br>+ /* Define the General Purpose Events for the platform */<br>+ #include "acpi/gpe.asl"<br>+<br>+ /* Define the Thermal zones and methods for the platform */<br>+ #include "acpi/thermal.asl"<br>+<br>+ /* Define the System Indicators for the platform */<br>+ #include "acpi/si.asl"<br>+}<br>+/* End of ASL file */<br>diff --git a/src/mainboard/biostar/a68n_5200/irq_tables.c b/src/mainboard/biostar/a68n_5200/irq_tables.c<br>new file mode 100644<br>index 0000000..e18e478<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/irq_tables.c<br>@@ -0,0 +1,101 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <device/pci.h><br>+#include <string.h><br>+#include <stdint.h><br>+#include <arch/pirq_routing.h><br>+<br>+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,<br>+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,<br>+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,<br>+ u8 slot, u8 rfu)<br>+{<br>+ pirq_info->bus = bus;<br>+ pirq_info->devfn = devfn;<br>+ pirq_info->irq[0].link = link0;<br>+ pirq_info->irq[0].bitmap = bitmap0;<br>+ pirq_info->irq[1].link = link1;<br>+ pirq_info->irq[1].bitmap = bitmap1;<br>+ pirq_info->irq[2].link = link2;<br>+ pirq_info->irq[2].bitmap = bitmap2;<br>+ pirq_info->irq[3].link = link3;<br>+ pirq_info->irq[3].bitmap = bitmap3;<br>+ pirq_info->slot = slot;<br>+ pirq_info->rfu = rfu;<br>+}<br>+<br>+unsigned long write_pirq_routing_table(unsigned long addr)<br>+{<br>+ struct irq_routing_table *pirq;<br>+ struct irq_info *pirq_info;<br>+ u32 slot_num;<br>+ u8 *v;<br>+<br>+ u8 sum = 0;<br>+ int i;<br>+<br>+ /* Align the table to be 16 byte aligned. */<br>+ addr += 15;<br>+ addr &= ~15;<br>+<br>+ /* This table must be between 0xf0000 & 0x100000 */<br>+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);<br>+<br>+ pirq = (void *)(addr);<br>+ v = (u8 *) (addr);<br>+<br>+ pirq->signature = PIRQ_SIGNATURE;<br>+ pirq->version = PIRQ_VERSION;<br>+<br>+ pirq->rtr_bus = 0;<br>+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);<br>+<br>+ pirq->exclusive_irqs = 0;<br>+<br>+ pirq->rtr_vendor = 0x1002;<br>+ pirq->rtr_device = 0x4384;<br>+<br>+ pirq->miniport_data = 0;<br>+<br>+ memset(pirq->rfu, 0, sizeof(pirq->rfu));<br>+<br>+ pirq_info = (void *)(&pirq->checksum + 1);<br>+ slot_num = 0;<br>+<br>+ /* pci bridge */<br>+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),<br>+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,<br>+ 0);<br>+ pirq_info++;<br>+<br>+ slot_num++;<br>+<br>+ pirq->size = 32 + 16 * slot_num;<br>+<br>+ for (i = 0; i < pirq->size; i++)<br>+ sum += v[i];<br>+<br>+ sum = pirq->checksum - sum;<br>+<br>+ if (sum != pirq->checksum) {<br>+ pirq->checksum = sum;<br>+ }<br>+<br>+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");<br>+<br>+ return (unsigned long)pirq_info;<br>+}<br>diff --git a/src/mainboard/biostar/a68n_5200/mainboard.c b/src/mainboard/biostar/a68n_5200/mainboard.c<br>new file mode 100644<br>index 0000000..a149ee5<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/mainboard.c<br>@@ -0,0 +1,29 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <device/device.h><br>+<br>+/**********************************************<br>+ * enable the dedicated function in mainboard.<br>+ **********************************************/<br>+static void mainboard_enable(device_t dev)<br>+{<br>+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");<br>+}<br>+<br>+struct chip_operations mainboard_ops = {<br>+ .enable_dev = mainboard_enable,<br>+};<br>diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c<br>new file mode 100644<br>index 0000000..fb8a7ce<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/mptable.c<br>@@ -0,0 +1,228 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <arch/smp/mpspec.h><br>+#include <device/pci.h><br>+#include <arch/io.h><br>+#include <arch/ioapic.h><br>+#include <string.h><br>+#include <stdint.h><br>+#include <arch/cpu.h><br>+#include <cpu/x86/lapic.h><br>+#include "southbridge/amd/agesa/hudson/hudson.h"<br>+<br>+u8 picr_data[0x54] = {<br>+ 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,<br>+ 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ 0x03,0x04,0x05,0x07<br>+};<br>+u8 intr_data[0x54] = {<br>+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,<br>+ 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ 0x10,0x11,0x12,0x13<br>+};<br>+<br>+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)<br>+{<br>+ mc->mpc_length += length;<br>+ mc->mpc_entry_count++;<br>+}<br>+<br>+static void my_smp_write_bus(struct mp_config_table *mc,<br>+ unsigned char id, const char *bustype)<br>+{<br>+ struct mpc_config_bus *mpc;<br>+ mpc = smp_next_mpc_entry(mc);<br>+ memset(mpc, '\0', sizeof(*mpc));<br>+ mpc->mpc_type = MP_BUS;<br>+ mpc->mpc_busid = id;<br>+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));<br>+ smp_add_mpc_entry(mc, sizeof(*mpc));<br>+}<br>+<br>+static void *smp_write_config_table(void *v)<br>+{<br>+ struct mp_config_table *mc;<br>+ int bus_isa;<br>+ u8 byte;<br>+<br>+ /*<br>+ * By the time this function gets called, the IOAPIC registers<br>+ * have been written so they can be read to get the correct<br>+ * APIC ID and Version<br>+ */<br>+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);<br>+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);<br>+<br>+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);<br>+<br>+ mptable_init(mc, LOCAL_APIC_ADDR);<br>+ memcpy(mc->mpc_oem, "AMD ", 8);<br>+<br>+ smp_write_processors(mc);<br>+<br>+ //mptable_write_buses(mc, NULL, &bus_isa);<br>+ my_smp_write_bus(mc, 0, "PCI ");<br>+ my_smp_write_bus(mc, 1, "PCI ");<br>+ bus_isa = 0x02;<br>+ my_smp_write_bus(mc, bus_isa, "ISA ");<br>+<br>+ /* I/O APICs: APIC ID Version State Address */<br>+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);<br>+<br>+ smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);<br>+ /* PIC IRQ routine */<br>+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {<br>+ outb(byte, 0xC00);<br>+ outb(picr_data[byte], 0xC01);<br>+ }<br>+<br>+ /* APIC IRQ routine */<br>+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {<br>+ outb(byte | 0x80, 0xC00);<br>+ outb(intr_data[byte], 0xC01);<br>+ }<br>+#if 0<br>+ outb(0x0B, 0xCD6);<br>+ outb(0x02, 0xCD7);<br>+<br>+ outb(0x50, 0xCD6);<br>+ outb(0x1F, 0xCD7);<br>+<br>+ outb(0x48, 0xCD6);<br>+ outb(0xF2, 0xCD7);<br>+<br>+ //outb(0xBE, 0xCD6);<br>+ //outb(0x52, 0xCD7);<br>+<br>+ outb(0xED, 0xCD6);<br>+ outb(0x17, 0xCD7);<br>+<br>+ *(volatile u8 *) (0xFED80D00 + 0x31) = 2;<br>+ *(volatile u8 *) (0xFED80D00 + 0x32) = 2;<br>+ *(volatile u8 *) (0xFED80D00 + 0x33) = 2;<br>+ *(volatile u8 *) (0xFED80D00 + 0x34) = 2;<br>+<br>+ *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8;<br>+ *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8;<br>+ *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8;<br>+ *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0;<br>+<br>+ *(volatile u8 *) (0xFED80D00 + 0x6c) = 1;<br>+ *(volatile u8 *) (0xFED80D00 + 0x6E) = 2;<br>+ *(volatile u8 *) (0xFED80D00 + 0x6f) = 2;<br>+<br>+ *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0;<br>+ *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8;<br>+ *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0;<br>+<br>+ *(volatile u8 *) (0xFED80D00 + 0xA6) = 2;<br>+ *(volatile u8 *) (0xFED80100 + 0xA6) = 0;<br>+<br>+ *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8;<br>+#endif<br>+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */<br>+#define IO_LOCAL_INT(type, intr, apicid, pin) \<br>+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));<br>+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);<br>+<br>+ /* PCI interrupts are level triggered, and are<br>+ * associated with a specific bus/device/function tuple.<br>+ */<br>+#define PCI_INT(bus, dev, int_sign, pin) \<br>+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))<br>+<br>+ /* Internal VGA */<br>+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);<br>+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);<br>+<br>+ /* SMBUS */<br>+ PCI_INT(0x0, 0x14, 0x0, 0x10);<br>+<br>+ /* HD Audio */<br>+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);<br>+<br>+ /* USB */<br>+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);<br>+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);<br>+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);<br>+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);<br>+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);<br>+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);<br>+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);<br>+<br>+ /* sata */<br>+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);<br>+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);<br>+<br>+ /* on board NIC & Slot PCIE. */<br>+<br>+ /* PCI slots */<br>+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));<br>+ if (dev && dev->enabled) {<br>+ u8 bus_pci = dev->link_list->secondary;<br>+ /* PCI_SLOT 0. */<br>+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);<br>+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);<br>+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);<br>+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);<br>+<br>+ /* PCI_SLOT 1. */<br>+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);<br>+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);<br>+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);<br>+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);<br>+<br>+ /* PCI_SLOT 2. */<br>+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);<br>+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);<br>+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);<br>+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);<br>+ }<br>+<br>+ /* PCIe Lan*/<br>+ PCI_INT(0x0, 0x06, 0x0, 0x13);<br>+<br>+ /* FCH PCIe PortA */<br>+ PCI_INT(0x0, 0x15, 0x0, 0x10);<br>+ /* FCH PCIe PortB */<br>+ PCI_INT(0x0, 0x15, 0x1, 0x11);<br>+ /* FCH PCIe PortC */<br>+ PCI_INT(0x0, 0x15, 0x2, 0x12);<br>+ /* FCH PCIe PortD */<br>+ PCI_INT(0x0, 0x15, 0x3, 0x13);<br>+<br>+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */<br>+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);<br>+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);<br>+ /* There is no extension information... */<br>+<br>+ /* Compute the checksums */<br>+ return mptable_finalize(mc);<br>+}<br>+<br>+unsigned long write_smp_table(unsigned long addr)<br>+{<br>+ void *v;<br>+ v = smp_write_floating_table(addr, 0);<br>+ return (unsigned long)smp_write_config_table(v);<br>+}<br>diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c<br>new file mode 100644<br>index 0000000..8190cb7<br>--- /dev/null<br>+++ b/src/mainboard/biostar/a68n_5200/romstage.c<br>@@ -0,0 +1,54 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <stdint.h><br>+#include <string.h><br>+#include <device/pci_def.h><br>+#include <device/pci_ids.h><br>+#include <arch/io.h><br>+#include <arch/stages.h><br>+#include <device/pnp_def.h><br>+#include <console/console.h><br>+#include <commonlib/loglevel.h><br>+#include <northbridge/amd/agesa/state_machine.h><br>+#include <southbridge/amd/agesa/hudson/hudson.h><br>+<br>+void board_BeforeAgesa(struct sysinfo *cb)<br>+{<br>+ int i;<br>+ u32 val;<br>+<br>+ /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for<br>+ * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA<br>+ * even though the register is not documented in the Kabini BKDG.<br>+ * Otherwise the serial output is bad code.<br>+ */<br>+ outb(0xD2, 0xcd6);<br>+ outb(0x00, 0xcd7);<br>+<br>+ /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */<br>+ outb(0xea, 0xcd6);<br>+ outb(0x1, 0xcd7);<br>+<br>+ /* Set LPC decode enables. */<br>+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3);<br>+ pci_write_config32(dev, 0x44, 0xff03ffd5);<br>+<br>+ hudson_lpc_port80();<br>+<br>+ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */<br>+ for (i = 0; i < 200000; i++)<br>+ val = inb(0xcd6);<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21871">change 21871</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21871"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9ccfe014a0e3a70148463fc9f8de02b500fac69e </div>
<div style="display:none"> Gerrit-Change-Number: 21871 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Damien Zammit <damien@zamaudio.com> </div>