<p>Damien Zammit has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21872">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">biostar/a68n_5200: Port to working UART console<br><br>Change-Id: Id44b81345ba189f82413042760d570a746294a1e<br>Signed-off-by: Damien Zammit <damien@zamaudio.com><br>---<br>M src/mainboard/biostar/a68n_5200/Kconfig<br>M src/mainboard/biostar/a68n_5200/devicetree.cb<br>M src/mainboard/biostar/a68n_5200/romstage.c<br>3 files changed, 103 insertions(+), 17 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21872/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig<br>index 55dfb11..53e6870 100644<br>--- a/src/mainboard/biostar/a68n_5200/Kconfig<br>+++ b/src/mainboard/biostar/a68n_5200/Kconfig<br>@@ -2,6 +2,7 @@<br> # This file is part of the coreboot project.<br> #<br> # Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+# Copyright (C) 2016 Edward O'Callaghan <funfunctor@folklore1984.net><br> #<br> # This program is free software; you can redistribute it and/or modify<br> # it under the terms of the GNU General Public License as published by<br>@@ -20,6 +21,7 @@<br> select CPU_AMD_AGESA_FAMILY16_KB<br> select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB<br> select SOUTHBRIDGE_AMD_AGESA_YANGTZE<br>+ select SUPERIO_ITE_IT8728F<br> select HAVE_OPTION_TABLE<br> select HAVE_PIRQ_TABLE<br> select HAVE_MP_TABLE<br>diff --git a/src/mainboard/biostar/a68n_5200/devicetree.cb b/src/mainboard/biostar/a68n_5200/devicetree.cb<br>index a027db9..a9d54d1 100644<br>--- a/src/mainboard/biostar/a68n_5200/devicetree.cb<br>+++ b/src/mainboard/biostar/a68n_5200/devicetree.cb<br>@@ -2,6 +2,7 @@<br> # This file is part of the coreboot project.<br> #<br> # Copyright (C) 2013 Advanced Micro Devices, Inc.<br>+# Copyright (C) 2016 Edward O'Callaghan <funfunctor@folklore1984.net><br> #<br> # This program is free software; you can redistribute it and/or modify<br> # it under the terms of the GNU General Public License as published by<br>@@ -30,9 +31,9 @@<br> device pci 2.0 on end # PCIe Host Bridge<br> device pci 2.1 on end # x4 PCIe slot<br> device pci 2.2 on end # mPCIe slot<br>- device pci 2.3 on end # Realtek NIC<br>- device pci 2.4 on end # Edge Connector<br>- device pci 2.5 on end # Edge Connector<br>+ device pci 2.3 off end # Realtek NIC<br>+ device pci 2.4 off end # Edge Connector<br>+ device pci 2.5 off end # Edge Connector<br> end #chip northbridge/amd/agesa/family16kb<br> <br> chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus<br>@@ -51,8 +52,42 @@<br> end<br> end # SM<br> device pci 14.2 on end # HDA 0x4383<br>- device pci 14.3 on end # LPC 0x439d<br>- device pci 14.7 on end # SD<br>+ device pci 14.3 on # LPC 0x439d<br>+ chip superio/ite/it8728f<br>+ #register "multi_function_register_1" = "0x01"<br>+ device pnp 2e.01 on # COM1<br>+ io 0x60 = 0x3f8<br>+ irq 0x70 = 4<br>+ end<br>+ device pnp 2e.02 off # COM2<br>+ io 0x60 = 0x2f8<br>+ irq 0x70 = 3<br>+ end<br>+ device pnp 2e.03 on # Parallel Port<br>+ io 0x60 = 0x378<br>+ irq 0x70 = 5<br>+ drq 0x74 = 4<br>+ end<br>+ device pnp 2e.04 on # Hardware Monitor<br>+ io 0x60 = 0xa00<br>+ io 0x62 = 0xa20<br>+ irq 0x70 = 0<br>+# XXX<br>+ io 0xf1 = 0x400<br>+ io 0xf3 = 0x0a0<br>+ io 0xf5 = 0x0f0<br>+ io 0xf9 = 0x4a0<br>+# XXX<br>+ end<br>+ device pnp 2e.05 on # KBC<br>+ io 0x60 = 0x060<br>+ end<br>+ device pnp 2e.06 on end # KBC?<br>+ device pnp 2e.07 on end # GPIO XXX<br>+ device pnp 2e.0a off end # IR<br>+ end # ITE IT8728F<br>+ end #LPC<br>+ device pci 14.7 off end # SD<br> end #chip southbridge/amd/agesa/hudson<br> <br> device pci 18.0 on end<br>diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c<br>index 8190cb7..5bca6a5 100644<br>--- a/src/mainboard/biostar/a68n_5200/romstage.c<br>+++ b/src/mainboard/biostar/a68n_5200/romstage.c<br>@@ -2,6 +2,8 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2016 Edward O'Callaghan <funfunctor@folklore1984.net><br>+ * Copyright (C) 2017 Damien Zammit <damien@zamaudio.com><br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -24,29 +26,76 @@<br> #include <commonlib/loglevel.h><br> #include <northbridge/amd/agesa/state_machine.h><br> #include <southbridge/amd/agesa/hudson/hudson.h><br>+#include <superio/ite/common/ite.h><br>+#include <superio/ite/it8728f/it8728f.h><br>+<br>+#define SB_MMIO 0xFED80000<br>+#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))<br>+<br>+#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)<br>+#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)<br>+#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO)<br>+<br>+static void sbxxx_enable_48mhzout(void)<br>+{<br>+ /* most likely programming to 48MHz out signal */<br>+ /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */<br>+ u32 reg32;<br>+ reg32 = SB_MMIO_MISC32(0x28);<br>+ reg32 &= 0xfff8ffff;<br>+ SB_MMIO_MISC32(0x28) = reg32;<br>+<br>+ /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */<br>+ reg32 = SB_MMIO_MISC32(0x40);<br>+ reg32 &= 0xffffbffb;<br>+ SB_MMIO_MISC32(0x40) = reg32;<br>+}<br> <br> void board_BeforeAgesa(struct sysinfo *cb)<br> {<br> int i;<br> u32 val;<br>-<br>- /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for<br>- * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA<br>- * even though the register is not documented in the Kabini BKDG.<br>- * Otherwise the serial output is bad code.<br>- */<br>- outb(0xD2, 0xcd6);<br>- outb(0x00, 0xcd7);<br>-<br>- /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */<br>- outb(0xea, 0xcd6);<br>- outb(0x1, 0xcd7);<br>+ u8 byte;<br> <br> /* Set LPC decode enables. */<br> pci_devfn_t dev = PCI_DEV(0, 0x14, 3);<br> pci_write_config32(dev, 0x44, 0xff03ffd5);<br> <br>+#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)<br>+ hudson_pci_port80();<br>+#endif<br>+#if IS_ENABLED(CONFIG_POST_DEVICE_LPC)<br> hudson_lpc_port80();<br>+#endif<br>+<br>+ /* enable SIO LPC decode */<br>+ byte = pci_read_config8(dev, 0x48);<br>+ byte |= 3; /* 2e, 2f */<br>+ pci_write_config8(dev, 0x48, byte);<br>+<br>+ /* enable serial decode */<br>+ byte = pci_read_config8(dev, 0x44);<br>+ byte |= (1 << 6); /* 0x3f8 */<br>+ pci_write_config8(dev, 0x44, byte);<br>+<br>+ /* Enable the AcpiMmio space */<br>+ outb(0x24, 0xcd6);<br>+ outb(0x1, 0xcd7);<br>+<br>+ /* run ite */<br>+ sbxxx_enable_48mhzout();<br>+ ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);<br>+ ite_kill_watchdog(GPIO_DEV);<br>+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>+<br>+ console_init();<br>+<br>+ /* turn on secondary smbus at b20 */<br>+ outb(0x28, 0xcd6);<br>+ byte = inb(0xcd7);<br>+ byte |= 1;<br>+ outb(byte, 0xcd7);<br>+ printk(BIOS_DEBUG, "Console inited!\n");<br> <br> /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */<br> for (i = 0; i < 200000; i++)<br></pre><p>To view, visit <a href="https://review.coreboot.org/21872">change 21872</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21872"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id44b81345ba189f82413042760d570a746294a1e </div>
<div style="display:none"> Gerrit-Change-Number: 21872 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Damien Zammit <damien@zamaudio.com> </div>