<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21864">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Update Flex Ratio from MSR<br><br>Read back from MSR to apply Flex Ratio into FSP.<br><br>TEST=Apply the patch and test to be able to boot up into OS.<br><br>Change-Id: Iadd4068bd7076b2f097ffe2e2ed87520b9c4c809<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>1 file changed, 14 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21864/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c<br>index 1775cae..466885a 100644<br>--- a/src/soc/intel/cannonlake/romstage/romstage.c<br>+++ b/src/soc/intel/cannonlake/romstage/romstage.c<br>@@ -18,11 +18,13 @@<br> #include <assert.h><br> #include <chip.h><br> #include <cpu/x86/mtrr.h><br>+#include <cpu/x86/msr.h><br> #include <cbmem.h><br> #include <console/console.h><br> #include <fsp/util.h><br> #include <intelblocks/pmclib.h><br> #include <memory_info.h><br>+#include <soc/msr.h><br> #include <soc/pci_devs.h><br> #include <soc/pm.h><br> #include <soc/romstage.h><br>@@ -66,6 +68,16 @@<br>         run_postcar_phase(&pcf);<br> }<br> <br>+static void cpu_flex_override(FSP_M_CONFIG *m_cfg)<br>+{<br>+ msr_t flex_ratio;<br>+    /*<br>+    * Set cpuratio to that value to intended flex ratio.<br>+         */<br>+  flex_ratio = rdmsr(MSR_FLEX_RATIO);<br>+  m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;<br>+}<br>+<br> static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)<br> {<br>      unsigned int i;<br>@@ -86,8 +98,8 @@<br>    m_cfg->PcieRpEnableMask = mask;<br>    m_cfg->PrmrrSize = config->PrmrrSize;<br>   m_cfg->EnableC6Dram = config->enable_c6dram;<br>-   /* Disable Cpu Ratio Override temporary. */<br>-  m_cfg->CpuRatio = 0;<br>+<br>+   cpu_flex_override(m_cfg);<br> }<br> <br> void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)<br></pre><p>To view, visit <a href="https://review.coreboot.org/21864">change 21864</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21864"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iadd4068bd7076b2f097ffe2e2ed87520b9c4c809 </div>
<div style="display:none"> Gerrit-Change-Number: 21864 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>