<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21860">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add all the SOC level DSDT tables<br><br>Add all the SOC level DSDT tables.<br><br>Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>A src/soc/intel/cannonlake/acpi/ipu.asl<br>A src/soc/intel/cannonlake/acpi/lpc.asl<br>A src/soc/intel/cannonlake/acpi/pch_hda.asl<br>A src/soc/intel/cannonlake/acpi/platform.asl<br>A src/soc/intel/cannonlake/acpi/serialio.asl<br>A src/soc/intel/cannonlake/acpi/smbus.asl<br>M src/soc/intel/cannonlake/acpi/southbridge.asl<br>A src/soc/intel/cannonlake/acpi/xhci.asl<br>8 files changed, 634 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/21860/4</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/acpi/ipu.asl b/src/soc/intel/cannonlake/acpi/ipu.asl<br>new file mode 100644<br>index 0000000..d5a2089<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/acpi/ipu.asl<br>@@ -0,0 +1,23 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* IPU3 input system - Device 05, Function 0 */<br>+Device (IMGU)<br>+{<br>+ Name (_ADR, 0x00050000)<br>+ Name (_DDN, "Imaging Unit")<br>+ Name (_CCA, ZERO)<br>+ Name (CAMD, 0x01)<br>+}<br>\ No newline at end of file<br>diff --git a/src/soc/intel/cannonlake/acpi/lpc.asl b/src/soc/intel/cannonlake/acpi/lpc.asl<br>new file mode 100644<br>index 0000000..f1c1bf3<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/acpi/lpc.asl<br>@@ -0,0 +1,117 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+Device (LPCB)<br>+{<br>+ Name (_ADR, 0x001f0000)<br>+ Name (_DDN, "LPC Bus Device")<br>+<br>+ Device (FWH)<br>+ {<br>+ Name (_HID, EISAID ("INT0800"))<br>+ Name (_DDN, "Firmware Hub")<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)<br>+ })<br>+ }<br>+<br>+ Device (HPET)<br>+ {<br>+ Name (_HID, EISAID ("PNP0103"))<br>+ Name (_DDN, "High Precision Event Timer")<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)<br>+ })<br>+ Method (_STA, 0)<br>+ {<br>+ Return (0xf)<br>+ }<br>+ }<br>+<br>+ Device (PIC)<br>+ {<br>+ Name (_HID, EISAID ("PNP0000"))<br>+ Name (_DDN, "8259 Interrupt Controller")<br>+ Name (_CRS, ResourceTemplate()<br>+ {<br>+ IO (Decode16, 0x20, 0x20, 0x01, 0x02)<br>+ IO (Decode16, 0x24, 0x24, 0x01, 0x02)<br>+ IO (Decode16, 0x28, 0x28, 0x01, 0x02)<br>+ IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)<br>+ IO (Decode16, 0x30, 0x30, 0x01, 0x02)<br>+ IO (Decode16, 0x34, 0x34, 0x01, 0x02)<br>+ IO (Decode16, 0x38, 0x38, 0x01, 0x02)<br>+ IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)<br>+ IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)<br>+ IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)<br>+ IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)<br>+ IO (Decode16, 0xac, 0xac, 0x01, 0x02)<br>+ IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)<br>+ IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)<br>+ IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)<br>+ IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)<br>+ IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)<br>+ IRQNoFlags () { 2 }<br>+ })<br>+ }<br>+<br>+ Device (LDRC)<br>+ {<br>+ Name (_HID, EISAID ("PNP0C02"))<br>+ Name (_UID, 2)<br>+ Name (_DDN, "Legacy Device Resources")<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO<br>+ IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO<br>+ IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status<br>+ IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved<br>+ IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved<br>+ IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved<br>+ IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post<br>+ IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved<br>+ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI<br>+ IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,<br>+ 0x1, 0xff)<br>+ })<br>+ }<br>+<br>+ Device (RTC)<br>+ {<br>+ Name (_HID, EISAID ("PNP0B00"))<br>+ Name (_DDN, "Real Time Clock")<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16, 0x70, 0x70, 1, 8)<br>+ })<br>+ }<br>+<br>+ Device (TIMR)<br>+ {<br>+ Name (_HID, EISAID ("PNP0100"))<br>+ Name (_DDN, "8254 Timer")<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16, 0x40, 0x40, 0x01, 0x04)<br>+ IO (Decode16, 0x50, 0x50, 0x10, 0x04)<br>+ IRQNoFlags () {0}<br>+ })<br>+ }<br>+<br>+}<br>diff --git a/src/soc/intel/cannonlake/acpi/pch_hda.asl b/src/soc/intel/cannonlake/acpi/pch_hda.asl<br>new file mode 100644<br>index 0000000..97967ab<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/acpi/pch_hda.asl<br>@@ -0,0 +1,84 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Google Inc.<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* Audio Controller - Device 31, Function 3 */<br>+<br>+Device (HDAS)<br>+{<br>+ Name (_ADR, 0x001f0003)<br>+ Name (_DDN, "Audio Controller")<br>+ Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))<br>+<br>+ /* Device is D3 wake capable */<br>+ Name (_S0W, 3)<br>+<br>+ /* NHLT Table Address populated from GNVS values */<br>+ Name (NBUF, ResourceTemplate () {<br>+ QWordMemory (ResourceConsumer, PosDecode, MinFixed,<br>+ MaxFixed, NonCacheable, ReadOnly,<br>+ 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)<br>+ })<br>+<br>+ /*<br>+ * Device Specific Method<br>+ * Arg0 - UUID<br>+ * Arg1 - Revision<br>+ * Arg2 - Function Index<br>+ */<br>+ Method (_DSM, 4)<br>+ {<br>+ If (LEqual (Arg0, ^UUID)) {<br>+ /*<br>+ * Function 0: Function Support Query<br>+ * Returns a bitmask of functions supported.<br>+ */<br>+ If (LEqual (Arg2, Zero)) {<br>+ /*<br>+ * NHLT Query only supported for revision 1 and<br>+ * if NHLT address and length are set in NVS.<br>+ */<br>+ If (LAnd (LEqual (Arg1, One),<br>+ LAnd (LNotEqual (NHLA, Zero),<br>+ LNotEqual (NHLL, Zero)))) {<br>+ Return (Buffer (One) { 0x03 })<br>+ } Else {<br>+ Return (Buffer (One) { 0x01 })<br>+ }<br>+ }<br>+<br>+ /*<br>+ * Function 1: Query NHLT memory address used by<br>+ * Intel Offload Engine Driver to discover any non-HDA<br>+ * devices that are supported by the DSP.<br>+ *<br>+ * Returns a pointer to NHLT table in memory.<br>+ */<br>+ If (LEqual (Arg2, One)) {<br>+ CreateQWordField (NBUF, ^NHLT._MIN, NBAS)<br>+ CreateQWordField (NBUF, ^NHLT._MAX, NMAS)<br>+ CreateQWordField (NBUF, ^NHLT._LEN, NLEN)<br>+<br>+ Store (NHLA, NBAS)<br>+ Store (NHLA, NMAS)<br>+ Store (NHLL, NLEN)<br>+<br>+ Return (NBUF)<br>+ }<br>+ }<br>+<br>+ Return (Buffer (One) { 0x00 })<br>+ }<br>+}<br>diff --git a/src/soc/intel/cannonlake/acpi/platform.asl b/src/soc/intel/cannonlake/acpi/platform.asl<br>new file mode 100644<br>index 0000000..17a19d9<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/acpi/platform.asl<br>@@ -0,0 +1,66 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* Enable ACPI _SWS methods */<br>+#include <soc/intel/common/acpi/acpi_wake_source.asl><br>+<br>+/* The APM port can be used for generating software SMIs */<br>+<br>+OperationRegion (APMP, SystemIO, 0xb2, 2)<br>+Field (APMP, ByteAcc, NoLock, Preserve)<br>+{<br>+ APMC, 8, // APM command<br>+ APMS, 8 // APM status<br>+}<br>+<br>+/* Port 80 POST */<br>+<br>+OperationRegion (POST, SystemIO, 0x80, 1)<br>+Field (POST, ByteAcc, Lock, Preserve)<br>+{<br>+ DBG0, 8<br>+}<br>+<br>+/*<br>+ * The _PIC method is called by the OS to choose between interrupt<br>+ * routing via the i8259 interrupt controller or the APIC.<br>+ *<br>+ * _PIC is called with a parameter of 0 for i8259 configuration and<br>+ * with a parameter of 1 for Local Apic/IOAPIC configuration.<br>+ */<br>+<br>+Method (_PIC, 1)<br>+{<br>+ /* Remember the OS' IRQ routing choice. */<br>+ Store (Arg0, PICM)<br>+}<br>+<br>+/*<br>+ * The _PTS method (Prepare To Sleep) is called before the OS is<br>+ * entering a sleep state. The sleep state number is passed in Arg0<br>+ */<br>+<br>+Method (_PTS, 1)<br>+{<br>+}<br>+<br>+/* The _WAK method is called on system wakeup */<br>+<br>+Method (_WAK, 1)<br>+{<br>+ Return (Package (){ 0, 0 })<br>+}<br>diff --git a/src/soc/intel/cannonlake/acpi/serialio.asl b/src/soc/intel/cannonlake/acpi/serialio.asl<br>new file mode 100644<br>index 0000000..0a9b15c<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/acpi/serialio.asl<br>@@ -0,0 +1,89 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Google Inc.<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* Intel Serial IO Devices */<br>+<br>+Device (I2C0)<br>+{<br>+ Name (_ADR, 0x00150000)<br>+ Name (_DDN, "Serial IO I2C Controller 0")<br>+}<br>+<br>+Device (I2C1)<br>+{<br>+ Name (_ADR, 0x00150001)<br>+ Name (_DDN, "Serial IO I2C Controller 1")<br>+}<br>+<br>+Device (I2C2)<br>+{<br>+ Name (_ADR, 0x00150002)<br>+ Name (_DDN, "Serial IO I2C Controller 2")<br>+}<br>+<br>+Device (I2C3)<br>+{<br>+ Name (_ADR, 0x00150003)<br>+ Name (_DDN, "Serial IO I2C Controller 3")<br>+}<br>+<br>+Device (I2C4)<br>+{<br>+ Name (_ADR, 0x00190000)<br>+ Name (_DDN, "Serial IO I2C Controller 4")<br>+}<br>+<br>+Device (I2C5)<br>+{<br>+ Name (_ADR, 0x00190001)<br>+ Name (_DDN, "Serial IO I2C Controller 5")<br>+}<br>+<br>+Device (SPI0)<br>+{<br>+ Name (_ADR, 0x001e0002)<br>+ Name (_DDN, "Serial IO SPI Controller 0")<br>+}<br>+<br>+Device (SPI1)<br>+{<br>+ Name (_ADR, 0x001e0003)<br>+ Name (_DDN, "Serial IO SPI Controller 1")<br>+}<br>+<br>+Device (SPI2)<br>+{<br>+ Name (_ADR, 0x00120006)<br>+ Name (_DDN, "Serial IO SPI Controller 2")<br>+}<br>+<br>+Device (UAR0)<br>+{<br>+ Name (_ADR, 0x001e0000)<br>+ Name (_DDN, "Serial IO UART Controller 0")<br>+}<br>+<br>+Device (UAR1)<br>+{<br>+ Name (_ADR, 0x001e0001)<br>+ Name (_DDN, "Serial IO UART Controller 1")<br>+}<br>+<br>+Device (UAR2)<br>+{<br>+ Name (_ADR, 0x00190002)<br>+ Name (_DDN, "Serial IO UART Controller 2")<br>+}<br>diff --git a/src/soc/intel/cannonlake/acpi/smbus.asl b/src/soc/intel/cannonlake/acpi/smbus.asl<br>new file mode 100644<br>index 0000000..cd5ba2c<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/acpi/smbus.asl<br>@@ -0,0 +1,23 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+// Intel SMBus Controller 0:1f.4<br>+<br>+Device (SBUS)<br>+{<br>+ Name (_ADR, 0x001f0004)<br>+}<br>diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl<br>index 408c31b..fdba171 100644<br>--- a/src/soc/intel/cannonlake/acpi/southbridge.asl<br>+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl<br>@@ -27,3 +27,21 @@<br> <br> /* GPIO controller */<br> #include "gpio.asl"<br>+<br>+/* LPC 0:1f.0 */<br>+#include "lpc.asl"<br>+<br>+/* PCH HDA */<br>+#include "pch_hda.asl"<br>+<br>+/* Serial IO */<br>+#include "serialio.asl"<br>+<br>+/* SMBus 0:1f.3 */<br>+#include "smbus.asl"<br>+<br>+/* USB XHCI 0:14.0 */<br>+#include "xhci.asl"<br>+<br>+/* PCI _OSC */<br>+#include <soc/intel/common/acpi/pci_osc.asl><br>diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl<br>new file mode 100644<br>index 0000000..93acb40<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/acpi/xhci.asl<br>@@ -0,0 +1,214 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ * Copyright (C) 2015 Google Inc.<br>+ * Copyright (C) 2015 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/*<br>+ * USB Port Wake Enable (UPWE) on usb attach/detach<br>+ * Arg0 - Port Number<br>+ * Arg1 - Port 1 Status and control offset<br>+ * Arg2 - xHCI Memory-mapped address<br>+ */<br>+Method (UPWE, 3, Serialized)<br>+{<br>+ /* Local0 = Arg1 + ((Arg0 - 1) * 0x10) */<br>+ Add (Arg1, Multiply (Subtract (Arg0, 1), 0x10), Local0)<br>+<br>+ /* Map ((XMEM << 16) + Local0 in PSCR */<br>+ OperationRegion (PSCR, SystemMemory,<br>+ Add (ShiftLeft (Arg2, 16), Local0), 0x10)<br>+ Field (PSCR, AnyAcc, NoLock, Preserve)<br>+ {<br>+ , 25,<br>+ UPCE, 1,<br>+ UPDE, 1,<br>+ }<br>+ Store (One, UPCE)<br>+ Store (One, UPDE)<br>+}<br>+<br>+/*<br>+ * USB Wake Enable Setup (UWES)<br>+ * Arg0 - Port enable bitmap<br>+ * Arg1 - Port 1 Status and control offset<br>+ * Arg2 - xHCI Memory-mapped address<br>+ */<br>+Method (UWES, 3, Serialized)<br>+{<br>+ Store (Arg0, Local0)<br>+<br>+ While (One) {<br>+ FindSetRightBit (Local0, Local1)<br>+ If (LEqual (Local1, Zero)) {<br>+ Break<br>+ }<br>+ UPWE (Local1, Arg1, Arg2)<br>+ /*<br>+ * Clear the lowest set bit in Local0 since it was<br>+ * processed.<br>+ * Local0 = Local0 & (Local0 - 1)<br>+ */<br>+ And (Local0, Subtract (Local0, 1), Local0)<br>+ }<br>+}<br>+<br>+/* XHCI Controller 0:14.0 */<br>+<br>+Device (XHCI)<br>+{<br>+ Name (_ADR, 0x00140000)<br>+<br>+ Name (_PRW, Package () { GPE0_PME_B0, 3 })<br>+<br>+ Method (_DSW, 3)<br>+ {<br>+ Store (Arg0, PMEE)<br>+ UWES (And (\U2WE, 0x3FF), 0x480, XMEM)<br>+ UWES (And (\U3WE, 0x3F), 0x540, XMEM)<br>+ }<br>+<br>+ Name (_S3D, 3) /* D3 supported in S3 */<br>+ Name (_S4D, 3) /* D3 supported in S4 */<br>+ Name (_S0W, 3) /* D3 can wake device in S0 */<br>+ Name (_S3W, 3) /* D3 can wake system from S3 */<br>+ Name (_S4W, 3) /* D3 can wake system from S4 */<br>+<br>+ OperationRegion (XPRT, PCI_Config, 0x00, 0x100)<br>+ Field (XPRT, AnyAcc, NoLock, Preserve)<br>+ {<br>+ Offset (0x0),<br>+ DVID, 16, /* VENDORID */<br>+ Offset (0x10),<br>+ , 16,<br>+ XMEM, 16, /* MEM_BASE */<br>+ Offset (0x50), /* XHCLKGTEN */<br>+ , 2,<br>+ STGE, 1, /* SS Link Trunk clock gating enable */<br>+ Offset (0x74),<br>+ D0D3, 2, /* POWERSTATE */<br>+ , 6,<br>+ PMEE, 1, /* PME_EN */<br>+ , 6,<br>+ PMES, 1, /* PME_STS */<br>+ Offset (0xA2),<br>+ , 2,<br>+ D3HE, 1, /* D3_hot_en */<br>+ }<br>+<br>+ OperationRegion (XREG, SystemMemory,<br>+ Add (ShiftLeft (XMEM, 16), 0x8000), 0x200)<br>+ Field (XREG, DWordAcc, Lock, Preserve)<br>+ {<br>+ Offset (0x1c4), /* USB2PMCTRL */<br>+ , 2,<br>+ UPSW, 2, /* U2PSUSPGP */<br>+ }<br>+<br>+ Method (_PSC, 0, Serialized)<br>+ {<br>+ Return (^D0D3)<br>+ }<br>+<br>+ Method (_PS0, 0, Serialized)<br>+ {<br>+ If (LEqual (^DVID, 0xFFFF)) {<br>+ Return<br>+ }<br>+ If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {<br>+ Return<br>+ }<br>+<br>+ /* Disable d3hot and SS link trunk clock gating */<br>+ Store(Zero, ^D3HE)<br>+ Store(Zero, ^STGE)<br>+<br>+ /* If device is in D3, set back to D0 */<br>+ If (LEqual (^D0D3, 3)) {<br>+ Store (Zero, Local0)<br>+ Store (Local0, ^D0D3)<br>+ Store (^D0D3, Local0)<br>+ }<br>+<br>+ /* Disable USB2 PHY SUS Well Power Gating */<br>+ Store (Zero, ^UPSW)<br>+ }<br>+<br>+ Method (_PS3, 0, Serialized)<br>+ {<br>+ If (LEqual (^DVID, 0xFFFF)) {<br>+ Return<br>+ }<br>+ If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {<br>+ Return<br>+ }<br>+<br>+ /* Clear PME Status */<br>+ Store (1, ^PMES)<br>+<br>+ /* Enable PME */<br>+ Store (1, ^PMEE)<br>+<br>+ /* If device is in D3, set back to D0 */<br>+ If (LEqual (^D0D3, 3)) {<br>+ Store (Zero, Local0)<br>+ Store (Local0, ^D0D3)<br>+ Store (^D0D3, Local0)<br>+ }<br>+<br>+ /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */<br>+ Store (3, ^UPSW)<br>+<br>+ /* Enable d3hot and SS link trunk clock gating */<br>+ Store(One, ^D3HE)<br>+ Store(One, ^STGE)<br>+<br>+ /* Now put device in D3 */<br>+ Store (3, Local0)<br>+ Store (Local0, ^D0D3)<br>+ Store (^D0D3, Local0)<br>+ }<br>+<br>+ /* Root Hub for Cannonlake-LP PCH */<br>+ Device (RHUB)<br>+ {<br>+ Name (_ADR, Zero)<br>+<br>+ /* USB2 */<br>+ Device (HS01) { Name (_ADR, 1) }<br>+ Device (HS02) { Name (_ADR, 2) }<br>+ Device (HS03) { Name (_ADR, 3) }<br>+ Device (HS04) { Name (_ADR, 4) }<br>+ Device (HS05) { Name (_ADR, 5) }<br>+ Device (HS06) { Name (_ADR, 6) }<br>+ Device (HS07) { Name (_ADR, 7) }<br>+ Device (HS08) { Name (_ADR, 8) }<br>+ Device (HS09) { Name (_ADR, 9) }<br>+ Device (HS10) { Name (_ADR, 10) }<br>+ Device (HS11) { Name (_ADR, 11) }<br>+ Device (HS12) { Name (_ADR, 12) }<br>+<br>+ /* USBr */<br>+ Device (USR1) { Name (_ADR, 11) }<br>+ Device (USR2) { Name (_ADR, 12) }<br>+<br>+ /* USB3 */<br>+ Device (SS01) { Name (_ADR, 13) }<br>+ Device (SS02) { Name (_ADR, 14) }<br>+ Device (SS03) { Name (_ADR, 15) }<br>+ Device (SS04) { Name (_ADR, 16) }<br>+ Device (SS05) { Name (_ADR, 17) }<br>+ Device (SS06) { Name (_ADR, 18) }<br>+ }<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21860">change 21860</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21860"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
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<div style="display:none"> Gerrit-Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9 </div>
<div style="display:none"> Gerrit-Change-Number: 21860 </div>
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