<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21847">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/gm45: Remove UMA alignment optimization<br><br>This code path was only triggered in one corner case: GFX UMA set to<br>48MiB. It created a hole below UMA to save MTRRs. But, this hole was<br>never accounted for when calculating cbmem_top(). Instead of trying<br>to fix it, remove it, it's not worth the trouble.<br><br>Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/northbridge/intel/gm45/northbridge.c<br>M src/northbridge/intel/gm45/raminit.c<br>2 files changed, 3 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/21847/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c<br>index 3cb7d11..8215979 100644<br>--- a/src/northbridge/intel/gm45/northbridge.c<br>+++ b/src/northbridge/intel/gm45/northbridge.c<br>@@ -71,7 +71,7 @@<br> static void mch_domain_read_resources(device_t dev)<br> {<br>         u64 tom, touud;<br>-      u32 tomk, tolud, uma_sizek = 0, usable_tomk;<br>+ u32 tomk, tolud, uma_sizek = 0;<br>       u32 pcie_config_base, pcie_config_size;<br> <br>    /* Total Memory 2GB example:<br>@@ -130,16 +130,12 @@<br>           uma_sizek = gms_sizek + gsm_sizek;<br>    }<br> <br>- usable_tomk = ALIGN_DOWN(tomk, 64 << 10);<br>-      if (tomk - usable_tomk > (16 << 10))<br>-                usable_tomk = tomk;<br>-<br>-       printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10);<br>+   printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);<br> <br>        /* Report the memory regions */<br>       ram_resource(dev, 3, 0, legacy_hole_base_k);<br>  ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,<br>-                     (usable_tomk - (legacy_hole_base_k + legacy_hole_size_k)));<br>+                  (tomk - (legacy_hole_base_k + legacy_hole_size_k)));<br> <br>  /*<br>     * If >= 4GB installed then memory from TOLUD to 4GB<br>diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c<br>index d2da3b0..a44e397 100644<br>--- a/src/northbridge/intel/gm45/raminit.c<br>+++ b/src/northbridge/intel/gm45/raminit.c<br>@@ -1241,10 +1241,6 @@<br>                      printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);<br> <br>                     uma_sizem = (gms_sizek + gsm_sizek) >> 10;<br>-                     /* Further reduce MTRR usage if it costs use less than<br>-                          16 MiB.  */<br>-                       if (ALIGN_UP(uma_sizem, 64) - uma_sizem <= 16)<br>-                            uma_sizem = ALIGN_UP(uma_sizem, 64);<br>          }<br>     }<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/21847">change 21847</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21847"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d </div>
<div style="display:none"> Gerrit-Change-Number: 21847 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>