<p>Vagiz Tarkhanov has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21846">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard: Add Gigabyte GA-Z77-DS3H support<br><br>What was tested: native ram and vga init, booting, suspend/resume, pcie<br>and pci slots, video, audio, COM port, PS/2 keyboard, virtualization,<br>pci pass-through, one out of two EHCI controllers, xHCI, fan and thermal<br>sensors in superio.<br><br>There is one remanining issue:<br>EHCI is buggy. With my Wacom tablet attached GRUB registers phantom key<br>presses, but in Linux the tablet works fine. Also, in Linux if a keyboard<br>and a mouse attached simultaneously, the mouse is unresponsive.<br>Workaround: attach mice and/or keyboards to xHCI because xHCI is stable.<br><br>This commit depends on the ability to set temperature offsets and limits<br>in ite superio.<br><br>Change-Id: I90fef8b7a1181c2f6481e834d1aa342905b85f1e<br>Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org><br>---<br>A src/mainboard/gigabyte/ga-z77-ds3h/Kconfig<br>A src/mainboard/gigabyte/ga-z77-ds3h/Kconfig.name<br>A src/mainboard/gigabyte/ga-z77-ds3h/Makefile.inc<br>A src/mainboard/gigabyte/ga-z77-ds3h/acpi/ec.asl<br>A src/mainboard/gigabyte/ga-z77-ds3h/acpi/mainboard.asl<br>A src/mainboard/gigabyte/ga-z77-ds3h/acpi/platform.asl<br>A src/mainboard/gigabyte/ga-z77-ds3h/acpi/superio.asl<br>A src/mainboard/gigabyte/ga-z77-ds3h/acpi/thermal.asl<br>A src/mainboard/gigabyte/ga-z77-ds3h/acpi/video.asl<br>A src/mainboard/gigabyte/ga-z77-ds3h/acpi_tables.c<br>A src/mainboard/gigabyte/ga-z77-ds3h/board_info.txt<br>A src/mainboard/gigabyte/ga-z77-ds3h/cmos.default<br>A src/mainboard/gigabyte/ga-z77-ds3h/cmos.layout<br>A src/mainboard/gigabyte/ga-z77-ds3h/devicetree.cb<br>A src/mainboard/gigabyte/ga-z77-ds3h/dsdt.asl<br>A src/mainboard/gigabyte/ga-z77-ds3h/gma-mainboard.ads<br>A src/mainboard/gigabyte/ga-z77-ds3h/gpio.c<br>A src/mainboard/gigabyte/ga-z77-ds3h/hda_verb.c<br>A src/mainboard/gigabyte/ga-z77-ds3h/mainboard.c<br>A src/mainboard/gigabyte/ga-z77-ds3h/romstage.c<br>A src/mainboard/gigabyte/ga-z77-ds3h/thermal.h<br>21 files changed, 1,251 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/21846/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/Kconfig b/src/mainboard/gigabyte/ga-z77-ds3h/Kconfig<br>new file mode 100644<br>index 0000000..3cd99ac<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/Kconfig<br>@@ -0,0 +1,67 @@<br>+if BOARD_GIGABYTE_GA_Z77_DS3H<br>+<br>+config BOARD_SPECIFIC_OPTIONS<br>+ def_bool y<br>+ select ARCH_X86<br>+ select CPU_INTEL_SOCKET_LGA1155<br>+ select NORTHBRIDGE_INTEL_IVYBRIDGE<br>+ select USE_NATIVE_RAMINIT<br>+ select SOUTHBRIDGE_INTEL_C216<br>+ select SUPERIO_ITE_IT8728F<br>+ select BOARD_ROMSIZE_KB_8192<br>+ select HAVE_ACPI_TABLES<br>+ select HAVE_OPTION_TABLE<br>+ select HAVE_CMOS_DEFAULT<br>+ select HAVE_ACPI_RESUME<br>+ select HAVE_SMI_HANDLER<br>+ select INTEL_INT15<br>+ select SERIRQ_CONTINUOUS_MODE<br>+ select MAINBOARD_HAS_LIBGFXINIT<br>+ select MAINBOARD_HAS_LPC_TPM<br>+ select TPM<br>+<br>+config DRAM_RESET_GATE_GPIO<br>+ int<br>+ default 25<br>+<br>+config USBDEBUG_HCD_INDEX<br>+ int<br>+ default 2<br>+<br>+config MAINBOARD_DIR<br>+ string<br>+ default gigabyte/ga-z77-ds3h<br>+<br>+config MAINBOARD_PART_NUMBER<br>+ string<br>+ default "GA-Z77-DS3H"<br>+<br>+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID<br>+ hex<br>+ default 0x5001<br>+<br>+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID<br>+ hex<br>+ default 0x1458<br>+<br>+config MAX_CPUS<br>+ int<br>+ default 8<br>+<br>+config HAVE_IFD_BIN<br>+ bool<br>+ default n<br>+<br>+config HAVE_ME_BIN<br>+ bool<br>+ default n<br>+<br>+config IFD_BIOS_SECTION<br>+ string<br>+ default "0x00300000:0x007fffff"<br>+<br>+config IFD_ME_SECTION<br>+ string<br>+ default "0x00001000:0x002fffff"<br>+<br>+endif # BOARD_GIGABYTE_GA_Z77_DS3H<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/Kconfig.name b/src/mainboard/gigabyte/ga-z77-ds3h/Kconfig.name<br>new file mode 100644<br>index 0000000..65b3f3f<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/Kconfig.name<br>@@ -0,0 +1,2 @@<br>+config BOARD_GIGABYTE_GA_Z77_DS3H<br>+ bool "GA-Z77-DS3H"<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/Makefile.inc b/src/mainboard/gigabyte/ga-z77-ds3h/Makefile.inc<br>new file mode 100644<br>index 0000000..a8846b6<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/Makefile.inc<br>@@ -0,0 +1,18 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+romstage-y += gpio.c<br>+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads<br>+<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/ec.asl<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/ec.asl<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/mainboard.asl<br>new file mode 100644<br>index 0000000..34de86f<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/mainboard.asl<br>@@ -0,0 +1,23 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+Scope (\_SB)<br>+{<br>+ Device (PWRB)<br>+ {<br>+ Name (_HID, EisaId("PNP0C0C"))<br>+ }<br>+}<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/platform.asl<br>new file mode 100644<br>index 0000000..0603164<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/platform.asl<br>@@ -0,0 +1,30 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* The _PTS method (Prepare To Sleep) is called before the OS is<br>+ * entering a sleep state. The sleep state number is passed in Arg0<br>+ */<br>+<br>+Method(_PTS,1)<br>+{<br>+<br>+}<br>+<br>+/* The _WAK method is called on system wakeup */<br>+<br>+Method(_WAK,1)<br>+{<br>+ Return(Package(){0,0})<br>+}<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/superio.asl<br>new file mode 100644<br>index 0000000..78bf687<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/superio.asl<br>@@ -0,0 +1,19 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* mainboard configuration */<br>+<br>+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard<br>+#define SIO_ENABLE_PS2M // Enable PS/2 Mouse<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/thermal.asl<br>new file mode 100644<br>index 0000000..61ea07c<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/thermal.asl<br>@@ -0,0 +1,61 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+// Thermal Zone<br>+<br>+Scope (\_TZ)<br>+{<br>+ ThermalZone (THRM)<br>+ {<br>+ Name (_TC1, 0x02)<br>+ Name (_TC2, 0x03)<br>+<br>+ // Thermal zone polling frequency: 2 seconds<br>+ Name (_TZP, 20)<br>+<br>+ // Thermal sampling period for passive cooling: 2 seconds<br>+ Name (_TSP, 20)<br>+<br>+ // Convert from Degrees C to 1/10 Kelvin for ACPI<br>+ Method (CTOK, 1)<br>+ {<br>+ // 10th of Degrees C<br>+ Multiply (Arg0, 10, Local0)<br>+<br>+ // Convert to Kelvin<br>+ Add (Local0, 2732, Local0)<br>+<br>+ Return (Local0)<br>+ }<br>+<br>+ // Threshold for OS to shutdown<br>+ Method (_CRT, 0, Serialized)<br>+ {<br>+ Return (CTOK (\TCRT))<br>+ }<br>+<br>+ // Threshold for passive cooling<br>+ Method (_PSV, 0, Serialized)<br>+ {<br>+ Return (CTOK (\TPSV))<br>+ }<br>+<br>+ // Processors used for passive cooling<br>+ Method (_PSL, 0, Serialized)<br>+ {<br>+ Return (\PPKG ())<br>+ }<br>+ }<br>+}<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi/video.asl b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/video.asl<br>new file mode 100644<br>index 0000000..f87af3c<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/video.asl<br>@@ -0,0 +1 @@<br>+// Blank<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi_tables.c b/src/mainboard/gigabyte/ga-z77-ds3h/acpi_tables.c<br>new file mode 100644<br>index 0000000..532242f<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi_tables.c<br>@@ -0,0 +1,53 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <types.h><br>+#include <string.h><br>+#include <cbmem.h><br>+#include <console/console.h><br>+#include <arch/acpi.h><br>+#include <arch/ioapic.h><br>+#include <arch/acpigen.h><br>+#include <arch/smp/mpspec.h><br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <device/pci_ids.h><br>+#include <southbridge/intel/bd82x6x/pch.h><br>+#include <southbridge/intel/bd82x6x/nvs.h><br>+#include "thermal.h"<br>+<br>+static void acpi_update_thermal_table(global_nvs_t *gnvs)<br>+{<br>+ gnvs->tcrt = CRITICAL_TEMPERATURE;<br>+ gnvs->tpsv = PASSIVE_TEMPERATURE;<br>+}<br>+<br>+void acpi_create_gnvs(global_nvs_t *gnvs)<br>+{<br>+ memset((void *)gnvs, 0, sizeof(*gnvs));<br>+<br>+ /* Disable USB ports in S3 by default */<br>+ gnvs->s3u0 = 0;<br>+ gnvs->s3u1 = 0;<br>+<br>+ /* Disable USB ports in S5 by default */<br>+ gnvs->s5u0 = 0;<br>+ gnvs->s5u1 = 0;<br>+<br>+ // the lid is open by default.<br>+ gnvs->lids = 1;<br>+<br>+ acpi_update_thermal_table(gnvs);<br>+}<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/board_info.txt b/src/mainboard/gigabyte/ga-z77-ds3h/board_info.txt<br>new file mode 100644<br>index 0000000..fc1c7e1<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/board_info.txt<br>@@ -0,0 +1,7 @@<br>+Category: desktop<br>+Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4147#sp<br>+ROM package: SOIC-8<br>+ROM protocol: SPI<br>+ROM socketed: n<br>+Flashrom support: y<br>+Release year: 2012<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/cmos.default b/src/mainboard/gigabyte/ga-z77-ds3h/cmos.default<br>new file mode 100644<br>index 0000000..767372c<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/cmos.default<br>@@ -0,0 +1,8 @@<br>+boot_option=Fallback<br>+baud_rate=115200<br>+debug_level=Spew<br>+power_on_after_fail=Enable<br>+nmi=Enable<br>+volume=0x3<br>+sata_mode=AHCI<br>+hyper_threading=Enable<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/cmos.layout b/src/mainboard/gigabyte/ga-z77-ds3h/cmos.layout<br>new file mode 100644<br>index 0000000..ebc7c42<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/cmos.layout<br>@@ -0,0 +1,125 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2007-2008 coresystems GmbH<br>+## Copyright (C) 2014 Vladimir Serbinenko<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+# -----------------------------------------------------------------<br>+entries<br>+<br>+# -----------------------------------------------------------------<br>+# Status Register A<br>+# -----------------------------------------------------------------<br>+# Status Register B<br>+# -----------------------------------------------------------------<br>+# Status Register C<br>+#96 4 r 0 status_c_rsvd<br>+#100 1 r 0 uf_flag<br>+#101 1 r 0 af_flag<br>+#102 1 r 0 pf_flag<br>+#103 1 r 0 irqf_flag<br>+# -----------------------------------------------------------------<br>+# Status Register D<br>+#104 7 r 0 status_d_rsvd<br>+#111 1 r 0 valid_cmos_ram<br>+# -----------------------------------------------------------------<br>+# Diagnostic Status Register<br>+#112 8 r 0 diag_rsvd1<br>+<br>+# -----------------------------------------------------------------<br>+0 120 r 0 reserved_memory<br>+#120 264 r 0 unused<br>+<br>+# -----------------------------------------------------------------<br>+# RTC_BOOT_BYTE (coreboot hardcoded)<br>+384 1 e 4 boot_option<br>+388 4 h 0 reboot_counter<br>+#390 2 r 0 unused?<br>+<br>+# -----------------------------------------------------------------<br>+# coreboot config options: console<br>+392 3 e 5 baud_rate<br>+395 4 e 6 debug_level<br>+#399 1 r 0 unused<br>+<br>+400 8 h 0 volume<br>+<br>+# coreboot config options: southbridge<br>+408 1 e 1 nmi<br>+409 2 e 7 power_on_after_fail<br>+<br>+#411 10 r 0 unused<br>+421 1 e 9 sata_mode<br>+#422 2 r 0 unused<br>+<br>+# coreboot config options: cpu<br>+424 1 e 2 hyper_threading<br>+#425 7 r 0 unused<br>+<br>+# coreboot config options: northbridge<br>+432 3 e 11 gfx_uma_size<br>+#435 549 r 0 unused<br>+<br>+# SandyBridge MRC Scrambler Seed values<br>+896 32 r 0 mrc_scrambler_seed<br>+928 32 r 0 mrc_scrambler_seed_s3<br>+960 16 r 0 mrc_scrambler_seed_chk<br>+<br>+# coreboot config options: check sums<br>+984 16 h 0 check_sum<br>+<br>+# -----------------------------------------------------------------<br>+<br>+enumerations<br>+<br>+#ID value text<br>+1 0 Disable<br>+1 1 Enable<br>+2 0 Enable<br>+2 1 Disable<br>+4 0 Fallback<br>+4 1 Normal<br>+5 0 115200<br>+5 1 57600<br>+5 2 38400<br>+5 3 19200<br>+5 4 9600<br>+5 5 4800<br>+5 6 2400<br>+5 7 1200<br>+6 1 Emergency<br>+6 2 Alert<br>+6 3 Critical<br>+6 4 Error<br>+6 5 Warning<br>+6 6 Notice<br>+6 7 Info<br>+6 8 Debug<br>+6 9 Spew<br>+7 0 Disable<br>+7 1 Enable<br>+7 2 Keep<br>+9 0 AHCI<br>+9 1 IDE<br>+11 0 32M<br>+11 1 64M<br>+11 2 96M<br>+11 3 128M<br>+11 4 160M<br>+11 5 192M<br>+11 6 224M<br>+<br>+# -----------------------------------------------------------------<br>+checksums<br>+<br>+checksum 392 415 984<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/devicetree.cb b/src/mainboard/gigabyte/ga-z77-ds3h/devicetree.cb<br>new file mode 100644<br>index 0000000..b9e9a02<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/devicetree.cb<br>@@ -0,0 +1,176 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2017 Vagiz Tarkhanov <rakkin@autistici.org><br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; either version 2 of the License, or<br>+# (at your option) any later version.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+chip northbridge/intel/sandybridge<br>+ # IGD Displays<br>+ register "gfx.ndid" = "3"<br>+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"<br>+<br>+ device cpu_cluster 0 on<br>+ chip cpu/intel/socket_LGA1155<br>+ device lapic 0 on end<br>+ end<br>+ chip cpu/intel/model_206ax<br>+ register "c1_acpower" = "1"<br>+ register "c2_acpower" = "3"<br>+ register "c3_acpower" = "5"<br>+ register "c1_battery" = "1"<br>+ register "c2_battery" = "3"<br>+ register "c3_battery" = "5"<br>+ # Magic APIC ID to locate this chip<br>+ device lapic 0xACAC off end<br>+ end<br>+ end<br>+<br>+ register "pci_mmio_size" = "2048"<br>+<br>+ device domain 0 on<br>+ subsystemid 0x1458 0x5000 inherit<br>+ device pci 00.0 on # Host Bridge<br>+ subsystemid 0x1458 0x5000<br>+ end<br>+ device pci 01.0 on end # PCIe Bridge for discrete graphics<br>+ device pci 02.0 on # Integrated graphics<br>+ subsystemid 0x1458 0xd000<br>+ end<br>+<br>+ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH<br>+ register "spi_uvscc" = "0x2005"<br>+ register "spi_lvscc" = "0x2005"<br>+ register "alt_gp_smi_en" = "0x0000"<br>+ register "gen1_dec" = "0x003c0a01"<br>+<br>+ # Set max SATA speed to 6.0 Gb/s<br>+ register "sata_port_map" = "0x3f"<br>+ register "sata_interface_speed_support" = "0x3"<br>+<br>+ register "pcie_port_coalesce" = "0"<br>+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"<br>+ register "p_cnt_throttling_supported" = "0"<br>+ register "docking_supported" = "0"<br>+ register "c2_latency" = "0x0065"<br>+<br>+ register "xhci_overcurrent_mapping" = "0x00000c03"<br>+ register "superspeed_capable_ports" = "0x0000000f"<br>+ register "xhci_switchable_ports" = "0x0000000f"<br>+<br>+ device pci 14.0 on # USB 3.0 Controller<br>+ subsystemid 0x1458 0x5007<br>+ end<br>+ device pci 16.0 on end # Management Engine Interface 1<br>+ device pci 16.1 off end # Management Engine Interface 2<br>+ device pci 16.2 off end # Management Engine IDE-R<br>+ device pci 16.3 off end # Management Engine KT<br>+ device pci 19.0 off end # Intel Gigabit Ethernet<br>+ device pci 1a.0 on # USB2 EHCI #2<br>+ subsystemid 0x1458 0x5006<br>+ end<br>+ device pci 1b.0 on # High Definition Audio<br>+ subsystemid 0x1458 0xa002<br>+ end<br>+ device pci 1c.0 on end # PCIe Port #1<br>+ device pci 1c.1 on end # PCIe Port #2<br>+ device pci 1c.2 on # PCIe Port #3, Atheros AR8161 Gbe<br>+ subsystemid 0x1458 0xe000<br>+ end<br>+ device pci 1c.3 on end # PCI Bridge<br>+ device pci 1c.4 on end # PCIe Port #5<br>+ device pci 1c.5 off end # PCIe Port #6<br>+ device pci 1c.6 off end # PCIe Port #7<br>+ device pci 1c.7 off end # PCIe Port #8<br>+ device pci 1d.0 on # USB2 EHCI #1<br>+ subsystemid 0x1458 0x5006<br>+ end<br>+ device pci 1e.0 off end # PCI Bridge<br>+ device pci 1f.0 on # ISA/LPC bridge<br>+ subsystemid 0x1458 0x5001<br>+ chip superio/ite/it8728f<br>+ register "ec.vin_mask" = "VIN_ALL"<br>+ register "TMPIN1" = "THERMAL_RESISTOR"<br>+ register "TMPIN2" = "THERMAL_RESISTOR"<br>+ register "TMPIN3" = "THERMAL_DIODE"<br>+ register "ec.peci_tmpin" = "3"<br>+ # PECI is calculated by substracting from this offset<br>+ register "ec.tmpin[2].offset" = "97"<br>+ # Temperature at which superio raises the alarm<br>+ register "ec.tmpin[2].max" = "85"<br>+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"<br>+ register "FAN1.smart.tmpin" = "3"<br>+ register "FAN1.smart.tmp_off" = "0"<br>+ register "FAN1.smart.tmp_start" = "20"<br>+ register "FAN1.smart.tmp_full" = "60"<br>+ register "FAN1.smart.tmp_delta" = "2"<br>+ register "FAN1.smart.pwm_start" = "50"<br>+ register "FAN1.smart.slope" = "1"<br>+ register "FAN2.mode" = "FAN_SMART_AUTOMATIC"<br>+ register "FAN2.smart.tmpin" = "3"<br>+ register "FAN2.smart.tmp_off" = "0"<br>+ register "FAN2.smart.tmp_start" = "20"<br>+ register "FAN2.smart.tmp_full" = "60"<br>+ register "FAN2.smart.tmp_delta" = "2"<br>+ register "FAN2.smart.pwm_start" = "50"<br>+ register "FAN2.smart.slope" = "1"<br>+ register "FAN3.mode" = "FAN_SMART_AUTOMATIC"<br>+ register "FAN3.smart.tmpin" = "3"<br>+ register "FAN3.smart.tmp_off" = "0"<br>+ register "FAN3.smart.tmp_start" = "20"<br>+ register "FAN3.smart.tmp_full" = "60"<br>+ register "FAN3.smart.tmp_delta" = "2"<br>+ register "FAN3.smart.pwm_start" = "50"<br>+ register "FAN3.smart.slope" = "1"<br>+<br>+ #FIXME: add FAN4<br>+<br>+ device pnp 2e.0 off end # FDC<br>+ device pnp 2e.1 on # Serial Port 1<br>+ io 0x60 = 0x3f8<br>+ irq 0x70 = 4<br>+ end<br>+ device pnp 2e.2 off end # Serial Port 2<br>+ device pnp 2e.3 off end # Parallel Port<br>+ device pnp 2e.4 on # EC<br>+ io 0x60 = 0xa30<br>+ io 0x62 = 0x230<br>+ irq 0x70 = 9<br>+ end<br>+ device pnp 2e.5 on # Keyboard<br>+ io 0x60 = 0x60<br>+ io 0x62 = 0x64<br>+ irq 0x70 = 1<br>+ irq 0xf0 = 8<br>+ end<br>+ device pnp 2e.6 on # Mouse<br>+ irq 0x70 = 12<br>+ end<br>+ device pnp 2e.7 off end # GPIO<br>+ device pnp 2e.a off end # IR<br>+ end<br>+<br>+ chip drivers/pc80/tpm<br>+ device pnp 0c31.0 on end<br>+ end<br>+ end<br>+ device pci 1f.2 on # SATA Controller 1<br>+ subsystemid 0x1458 0xb005<br>+ end<br>+ device pci 1f.3 on # SMBus<br>+ subsystemid 0x1458 0x5001<br>+ end<br>+ device pci 1f.4 off end<br>+ device pci 1f.5 off end # SATA Controller 2<br>+ end<br>+ end<br>+end<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/dsdt.asl b/src/mainboard/gigabyte/ga-z77-ds3h/dsdt.asl<br>new file mode 100644<br>index 0000000..75f2efe<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/dsdt.asl<br>@@ -0,0 +1,29 @@<br>+DefinitionBlock(<br>+ "dsdt.aml",<br>+ "DSDT",<br>+ 0x03, // DSDT revision: ACPI v3.0<br>+ "COREv4", // OEM id<br>+ "COREBOOT", // OEM table id<br>+ 0x20141018 // OEM revision<br>+)<br>+{<br>+ #include <southbridge/intel/bd82x6x/acpi/platform.asl><br>+<br>+ // Some generic macros<br>+ #include "acpi/platform.asl"<br>+ #include <cpu/intel/model_206ax/acpi/cpu.asl><br>+ /* global NVS and variables. */<br>+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl><br>+<br>+ Scope (\_SB) {<br>+ Device (PCI0)<br>+ {<br>+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/pch.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl><br>+<br>+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl><br>+ }<br>+ }<br>+}<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/gma-mainboard.ads b/src/mainboard/gigabyte/ga-z77-ds3h/gma-mainboard.ads<br>new file mode 100644<br>index 0000000..2b88265<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/gma-mainboard.ads<br>@@ -0,0 +1,15 @@<br>+with HW.GFX.GMA;<br>+with HW.GFX.GMA.Display_Probing;<br>+<br>+use HW.GFX.GMA;<br>+use HW.GFX.GMA.Display_Probing;<br>+<br>+private package GMA.Mainboard is<br>+<br>+ ports : constant Port_List :=<br>+ (HDMI1,<br>+ HDMI2,<br>+ Analog,<br>+ others => Disabled);<br>+<br>+end GMA.Mainboard;<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/gpio.c b/src/mainboard/gigabyte/ga-z77-ds3h/gpio.c<br>new file mode 100644<br>index 0000000..3d4342e<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/gpio.c<br>@@ -0,0 +1,434 @@<br>+#include <southbridge/intel/common/gpio.h><br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_mode = {<br>+ .gpio0 = GPIO_MODE_GPIO,<br>+ .gpio1 = GPIO_MODE_GPIO,<br>+ .gpio2 = GPIO_MODE_GPIO,<br>+ .gpio3 = GPIO_MODE_GPIO,<br>+ .gpio4 = GPIO_MODE_GPIO,<br>+ .gpio5 = GPIO_MODE_GPIO,<br>+ .gpio6 = GPIO_MODE_GPIO,<br>+ .gpio7 = GPIO_MODE_GPIO,<br>+ .gpio8 = GPIO_MODE_GPIO,<br>+ .gpio9 = GPIO_MODE_NATIVE,<br>+ .gpio10 = GPIO_MODE_NATIVE,<br>+ .gpio11 = GPIO_MODE_NATIVE,<br>+ .gpio12 = GPIO_MODE_GPIO,<br>+ .gpio13 = GPIO_MODE_GPIO,<br>+ .gpio14 = GPIO_MODE_NATIVE,<br>+ .gpio15 = GPIO_MODE_GPIO,<br>+ .gpio16 = GPIO_MODE_GPIO,<br>+ .gpio17 = GPIO_MODE_GPIO,<br>+ .gpio18 = GPIO_MODE_NATIVE,<br>+ .gpio19 = GPIO_MODE_GPIO,<br>+ .gpio20 = GPIO_MODE_NATIVE,<br>+ .gpio21 = GPIO_MODE_GPIO,<br>+ .gpio22 = GPIO_MODE_GPIO,<br>+ .gpio23 = GPIO_MODE_NATIVE,<br>+ .gpio24 = GPIO_MODE_GPIO,<br>+ .gpio25 = GPIO_MODE_NATIVE,<br>+ .gpio26 = GPIO_MODE_NATIVE,<br>+ .gpio27 = GPIO_MODE_GPIO,<br>+ .gpio28 = GPIO_MODE_GPIO,<br>+ .gpio29 = GPIO_MODE_GPIO,<br>+ .gpio30 = GPIO_MODE_NATIVE,<br>+ .gpio31 = GPIO_MODE_GPIO,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_direction = {<br>+ .gpio0 = GPIO_DIR_INPUT,<br>+ .gpio1 = GPIO_DIR_INPUT,<br>+ .gpio2 = GPIO_DIR_INPUT,<br>+ .gpio3 = GPIO_DIR_INPUT,<br>+ .gpio4 = GPIO_DIR_INPUT,<br>+ .gpio5 = GPIO_DIR_INPUT,<br>+ .gpio6 = GPIO_DIR_INPUT,<br>+ .gpio7 = GPIO_DIR_INPUT,<br>+ .gpio8 = GPIO_DIR_OUTPUT,<br>+ .gpio9 = GPIO_DIR_INPUT,<br>+ .gpio10 = GPIO_DIR_INPUT,<br>+ .gpio11 = GPIO_DIR_INPUT,<br>+ .gpio12 = GPIO_DIR_OUTPUT,<br>+ .gpio13 = GPIO_DIR_INPUT,<br>+ .gpio14 = GPIO_DIR_INPUT,<br>+ .gpio15 = GPIO_DIR_OUTPUT,<br>+ .gpio16 = GPIO_DIR_INPUT,<br>+ .gpio17 = GPIO_DIR_INPUT,<br>+ .gpio18 = GPIO_DIR_INPUT,<br>+ .gpio19 = GPIO_DIR_INPUT,<br>+ .gpio20 = GPIO_DIR_INPUT,<br>+ .gpio21 = GPIO_DIR_INPUT,<br>+ .gpio22 = GPIO_DIR_INPUT,<br>+ .gpio23 = GPIO_DIR_INPUT,<br>+ .gpio24 = GPIO_DIR_OUTPUT,<br>+ .gpio25 = GPIO_DIR_INPUT,<br>+ .gpio26 = GPIO_DIR_INPUT,<br>+ .gpio27 = GPIO_DIR_INPUT,<br>+ .gpio28 = GPIO_DIR_OUTPUT,<br>+ .gpio29 = GPIO_DIR_INPUT,<br>+ .gpio30 = GPIO_DIR_OUTPUT,<br>+ .gpio31 = GPIO_DIR_INPUT,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_level = {<br>+ .gpio0 = GPIO_LEVEL_HIGH,<br>+ .gpio1 = GPIO_LEVEL_HIGH,<br>+ .gpio2 = GPIO_LEVEL_HIGH,<br>+ .gpio3 = GPIO_LEVEL_HIGH,<br>+ .gpio4 = GPIO_LEVEL_HIGH,<br>+ .gpio5 = GPIO_LEVEL_HIGH,<br>+ .gpio6 = GPIO_LEVEL_HIGH,<br>+ .gpio7 = GPIO_LEVEL_HIGH,<br>+ .gpio8 = GPIO_LEVEL_HIGH,<br>+ .gpio9 = GPIO_LEVEL_HIGH,<br>+ .gpio10 = GPIO_LEVEL_HIGH,<br>+ .gpio11 = GPIO_LEVEL_HIGH,<br>+ .gpio12 = GPIO_LEVEL_HIGH,<br>+ .gpio13 = GPIO_LEVEL_HIGH,<br>+ .gpio14 = GPIO_LEVEL_HIGH,<br>+ .gpio15 = GPIO_LEVEL_LOW,<br>+ .gpio16 = GPIO_LEVEL_HIGH,<br>+ .gpio17 = GPIO_LEVEL_HIGH,<br>+ .gpio18 = GPIO_LEVEL_LOW,<br>+ .gpio19 = GPIO_LEVEL_HIGH,<br>+ .gpio20 = GPIO_LEVEL_HIGH,<br>+ .gpio21 = GPIO_LEVEL_HIGH,<br>+ .gpio22 = GPIO_LEVEL_HIGH,<br>+ .gpio23 = GPIO_LEVEL_HIGH,<br>+ .gpio24 = GPIO_LEVEL_LOW,<br>+ .gpio25 = GPIO_LEVEL_LOW,<br>+ .gpio26 = GPIO_LEVEL_LOW,<br>+ .gpio27 = GPIO_LEVEL_HIGH,<br>+ .gpio28 = GPIO_LEVEL_LOW,<br>+ .gpio29 = GPIO_LEVEL_HIGH,<br>+ .gpio30 = GPIO_LEVEL_HIGH,<br>+ .gpio31 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_reset = {<br>+ .gpio0 = GPIO_RESET_PWROK,<br>+ .gpio1 = GPIO_RESET_PWROK,<br>+ .gpio2 = GPIO_RESET_PWROK,<br>+ .gpio3 = GPIO_RESET_PWROK,<br>+ .gpio4 = GPIO_RESET_PWROK,<br>+ .gpio5 = GPIO_RESET_PWROK,<br>+ .gpio6 = GPIO_RESET_PWROK,<br>+ .gpio7 = GPIO_RESET_PWROK,<br>+ .gpio8 = GPIO_RESET_PWROK,<br>+ .gpio9 = GPIO_RESET_PWROK,<br>+ .gpio10 = GPIO_RESET_PWROK,<br>+ .gpio11 = GPIO_RESET_PWROK,<br>+ .gpio12 = GPIO_RESET_PWROK,<br>+ .gpio13 = GPIO_RESET_PWROK,<br>+ .gpio14 = GPIO_RESET_PWROK,<br>+ .gpio15 = GPIO_RESET_PWROK,<br>+ .gpio16 = GPIO_RESET_PWROK,<br>+ .gpio17 = GPIO_RESET_PWROK,<br>+ .gpio18 = GPIO_RESET_PWROK,<br>+ .gpio19 = GPIO_RESET_PWROK,<br>+ .gpio20 = GPIO_RESET_PWROK,<br>+ .gpio21 = GPIO_RESET_PWROK,<br>+ .gpio22 = GPIO_RESET_PWROK,<br>+ .gpio23 = GPIO_RESET_PWROK,<br>+ .gpio24 = GPIO_RESET_RSMRST,<br>+ .gpio25 = GPIO_RESET_PWROK,<br>+ .gpio26 = GPIO_RESET_PWROK,<br>+ .gpio27 = GPIO_RESET_PWROK,<br>+ .gpio28 = GPIO_RESET_PWROK,<br>+ .gpio29 = GPIO_RESET_PWROK,<br>+ .gpio30 = GPIO_RESET_PWROK,<br>+ .gpio31 = GPIO_RESET_PWROK,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_invert = {<br>+ .gpio0 = GPIO_NO_INVERT,<br>+ .gpio1 = GPIO_NO_INVERT,<br>+ .gpio2 = GPIO_NO_INVERT,<br>+ .gpio3 = GPIO_NO_INVERT,<br>+ .gpio4 = GPIO_NO_INVERT,<br>+ .gpio5 = GPIO_NO_INVERT,<br>+ .gpio6 = GPIO_NO_INVERT,<br>+ .gpio7 = GPIO_NO_INVERT,<br>+ .gpio8 = GPIO_NO_INVERT,<br>+ .gpio9 = GPIO_NO_INVERT,<br>+ .gpio10 = GPIO_NO_INVERT,<br>+ .gpio11 = GPIO_NO_INVERT,<br>+ .gpio12 = GPIO_NO_INVERT,<br>+ .gpio13 = GPIO_INVERT,<br>+ .gpio14 = GPIO_NO_INVERT,<br>+ .gpio15 = GPIO_NO_INVERT,<br>+ .gpio16 = GPIO_NO_INVERT,<br>+ .gpio17 = GPIO_NO_INVERT,<br>+ .gpio18 = GPIO_NO_INVERT,<br>+ .gpio19 = GPIO_NO_INVERT,<br>+ .gpio20 = GPIO_NO_INVERT,<br>+ .gpio21 = GPIO_NO_INVERT,<br>+ .gpio22 = GPIO_NO_INVERT,<br>+ .gpio23 = GPIO_NO_INVERT,<br>+ .gpio24 = GPIO_NO_INVERT,<br>+ .gpio25 = GPIO_NO_INVERT,<br>+ .gpio26 = GPIO_NO_INVERT,<br>+ .gpio27 = GPIO_NO_INVERT,<br>+ .gpio28 = GPIO_NO_INVERT,<br>+ .gpio29 = GPIO_NO_INVERT,<br>+ .gpio30 = GPIO_NO_INVERT,<br>+ .gpio31 = GPIO_NO_INVERT,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_blink = {<br>+ .gpio0 = GPIO_NO_BLINK,<br>+ .gpio1 = GPIO_NO_BLINK,<br>+ .gpio2 = GPIO_NO_BLINK,<br>+ .gpio3 = GPIO_NO_BLINK,<br>+ .gpio4 = GPIO_NO_BLINK,<br>+ .gpio5 = GPIO_NO_BLINK,<br>+ .gpio6 = GPIO_NO_BLINK,<br>+ .gpio7 = GPIO_NO_BLINK,<br>+ .gpio8 = GPIO_NO_BLINK,<br>+ .gpio9 = GPIO_NO_BLINK,<br>+ .gpio10 = GPIO_NO_BLINK,<br>+ .gpio11 = GPIO_NO_BLINK,<br>+ .gpio12 = GPIO_NO_BLINK,<br>+ .gpio13 = GPIO_NO_BLINK,<br>+ .gpio14 = GPIO_NO_BLINK,<br>+ .gpio15 = GPIO_NO_BLINK,<br>+ .gpio16 = GPIO_NO_BLINK,<br>+ .gpio17 = GPIO_NO_BLINK,<br>+ .gpio18 = GPIO_BLINK,<br>+ .gpio19 = GPIO_NO_BLINK,<br>+ .gpio20 = GPIO_NO_BLINK,<br>+ .gpio21 = GPIO_NO_BLINK,<br>+ .gpio22 = GPIO_NO_BLINK,<br>+ .gpio23 = GPIO_NO_BLINK,<br>+ .gpio24 = GPIO_NO_BLINK,<br>+ .gpio25 = GPIO_NO_BLINK,<br>+ .gpio26 = GPIO_NO_BLINK,<br>+ .gpio27 = GPIO_NO_BLINK,<br>+ .gpio28 = GPIO_NO_BLINK,<br>+ .gpio29 = GPIO_NO_BLINK,<br>+ .gpio30 = GPIO_NO_BLINK,<br>+ .gpio31 = GPIO_NO_BLINK,<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_mode = {<br>+ .gpio32 = GPIO_MODE_GPIO,<br>+ .gpio33 = GPIO_MODE_GPIO,<br>+ .gpio34 = GPIO_MODE_GPIO,<br>+ .gpio35 = GPIO_MODE_GPIO,<br>+ .gpio36 = GPIO_MODE_GPIO,<br>+ .gpio37 = GPIO_MODE_GPIO,<br>+ .gpio38 = GPIO_MODE_GPIO,<br>+ .gpio39 = GPIO_MODE_GPIO,<br>+ .gpio40 = GPIO_MODE_NATIVE,<br>+ .gpio41 = GPIO_MODE_NATIVE,<br>+ .gpio42 = GPIO_MODE_NATIVE,<br>+ .gpio43 = GPIO_MODE_NATIVE,<br>+ .gpio44 = GPIO_MODE_NATIVE,<br>+ .gpio45 = GPIO_MODE_NATIVE,<br>+ .gpio46 = GPIO_MODE_NATIVE,<br>+ .gpio47 = GPIO_MODE_NATIVE,<br>+ .gpio48 = GPIO_MODE_GPIO,<br>+ .gpio49 = GPIO_MODE_GPIO,<br>+ .gpio50 = GPIO_MODE_NATIVE,<br>+ .gpio51 = GPIO_MODE_NATIVE,<br>+ .gpio52 = GPIO_MODE_NATIVE,<br>+ .gpio53 = GPIO_MODE_NATIVE,<br>+ .gpio54 = GPIO_MODE_NATIVE,<br>+ .gpio55 = GPIO_MODE_NATIVE,<br>+ .gpio56 = GPIO_MODE_NATIVE,<br>+ .gpio57 = GPIO_MODE_GPIO,<br>+ .gpio58 = GPIO_MODE_NATIVE,<br>+ .gpio59 = GPIO_MODE_NATIVE,<br>+ .gpio60 = GPIO_MODE_NATIVE,<br>+ .gpio61 = GPIO_MODE_NATIVE,<br>+ .gpio62 = GPIO_MODE_NATIVE,<br>+ .gpio63 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_direction = {<br>+ .gpio32 = GPIO_DIR_OUTPUT,<br>+ .gpio33 = GPIO_DIR_OUTPUT,<br>+ .gpio34 = GPIO_DIR_INPUT,<br>+ .gpio35 = GPIO_DIR_OUTPUT,<br>+ .gpio36 = GPIO_DIR_INPUT,<br>+ .gpio37 = GPIO_DIR_INPUT,<br>+ .gpio38 = GPIO_DIR_INPUT,<br>+ .gpio39 = GPIO_DIR_INPUT,<br>+ .gpio40 = GPIO_DIR_INPUT,<br>+ .gpio41 = GPIO_DIR_INPUT,<br>+ .gpio42 = GPIO_DIR_INPUT,<br>+ .gpio43 = GPIO_DIR_INPUT,<br>+ .gpio44 = GPIO_DIR_INPUT,<br>+ .gpio45 = GPIO_DIR_INPUT,<br>+ .gpio46 = GPIO_DIR_INPUT,<br>+ .gpio47 = GPIO_DIR_INPUT,<br>+ .gpio48 = GPIO_DIR_INPUT,<br>+ .gpio49 = GPIO_DIR_INPUT,<br>+ .gpio50 = GPIO_DIR_INPUT,<br>+ .gpio51 = GPIO_DIR_OUTPUT,<br>+ .gpio52 = GPIO_DIR_INPUT,<br>+ .gpio53 = GPIO_DIR_OUTPUT,<br>+ .gpio54 = GPIO_DIR_INPUT,<br>+ .gpio55 = GPIO_DIR_OUTPUT,<br>+ .gpio56 = GPIO_DIR_INPUT,<br>+ .gpio57 = GPIO_DIR_INPUT,<br>+ .gpio58 = GPIO_DIR_INPUT,<br>+ .gpio59 = GPIO_DIR_INPUT,<br>+ .gpio60 = GPIO_DIR_INPUT,<br>+ .gpio61 = GPIO_DIR_OUTPUT,<br>+ .gpio62 = GPIO_DIR_OUTPUT,<br>+ .gpio63 = GPIO_DIR_OUTPUT,<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_level = {<br>+ .gpio32 = GPIO_LEVEL_HIGH,<br>+ .gpio33 = GPIO_LEVEL_HIGH,<br>+ .gpio34 = GPIO_LEVEL_HIGH,<br>+ .gpio35 = GPIO_LEVEL_LOW,<br>+ .gpio36 = GPIO_LEVEL_LOW,<br>+ .gpio37 = GPIO_LEVEL_LOW,<br>+ .gpio38 = GPIO_LEVEL_HIGH,<br>+ .gpio39 = GPIO_LEVEL_HIGH,<br>+ .gpio40 = GPIO_LEVEL_HIGH,<br>+ .gpio41 = GPIO_LEVEL_HIGH,<br>+ .gpio42 = GPIO_LEVEL_HIGH,<br>+ .gpio43 = GPIO_LEVEL_HIGH,<br>+ .gpio44 = GPIO_LEVEL_HIGH,<br>+ .gpio45 = GPIO_LEVEL_HIGH,<br>+ .gpio46 = GPIO_LEVEL_HIGH,<br>+ .gpio47 = GPIO_LEVEL_LOW,<br>+ .gpio48 = GPIO_LEVEL_HIGH,<br>+ .gpio49 = GPIO_LEVEL_HIGH,<br>+ .gpio50 = GPIO_LEVEL_HIGH,<br>+ .gpio51 = GPIO_LEVEL_HIGH,<br>+ .gpio52 = GPIO_LEVEL_HIGH,<br>+ .gpio53 = GPIO_LEVEL_HIGH,<br>+ .gpio54 = GPIO_LEVEL_HIGH,<br>+ .gpio55 = GPIO_LEVEL_HIGH,<br>+ .gpio56 = GPIO_LEVEL_LOW,<br>+ .gpio57 = GPIO_LEVEL_HIGH,<br>+ .gpio58 = GPIO_LEVEL_HIGH,<br>+ .gpio59 = GPIO_LEVEL_HIGH,<br>+ .gpio60 = GPIO_LEVEL_HIGH,<br>+ .gpio61 = GPIO_LEVEL_HIGH,<br>+ .gpio62 = GPIO_LEVEL_LOW,<br>+ .gpio63 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_reset = {<br>+ .gpio32 = GPIO_RESET_PWROK,<br>+ .gpio33 = GPIO_RESET_PWROK,<br>+ .gpio34 = GPIO_RESET_PWROK,<br>+ .gpio35 = GPIO_RESET_PWROK,<br>+ .gpio36 = GPIO_RESET_PWROK,<br>+ .gpio37 = GPIO_RESET_PWROK,<br>+ .gpio38 = GPIO_RESET_PWROK,<br>+ .gpio39 = GPIO_RESET_PWROK,<br>+ .gpio40 = GPIO_RESET_PWROK,<br>+ .gpio41 = GPIO_RESET_PWROK,<br>+ .gpio42 = GPIO_RESET_PWROK,<br>+ .gpio43 = GPIO_RESET_PWROK,<br>+ .gpio44 = GPIO_RESET_PWROK,<br>+ .gpio45 = GPIO_RESET_PWROK,<br>+ .gpio46 = GPIO_RESET_PWROK,<br>+ .gpio47 = GPIO_RESET_PWROK,<br>+ .gpio48 = GPIO_RESET_PWROK,<br>+ .gpio49 = GPIO_RESET_PWROK,<br>+ .gpio50 = GPIO_RESET_PWROK,<br>+ .gpio51 = GPIO_RESET_PWROK,<br>+ .gpio52 = GPIO_RESET_PWROK,<br>+ .gpio53 = GPIO_RESET_PWROK,<br>+ .gpio54 = GPIO_RESET_PWROK,<br>+ .gpio55 = GPIO_RESET_PWROK,<br>+ .gpio56 = GPIO_RESET_PWROK,<br>+ .gpio57 = GPIO_RESET_PWROK,<br>+ .gpio58 = GPIO_RESET_PWROK,<br>+ .gpio59 = GPIO_RESET_PWROK,<br>+ .gpio60 = GPIO_RESET_PWROK,<br>+ .gpio61 = GPIO_RESET_PWROK,<br>+ .gpio62 = GPIO_RESET_PWROK,<br>+ .gpio63 = GPIO_RESET_PWROK,<br>+};<br>+<br>+static const struct pch_gpio_set3 pch_gpio_set3_mode = {<br>+ .gpio64 = GPIO_MODE_NATIVE,<br>+ .gpio65 = GPIO_MODE_NATIVE,<br>+ .gpio66 = GPIO_MODE_NATIVE,<br>+ .gpio67 = GPIO_MODE_NATIVE,<br>+ .gpio68 = GPIO_MODE_GPIO,<br>+ .gpio69 = GPIO_MODE_GPIO,<br>+ .gpio70 = GPIO_MODE_NATIVE,<br>+ .gpio71 = GPIO_MODE_NATIVE,<br>+ .gpio72 = GPIO_MODE_GPIO,<br>+ .gpio73 = GPIO_MODE_NATIVE,<br>+ .gpio74 = GPIO_MODE_NATIVE,<br>+ .gpio75 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+static const struct pch_gpio_set3 pch_gpio_set3_direction = {<br>+ .gpio64 = GPIO_DIR_OUTPUT,<br>+ .gpio65 = GPIO_DIR_OUTPUT,<br>+ .gpio66 = GPIO_DIR_OUTPUT,<br>+ .gpio67 = GPIO_DIR_OUTPUT,<br>+ .gpio68 = GPIO_DIR_INPUT,<br>+ .gpio69 = GPIO_DIR_INPUT,<br>+ .gpio70 = GPIO_DIR_INPUT,<br>+ .gpio71 = GPIO_DIR_INPUT,<br>+ .gpio72 = GPIO_DIR_INPUT,<br>+ .gpio73 = GPIO_DIR_INPUT,<br>+ .gpio74 = GPIO_DIR_INPUT,<br>+ .gpio75 = GPIO_DIR_INPUT,<br>+};<br>+<br>+static const struct pch_gpio_set3 pch_gpio_set3_level = {<br>+ .gpio64 = GPIO_LEVEL_HIGH,<br>+ .gpio65 = GPIO_LEVEL_HIGH,<br>+ .gpio66 = GPIO_LEVEL_HIGH,<br>+ .gpio67 = GPIO_LEVEL_HIGH,<br>+ .gpio68 = GPIO_LEVEL_HIGH,<br>+ .gpio69 = GPIO_LEVEL_LOW,<br>+ .gpio70 = GPIO_LEVEL_HIGH,<br>+ .gpio71 = GPIO_LEVEL_HIGH,<br>+ .gpio72 = GPIO_LEVEL_HIGH,<br>+ .gpio73 = GPIO_LEVEL_LOW,<br>+ .gpio74 = GPIO_LEVEL_HIGH,<br>+ .gpio75 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+static const struct pch_gpio_set3 pch_gpio_set3_reset = {<br>+ .gpio64 = GPIO_RESET_PWROK,<br>+ .gpio65 = GPIO_RESET_PWROK,<br>+ .gpio66 = GPIO_RESET_PWROK,<br>+ .gpio67 = GPIO_RESET_PWROK,<br>+ .gpio68 = GPIO_RESET_PWROK,<br>+ .gpio69 = GPIO_RESET_PWROK,<br>+ .gpio70 = GPIO_RESET_PWROK,<br>+ .gpio71 = GPIO_RESET_PWROK,<br>+ .gpio72 = GPIO_RESET_PWROK,<br>+ .gpio73 = GPIO_RESET_PWROK,<br>+ .gpio74 = GPIO_RESET_PWROK,<br>+ .gpio75 = GPIO_RESET_PWROK,<br>+};<br>+<br>+const struct pch_gpio_map mainboard_gpio_map = {<br>+ .set1 = {<br>+ .mode = &pch_gpio_set1_mode,<br>+ .direction = &pch_gpio_set1_direction,<br>+ .level = &pch_gpio_set1_level,<br>+ .blink = &pch_gpio_set1_blink,<br>+ .invert = &pch_gpio_set1_invert,<br>+ .reset = &pch_gpio_set1_reset,<br>+ },<br>+ .set2 = {<br>+ .mode = &pch_gpio_set2_mode,<br>+ .direction = &pch_gpio_set2_direction,<br>+ .level = &pch_gpio_set2_level,<br>+ .reset = &pch_gpio_set2_reset,<br>+ },<br>+ .set3 = {<br>+ .mode = &pch_gpio_set3_mode,<br>+ .direction = &pch_gpio_set3_direction,<br>+ .level = &pch_gpio_set3_level,<br>+ .reset = &pch_gpio_set3_reset,<br>+ },<br>+};<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/hda_verb.c b/src/mainboard/gigabyte/ga-z77-ds3h/hda_verb.c<br>new file mode 100644<br>index 0000000..253ec08<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/hda_verb.c<br>@@ -0,0 +1,8 @@<br>+#include <device/azalia_device.h><br>+<br>+const u32 cim_verb_data[] = {<br>+};<br>+<br>+const u32 pc_beep_verbs[0] = {};<br>+<br>+AZALIA_ARRAY_SIZES;<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/mainboard.c b/src/mainboard/gigabyte/ga-z77-ds3h/mainboard.c<br>new file mode 100644<br>index 0000000..97cc46f<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/mainboard.c<br>@@ -0,0 +1,40 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ * Copyright (C) 2011-2012 Google Inc.<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/device.h><br>+#include <drivers/intel/gma/int15.h><br>+#include <southbridge/intel/bd82x6x/pch.h><br>+<br>+static void mainboard_init(device_t dev)<br>+{<br>+}<br>+<br>+// mainboard_enable is executed as first thing after<br>+// enumerate_buses().<br>+<br>+static void mainboard_enable(device_t dev)<br>+{<br>+ dev->ops->init = mainboard_init;<br>+<br>+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,<br>+ GMA_INT15_PANEL_FIT_DEFAULT,<br>+ GMA_INT15_BOOT_DISPLAY_CRT, 0);<br>+}<br>+<br>+struct chip_operations mainboard_ops = {<br>+ .enable_dev = mainboard_enable,<br>+};<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/romstage.c b/src/mainboard/gigabyte/ga-z77-ds3h/romstage.c<br>new file mode 100644<br>index 0000000..81c5ded<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/romstage.c<br>@@ -0,0 +1,109 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Damien Zammit <damien@zamaudio.com><br>+ * Copyright (C) 2017 Vagiz Tarkhanov <rakkin@autistici.org><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#define SUPERIO_BASE 0x2e<br>+<br>+#define GPIO_DEV PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)<br>+#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, IT8728F_SP1)<br>+<br>+#include <superio/ite/it8728f/it8728f.h><br>+#include <superio/ite/common/ite.h><br>+#include <northbridge/intel/sandybridge/raminit_native.h><br>+#include <drivers/uart/uart8250reg.h><br>+<br>+<br>+static void it8728f_z77ds3h_disable_reboot(pnp_devfn_t dev)<br>+{<br>+ /* protect dual bios */<br>+ ite_reg_write(dev, 0xEF, 0x7E);<br>+<br>+ /* booting with coreboot gives 0x40 while vendor sets 0x00 */<br>+ ite_reg_write(dev, 0x25, 0x00);<br>+ /* simple iobase 0xa00 */<br>+ ite_reg_write(dev, 0x62, 0x0a);<br>+ /* clear watchdog timeout */<br>+ ite_reg_write(dev, 0x73, 0x00);<br>+ /* enable generation of SMI# due to EC's IRQ */<br>+ ite_reg_write(dev, 0xf0, 0x10);<br>+ /* hardware monitor alert beep -> gp36(pin12)*/<br>+ ite_reg_write(dev, 0xf6, 0x1c);<br>+}<br>+<br>+void rcba_config(void)<br>+{<br>+ /* Disable unused devices (board specific) */<br>+ RCBA32(FD) = 0x17e01fe3;<br>+<br>+ /* Enable HECI */<br>+ RCBA32(FD2) &= ~0x2;<br>+}<br>+<br>+void pch_enable_lpc(void)<br>+{<br>+ /*<br>+ * Enable:<br>+ * EC Decode Range PortA30/A20<br>+ * SuperIO Port2E/2F<br>+ * PS/2 Keyboard/Mouse Port60/64<br>+ */<br>+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN<br>+ | CNF1_LPC_EN | COMA_LPC_EN);<br>+<br>+ /* GPIO */<br>+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>+ it8728f_z77ds3h_disable_reboot(GPIO_DEV);<br>+}<br>+<br>+const struct southbridge_usb_port mainboard_usb_ports[] = {<br>+ { 1, 6, 0 }, // f53 - current<br>+ { 1, 6, 0 }, // f53<br>+ { 1, 1, 1 }, // f57<br>+ { 1, 7, 1 }, // 357<br>+ { 1, 1, 2 }, // f57<br>+ { 1, 1, 2 }, // f57<br>+ { 1, 8, 3 }, // 353<br>+ { 1, 8, 3 }, // 353<br>+ { 1, 6, 4 }, // f53<br>+ { 1, 6, 4 }, // f53<br>+ { 1, 6, 6 }, // f53<br>+ { 1, 1, 5 }, // f57<br>+ { 1, 1, 5 }, // f57<br>+ { 1, 6, 6 }, // f53<br>+};<br>+<br>+void mainboard_get_spd(spd_raw_data *spd, bool id_only)<br>+{<br>+ read_spd(&spd[0], 0x50, id_only);<br>+ read_spd(&spd[1], 0x51, id_only);<br>+ read_spd(&spd[2], 0x52, id_only);<br>+ read_spd(&spd[3], 0x53, id_only);<br>+}<br>+<br>+void mainboard_early_init(int s3resume)<br>+{<br>+}<br>+<br>+void mainboard_config_superio(void)<br>+{<br>+ /* Aparantly the COMA port is booted in an undefined state in which<br>+ * the divisor is very high. In console_init() some functions are<br>+ * called which print to the console resulting in very long<br>+ * (up to 30s) boot delays.<br>+ * Setting the Baudrate Divisor Latch Access Bit (BDLAB) here fixes it.<br>+ */<br>+ if (CONFIG_TTYS0_BASE == 0x3f8)<br>+ outb(UART8250_LCR_DLAB, CONFIG_TTYS0_BASE + UART8250_LCR);<br>+}<br>diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/thermal.h b/src/mainboard/gigabyte/ga-z77-ds3h/thermal.h<br>new file mode 100644<br>index 0000000..3791f32<br>--- /dev/null<br>+++ b/src/mainboard/gigabyte/ga-z77-ds3h/thermal.h<br>@@ -0,0 +1,26 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef GAZ77DS3H_THERMAL_H<br>+#define GAZ77DS3H_THERMAL_H<br>+<br>+ /* Temperature which OS will shutdown at */<br>+ #define CRITICAL_TEMPERATURE 97<br>+<br>+ /* Temperature which OS will throttle CPU */<br>+ #define PASSIVE_TEMPERATURE 85<br>+<br>+#endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/21846">change 21846</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21846"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I90fef8b7a1181c2f6481e834d1aa342905b85f1e </div>
<div style="display:none"> Gerrit-Change-Number: 21846 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Vagiz Tarkhanov <rakkin@autistici.org> </div>