<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21761">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">debug reboot<br><br>Change-Id: I08a4bc7ea7023383d7d05118d42340857bfc439c<br>Signed-off-by: Marc Jones <marcj303@gmail.com><br>---<br>M src/lib/bootblock.c<br>M src/lib/prog_loaders.c<br>M src/soc/amd/common/agesawrapper.c<br>M src/soc/amd/common/def_callouts.c<br>M src/soc/amd/stoneyridge/Makefile.inc<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>M src/soc/amd/stoneyridge/reset.c<br>7 files changed, 23 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/21761/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c<br>index 2e228c6..52c5cca 100644<br>--- a/src/lib/bootblock.c<br>+++ b/src/lib/bootblock.c<br>@@ -48,7 +48,9 @@<br>    }<br> <br>  bootblock_soc_init();<br>+        post_code(0x66);<br>      bootblock_mainboard_init();<br>+  post_code(0x67);<br> <br>   run_romstage();<br> }<br>diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c<br>index 128869b..f9f4492 100644<br>--- a/src/lib/prog_loaders.c<br>+++ b/src/lib/prog_loaders.c<br>@@ -52,19 +52,19 @@<br> {<br>         struct prog romstage =<br>                PROG_INIT(PROG_ROMSTAGE, CONFIG_CBFS_PREFIX "/romstage");<br>-<br>+post_code(0x50);<br>     if (prog_locate(&romstage))<br>               goto fail;<br>-<br>+post_code(0x51);<br>      timestamp_add_now(TS_START_COPYROM);<br> <br>       if (cbfs_prog_stage_load(&romstage))<br>              goto fail;<br>-<br>+post_code(0x52);<br>      timestamp_add_now(TS_END_COPYROM);<br> <br>         prog_run(&romstage);<br>-<br>+post_code(0x53);<br> fail:<br>        if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE))<br>             die("Couldn't load romstage.\n");<br>diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c<br>index b95d61a..876fe31 100644<br>--- a/src/soc/amd/common/agesawrapper.c<br>+++ b/src/soc/amd/common/agesawrapper.c<br>@@ -71,10 +71,12 @@<br> <br>  AmdResetParams.FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3));<br>       AmdResetParams.FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3);<br>-<br>+       post_code(0x60);<br>      status = AmdInitReset(&AmdResetParams);<br>+  post_code(0x61);<br>      if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);<br>       AmdReleaseStruct (&AmdParamStruct);<br>+      post_code(0x62);<br>      return status;<br> }<br> <br>@@ -101,11 +103,12 @@<br>  OemCustomizeInitEarly (AmdEarlyParamsPtr);<br> <br>         AmdEarlyParamsPtr->GnbConfig.PsppPolicy = PsppDisabled;<br>+   post_code(0x63);<br>      status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);<br>-<br>+post_code(0x64);<br>        if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);<br>       AmdReleaseStruct (&AmdParamStruct);<br>-<br>+post_code(0x65);<br>         return status;<br> }<br> <br>diff --git a/src/soc/amd/common/def_callouts.c b/src/soc/amd/common/def_callouts.c<br>index fda0013..8bce75e 100644<br>--- a/src/soc/amd/common/def_callouts.c<br>+++ b/src/soc/amd/common/def_callouts.c<br>@@ -16,6 +16,7 @@<br> <br> #include <cbfs.h><br> #include <spd_bin.h><br>+#include <reset.h><br> <br> #include <AGESA.h><br> #include <amdlib.h><br>@@ -60,7 +61,7 @@<br> AGESA_STATUS agesa_Reset(UINT32 Func, UINTN Data, VOID *ConfigPtr)<br> {<br>      AGESA_STATUS Status;<br>- UINT8 Value;<br>+ //UINT8 Value;<br>        UINTN ResetType;<br>      AMD_CONFIG_PARAMS *StdHeader;<br> <br>@@ -80,8 +81,10 @@<br> <br>       case WARM_RESET_IMMEDIATELY:<br>  case COLD_RESET_IMMEDIATELY:<br>-         Value = 0x06;<br>-                LibAmdIoWrite(AccessWidth8, SYS_RESET, &Value, StdHeader);<br>+       post_code(0x6E);<br>+     hard_reset();<br>+                //Value = 0x06;<br>+              //LibAmdIoWrite(AccessWidth8, SYS_RESET, &Value, StdHeader);<br>              break;<br> <br>     default:<br>diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc<br>index 06d9f58..4f2d13a 100644<br>--- a/src/soc/amd/stoneyridge/Makefile.inc<br>+++ b/src/soc/amd/stoneyridge/Makefile.inc<br>@@ -52,6 +52,7 @@<br> romstage-y += gpio.c<br> romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c<br> romstage-y += pmutil.c<br>+romstage-y += reset.c<br> romstage-y += smbus.c<br> romstage-y += smbus_spd.c<br> romstage-y += ramtop.c<br>@@ -74,7 +75,6 @@<br> ramstage-y += lpc.c<br> ramstage-y += model_15_init.c<br> ramstage-y += northbridge.c<br>-ramstage-y += pmutil.c<br> ramstage-y += reset.c<br> ramstage-y += sata.c<br> ramstage-y += sm.c<br>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>index 3f01603..3a1fdc4 100644<br>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>@@ -60,4 +60,5 @@<br> <br>    post_code(0x38);<br>      AGESAWRAPPER(amdinitearly); /* APs will not exit amdinitearly */<br>+     post_code(0x39);<br> }<br>diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c<br>index 73f944d..9f1f060 100644<br>--- a/src/soc/amd/stoneyridge/reset.c<br>+++ b/src/soc/amd/stoneyridge/reset.c<br>@@ -19,6 +19,7 @@<br> #include <arch/io.h><br> #include <reset.h><br> #include <soc/southbridge.h><br>+#include <console/console.h><br> <br> #define HT_INIT_CONTROL                     0x6c<br>  #define HTIC_BIOSR_Detect               (1 << 5)<br>@@ -34,6 +35,8 @@<br> <br> void do_hard_reset(void)<br> {<br>+<br>+       post_code(0x6F);<br>      set_bios_reset();<br>     /* Try rebooting through port 0xcf9 */<br>        /*<br></pre><p>To view, visit <a href="https://review.coreboot.org/21761">change 21761</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21761"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I08a4bc7ea7023383d7d05118d42340857bfc439c </div>
<div style="display:none"> Gerrit-Change-Number: 21761 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>