<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21766">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/*/gma: Port ACPI opregion to older platforms<br><br>Port the ACPI opregion implementation that resides in<br>drivers/intel/gma to older platforms.<br><br>It allows to include a vbt.bin and to allows GNU/Linux to load the<br>opregion as ASLS is being set.<br><br>Windows' Intel will likely ignore it as it relies on legacy VBIOS<br>to be loaded at 0xc0000.<br><br>Needs test on all platforms.<br><br>Change-Id: I1896411155592b343e48cbd116e2f70fb0dbfafa<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/northbridge/intel/gm45/gma.c<br>M src/northbridge/intel/i945/gma.c<br>M src/northbridge/intel/x4x/gma.c<br>3 files changed, 158 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/21766/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c<br>index 00b3fa0..bdad49b 100644<br>--- a/src/northbridge/intel/gm45/gma.c<br>+++ b/src/northbridge/intel/gm45/gma.c<br>@@ -25,6 +25,8 @@<br> #include <cpu/x86/msr.h><br> #include <cpu/x86/mtrr.h><br> #include <commonlib/helpers.h><br>+#include <cbmem.h><br>+#include <southbridge/intel/i82801ix/nvs.h><br> <br> #include "drivers/intel/gma/i915_reg.h"<br> #include "chip.h"<br>@@ -32,6 +34,7 @@<br> #include <drivers/intel/gma/intel_bios.h><br> #include <drivers/intel/gma/edid.h><br> #include <drivers/intel/gma/i915.h><br>+#include <drivers/intel/gma/opregion.h><br> #include <pc80/vga.h><br> #include <pc80/vga_io.h><br> <br>@@ -47,6 +50,19 @@<br> void gtt_write(u32 reg, u32 data)<br> {<br> write32(res2mmio(gtt_res, reg, 0), data);<br>+}<br>+<br>+uintptr_t gma_get_gnvs_aslb(const void *gnvs)<br>+{<br>+ const global_nvs_t *gnvs_ptr = gnvs;<br>+ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);<br>+}<br>+<br>+void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)<br>+{<br>+ global_nvs_t *gnvs_ptr = gnvs;<br>+ if (gnvs_ptr)<br>+ gnvs_ptr->aslb = aslb;<br> }<br> <br> static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,<br>@@ -758,6 +774,8 @@<br> <br> if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))<br> gma_ngi(dev, &edid_lvds);<br>+<br>+ intel_gma_restore_opregion();<br> }<br> <br> static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>@@ -793,6 +811,37 @@<br> drivers_intel_gma_displays_ssdt_generate(gfx);<br> }<br> <br>+static unsigned long<br>+gma_write_acpi_tables(struct device *const dev,<br>+ unsigned long current,<br>+ struct acpi_rsdp *const rsdp)<br>+{<br>+ igd_opregion_t *opregion = (igd_opregion_t *)current;<br>+ global_nvs_t *gnvs;<br>+<br>+ if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)<br>+ return current;<br>+<br>+ current += sizeof(igd_opregion_t);<br>+<br>+ /* GNVS has been already set up */<br>+ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);<br>+ if (gnvs) {<br>+ /* IGD OpRegion Base Address */<br>+ gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);<br>+ } else {<br>+ printk(BIOS_ERR, "Error: GNVS table not found.\n");<br>+ }<br>+<br>+ current = acpi_align_current(current);<br>+ return current;<br>+}<br>+<br>+static const char *gma_acpi_name(const struct device *dev)<br>+{<br>+ return "GFX0";<br>+}<br>+<br> static struct pci_operations gma_pci_ops = {<br> .set_subsystem = gma_set_subsystem,<br> };<br>@@ -806,6 +855,8 @@<br> .scan_bus = 0,<br> .enable = 0,<br> .ops_pci = &gma_pci_ops,<br>+ .acpi_name = gma_acpi_name,<br>+ .write_acpi_tables = gma_write_acpi_tables,<br> };<br> <br> static const unsigned short pci_device_ids[] =<br>diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c<br>index 37f73ed..8d60bc9 100644<br>--- a/src/northbridge/intel/i945/gma.c<br>+++ b/src/northbridge/intel/i945/gma.c<br>@@ -23,10 +23,13 @@<br> #include <edid.h><br> #include <drivers/intel/gma/edid.h><br> #include <drivers/intel/gma/i915.h><br>+#include <drivers/intel/gma/opregion.h><br> #include <string.h><br> #include <pc80/vga.h><br> #include <pc80/vga_io.h><br> #include <commonlib/helpers.h><br>+#include <cbmem.h><br>+#include <southbridge/intel/i82801gx/nvs.h><br> <br> #include "i945.h"<br> #include "chip.h"<br>@@ -48,6 +51,19 @@<br> #define BASE_FREQUENCY 100000<br> <br> #define DEFAULT_BLC_PWM 180<br>+<br>+uintptr_t gma_get_gnvs_aslb(const void *gnvs)<br>+{<br>+ const global_nvs_t *gnvs_ptr = gnvs;<br>+ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);<br>+}<br>+<br>+void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)<br>+{<br>+ global_nvs_t *gnvs_ptr = gnvs;<br>+ if (gnvs_ptr)<br>+ gnvs_ptr->aslb = aslb;<br>+}<br> <br> static int gtt_setup(u8 *mmiobase)<br> {<br>@@ -687,6 +703,8 @@<br> /* PCI Init, will run VBIOS */<br> pci_dev_init(dev);<br> }<br>+<br>+ intel_gma_restore_opregion();<br> }<br> <br> /* This doesn't reclaim stolen UMA memory, but IGD could still<br>@@ -767,6 +785,37 @@<br> pci_dev_read_resources(dev);<br> }<br> <br>+static unsigned long<br>+gma_write_acpi_tables(struct device *const dev,<br>+ unsigned long current,<br>+ struct acpi_rsdp *const rsdp)<br>+{<br>+ igd_opregion_t *opregion = (igd_opregion_t *)current;<br>+ global_nvs_t *gnvs;<br>+<br>+ if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)<br>+ return current;<br>+<br>+ current += sizeof(igd_opregion_t);<br>+<br>+ /* GNVS has been already set up */<br>+ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);<br>+ if (gnvs) {<br>+ /* IGD OpRegion Base Address */<br>+ gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);<br>+ } else {<br>+ printk(BIOS_ERR, "Error: GNVS table not found.\n");<br>+ }<br>+<br>+ current = acpi_align_current(current);<br>+ return current;<br>+}<br>+<br>+static const char *gma_acpi_name(const struct device *dev)<br>+{<br>+ return "GFX0";<br>+}<br>+<br> static struct pci_operations gma_pci_ops = {<br> .set_subsystem = gma_set_subsystem,<br> };<br>@@ -781,6 +830,8 @@<br> .enable = 0,<br> .disable = gma_func0_disable,<br> .ops_pci = &gma_pci_ops,<br>+ .acpi_name = gma_acpi_name,<br>+ .write_acpi_tables = gma_write_acpi_tables,<br> };<br> <br> <br>diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c<br>index db96fac..cf3804d 100644<br>--- a/src/northbridge/intel/x4x/gma.c<br>+++ b/src/northbridge/intel/x4x/gma.c<br>@@ -26,6 +26,7 @@<br> #include <cpu/x86/msr.h><br> #include <cpu/x86/mtrr.h><br> #include <commonlib/helpers.h><br>+#include <cbmem.h><br> <br> #include "drivers/intel/gma/i915_reg.h"<br> #include "chip.h"<br>@@ -33,10 +34,30 @@<br> #include <drivers/intel/gma/intel_bios.h><br> #include <drivers/intel/gma/edid.h><br> #include <drivers/intel/gma/i915.h><br>+#include <drivers/intel/gma/opregion.h><br> #include <pc80/vga.h><br> #include <pc80/vga_io.h><br> <br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX)<br>+#include <southbridge/intel/i82801jx/nvs.h><br>+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)<br>+#include <southbridge/intel/i82801gx/nvs.h><br>+#endif<br>+<br> #define BASE_FREQUENCY 96000<br>+<br>+uintptr_t gma_get_gnvs_aslb(const void *gnvs)<br>+{<br>+ const global_nvs_t *gnvs_ptr = gnvs;<br>+ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);<br>+}<br>+<br>+void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)<br>+{<br>+ global_nvs_t *gnvs_ptr = gnvs;<br>+ if (gnvs_ptr)<br>+ gnvs_ptr->aslb = aslb;<br>+}<br> <br> static u8 edid_is_present(u8 *edid, u32 edid_size)<br> {<br>@@ -395,6 +416,8 @@<br> } else {<br> pci_dev_init(dev);<br> }<br>+<br>+ intel_gma_restore_opregion();<br> }<br> <br> static void gma_func0_disable(struct device *dev)<br>@@ -439,6 +462,37 @@<br> drivers_intel_gma_displays_ssdt_generate(gfx);<br> }<br> <br>+static unsigned long<br>+gma_write_acpi_tables(struct device *const dev,<br>+ unsigned long current,<br>+ struct acpi_rsdp *const rsdp)<br>+{<br>+ igd_opregion_t *opregion = (igd_opregion_t *)current;<br>+ global_nvs_t *gnvs;<br>+<br>+ if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)<br>+ return current;<br>+<br>+ current += sizeof(igd_opregion_t);<br>+<br>+ /* GNVS has been already set up */<br>+ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);<br>+ if (gnvs) {<br>+ /* IGD OpRegion Base Address */<br>+ gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);<br>+ } else {<br>+ printk(BIOS_ERR, "Error: GNVS table not found.\n");<br>+ }<br>+<br>+ current = acpi_align_current(current);<br>+ return current;<br>+}<br>+<br>+static const char *gma_acpi_name(const struct device *dev)<br>+{<br>+ return "GFX0";<br>+}<br>+<br> static struct pci_operations gma_pci_ops = {<br> .set_subsystem = gma_set_subsystem,<br> };<br>@@ -451,6 +505,8 @@<br> .init = gma_func0_init,<br> .ops_pci = &gma_pci_ops,<br> .disable = gma_func0_disable,<br>+ .acpi_name = gma_acpi_name,<br>+ .write_acpi_tables = gma_write_acpi_tables,<br> };<br> <br> static const unsigned short pci_device_ids[] = {<br></pre><p>To view, visit <a href="https://review.coreboot.org/21766">change 21766</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21766"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1896411155592b343e48cbd116e2f70fb0dbfafa </div>
<div style="display:none"> Gerrit-Change-Number: 21766 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>