<p>Gaggery Tsai has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21765">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/fizz: Enable Devslp for SATA port 1<br><br>This patch is to enable the support of device sleep<br>for SATA port 1.<br><br>BUG=b:65808359<br>BRANCH=None<br>TEST=Ran "suspend_stress_test -c 2500" and passed the test.<br><br>Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3<br>Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com><br>---<br>M src/mainboard/google/fizz/devicetree.cb<br>M src/mainboard/google/fizz/gpio.h<br>2 files changed, 2 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/21765/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb<br>index ead880e..8f5c49f 100644<br>--- a/src/mainboard/google/fizz/devicetree.cb<br>+++ b/src/mainboard/google/fizz/devicetree.cb<br>@@ -30,8 +30,8 @@<br>       register "EnableSata" = "1"<br>       register "SataSalpSupport" = "1"<br>  register "SataMode" = "1"<br>-        register "SataPortsEnable[0]" = "1"<br>       register "SataPortsEnable[1]" = "1"<br>+      register "SataPortsDevSlp[1]" = "1"<br>       register "EnableAzalia" = "1"<br>     register "DspEnable" = "1"<br>        register "IoBufferOwnership" = "3"<br>diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h<br>index 13081ec..d9f1bd8 100644<br>--- a/src/mainboard/google/fizz/gpio.h<br>+++ b/src/mainboard/google/fizz/gpio.h<br>@@ -167,7 +167,7 @@<br> /* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP,<br>                                 NF1), /* DB_PCIE_SATA#_DET */<br> /* CPU_GP0 */                PAD_CFG_NC(GPP_E3),<br>-/* SATA_DEVSLP0 */        PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* DEVSLP0_MB */<br>+/* SATA_DEVSLP0 */      PAD_CFG_GPI(GPP_E4, NONE, DEEP), /* DEVSLP0_MB */<br> /* SATA_DEVSLP1 */  PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */<br> /* SATA_DEVSLP2 */      PAD_CFG_NC(GPP_E6), /* TP328 */<br> /* CPU_GP1 */         PAD_CFG_NC(GPP_E7),<br></pre><p>To view, visit <a href="https://review.coreboot.org/21765">change 21765</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21765"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3 </div>
<div style="display:none"> Gerrit-Change-Number: 21765 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Gaggery Tsai <gaggery.tsai@intel.com> </div>