<p>John E. Kabat Jr. has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21728">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Add ELOG to SMM (WIP)<br><br>Add ELOG entries to smihandler.c<br>Use latest southbridge.h<br>Change ACPI_SMI_CMD_ENABLE from 0xEF to 0xE1 to fix conflict with<br>ELOG_GSMI_APM_CNT in elog.<br>Correct errors on debug statement in eloc.g.<br>Add required file uart.c to the makefile for elog<br>Test code included - will be removed later.<br>BUG=b:65485690<br>Blocked by issue 65587605 SMM mode SPI driver<br><br>Change-Id: I458babe1694f042215dd0e1c3277856e340de86f<br>Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com><br>---<br>M src/drivers/elog/Makefile.inc<br>M src/drivers/elog/elog.c<br>M src/soc/amd/stoneyridge/Makefile.inc<br>M src/soc/amd/stoneyridge/include/soc/smi.h<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/smihandler.c<br>6 files changed, 275 insertions(+), 54 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/21728/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc<br>index 79a7cc0..437e5dd 100644<br>--- a/src/drivers/elog/Makefile.inc<br>+++ b/src/drivers/elog/Makefile.inc<br>@@ -1,6 +1,7 @@<br> ramstage-$(CONFIG_ELOG) += elog.c<br> <br> smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c<br>+smm-$(CONFIG_ELOG_DEBUG) += ../../lib/hexdump.c<br> <br> romstage-$(CONFIG_ELOG_BOOT_COUNT) += boot_count.c<br> ramstage-$(CONFIG_ELOG_BOOT_COUNT) += boot_count.c<br>diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c<br>index 1c17561..d174419 100644<br>--- a/src/drivers/elog/elog.c<br>+++ b/src/drivers/elog/elog.c<br>@@ -324,8 +324,8 @@<br> <br> address = rdev_mmap(rdev, offset, size);<br> <br>- elog_debug("%s(address=0x%p offset=0x%08x size=%u)\n", __func__,<br>- address, offset, size);<br>+ printk(BIOS_DEBUG, "%s(address=0x%p offset=0x%08zx size=%zu)\n",<br>+ __func__, address, offset, size);<br> <br> if (address == NULL)<br> return;<br>diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc<br>index 5524a29..f783a9f 100644<br>--- a/src/soc/amd/stoneyridge/Makefile.inc<br>+++ b/src/soc/amd/stoneyridge/Makefile.inc<br>@@ -85,10 +85,10 @@<br> ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c<br> ramstage-y += usb.c<br> ramstage-y += tsc_freq.c<br>-<br> smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c<br> smm-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c<br> smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c<br>+smm-$(CONFIG_STONEYRIDGE_UART) += uart.c<br> <br> CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge<br> CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include<br>diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h<br>index 6f7cadb..aa11afa 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/smi.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/smi.h<br>@@ -54,27 +54,33 @@<br> #define SMISTAT1_FAKESMI_0 (1 << 1)<br> #define SMISTAT1_FAKESMI_1 (1 << 2)<br> #define SMISTAT1_FAKESMI_2 (1 << 3)<br>-#define SMISTAT1_FAKESMI_EVTS (0b111 << 1)<br>-#define SMISTAT1_FAKE_SMI_EVTS (SMISTAT1_FAKESMI_0 | SMISTAT1_FAKESMI_1 | SMISTAT1_FAKESMI_2)<br>-#define SMISTAT1_ECGE0_EVTS (1 << 8)<br>-#define SMISTAT1_TWARN_EVTS (1 << 16))<br>-#define SMISTAT1_PWRBTN_EVTS (1 << 19)<br>-#define SMISTAT1_PROCHOT_EVTS (1 << 20)<br>+#define SMISTAT1_FAKE_SMI_EVTS (0x07 << 1)<br>+#define SMISTAT1_FAKESMI_EVTS (SMISTAT1_FAKESMI_0 | \<br>+ SMISTAT1_FAKESMI_1 | \<br>+ SMISTAT1_FAKESMI_2)<br>+#define SMISTAT1_ECGE0 (1 << 8)<br>+#define SMISTAT1_TWARN (1 << 16)<br>+#define SMISTAT1_PWRBTN (1 << 19)<br>+#define SMISTAT1_PROCHOT (1 << 20)<br> #define SMI_REG_SMISTAT2 0x88<br>-#define SMISTAT2_SLPTYP_EVTS (1 << 1)<br>-#define SMISTAT2_PWRBTN_EVTS (1 << 10)<br>-#define SMISTAT2_ACPI_CMD_EVTS (1 << 11)<br>-#define SMISTAT2_ECSMI0_EVTS (1 << 15)<br>-#define SMISTAT2_PROCHOT_EVTS (1 << 19)<br>+#define SMISTAT2_SLPTYP (1 << 1)<br>+#define SMISTAT2_PWRBTN (1 << 10)<br>+#define SMISTAT2_ACPI_CMD (1 << 11)<br>+#define SMISTAT2_ECSMI0 (1 << 15)<br>+#define SMISTAT2_PROCHOT (1 << 19)<br> #define SMI_REG_SMISTAT3 0x8c<br> #define SMI_REG_SMISTAT4 0x90<br>-#define SMISTAT4_FAKESMI_EVTS (0b111 << 10)<br> #define SMISTAT4_FAKESMI_0 (1 << 10)<br> #define SMISTAT4_FAKESMI_1 (1 << 11)<br> #define SMISTAT4_FAKESMI_2 (1 << 12)<br>-#define SMISTAT4_MEMTRAP_EVT (1 << 24)<br>+#define SMISTAT4_FAKE_SMI_EVTS (0x07 << 10)<br>+#define SMISTAT4_FAKESMI_EVTS (SMISTAT4_FAKESMI_0 | \<br>+ SMISTAT4_FAKESMI_1 | \<br>+ SMISTAT4_FAKESMI_2)<br>+#define SMISTAT4_MEMTRAP (1 << 24)<br> <br>-#define SMI_REG_SMI_TIMERT 0x94<br>+#define SMI_REG_SMI_POINTER 0x94<br>+#define SMI_REG_SMI_TIMERT 0x96<br> <br> #define SMI_REG_SMITRIG0 0x98<br> #define SMITRG0_SMIENB (1 << 31)<br>@@ -85,19 +91,13 @@<br> <br> #define SMI_REG_SMITRIG1 0x9c<br> <br>-/* Bit settings for SMI_CTL */<br>-#define SMI_CTL_SET_DISABLE (0b00)<br>-#define SMI_CTL_SET_SMI (0b01)<br>-#define SMI_CTL_SET_NMI (0b10)<br>-#define SMI_CTL_SET_IRQ13 (0b11)<br>-<br> #define SMI_REG_CONTROL0 0xa0<br> #define SMI_REG_CONTROL1 0xa4<br> <br> #define SMI_REG_SMICTRL2 0xa8 /* SMIs reported in SMIx84 */<br>-#define SMICTRL2_FAKE2_SMI_EN (SMI_CTL_SET_SMI << 6)<br>-#define SMICTRL2_FAKE1_SMI_EN (SMI_CTL_SET_SMI << 4)<br>-#define SMICTRL2_FAKE0_SMI_EN (SMI_CTL_SET_SMI << 2)<br>+#define SMICTRL2_FAKE2_SMI_EN (SMI_MODE_SMI << 6)<br>+#define SMICTRL2_FAKE1_SMI_EN (SMI_MODE_SMI << 4)<br>+#define SMICTRL2_FAKE0_SMI_EN (SMI_MODE_SMI << 2)<br> <br> #define SMI_REG_CONTROL3 0xac<br> #define SMI_REG_CONTROL4 0xb0<br>@@ -106,13 +106,14 @@<br> #define SMI_REG_CONTROL7 0xbc<br> <br> #define SMI_REG_SMICTRL8 0xc0 /* SMIs reported in SMIx90 */<br>-#define SMICTRL8_FAKE2_SMI_EN (SMI_CTL_SET_SMI << 24)<br>-#define SMICTRL8_FAKE1_SMI_EN (SMI_CTL_SET_SMI << 22)<br>-#define SMICTRL8_FAKE0_SMI_EN (SMI_CTL_SET_SMI << 20)<br>+#define SMICTRL8_FAKE2_SMI_EN (SMI_MODE_SMI << 24)<br>+#define SMICTRL8_FAKE1_SMI_EN (SMI_MODE_SMI << 22)<br>+#define SMICTRL8_FAKE0_SMI_EN (SMI_MODE_SMI << 20)<br> <br> #define SMI_REG_SMICTRL9 0xc4 /* SMIs reported in SMIx90 */<br>-#define SMICTRL9_MTRAP_EN (SMI_CTL_SET_SMI << 16) /* Enable memory trap SMI */<br>+#define SMICTRL9_MTRAP_EN (SMI_MODE_SMI << 16) /* Enable memory trap */<br> #define SMICTRL9_MTRAP_MASK (0x03 << 16) /* Memory trap field mask */<br>+<br> #define SMI_REG_IO_TRAP0 0xc8<br> #define SMI_REG_MEM_TRAP0 0xd0<br> #define SMI_REG_MEM_RD_OVR_DATA 0xd4<br>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>index 20edf5f..8604206 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>@@ -23,6 +23,109 @@<br> #include <device/device.h><br> #include "chip.h"<br> <br>+/* Some older include files such as fch.h use predefined bits values<br>+ * instead of using BIT(x) macro. As they are used in early_setup.c,<br>+ * they need to be defined, and southbridge.h needs to be included<br>+ * before the ofending file.<br>+ */<br>+<br>+#ifndef BIT0<br>+#define BIT0 BIT(0)<br>+#endif<br>+#ifndef BIT1<br>+#define BIT1 BIT(1)<br>+#endif<br>+#ifndef BIT2<br>+#define BIT2 BIT(2)<br>+#endif<br>+#ifndef BIT3<br>+#define BIT3 BIT(3)<br>+#endif<br>+#ifndef BIT4<br>+#define BIT4 BIT(4)<br>+#endif<br>+#ifndef BIT5<br>+#define BIT5 BIT(5)<br>+#endif<br>+#ifndef BIT6<br>+#define BIT6 BIT(6)<br>+#endif<br>+#ifndef BIT7<br>+#define BIT7 BIT(7)<br>+#endif<br>+#ifndef BIT8<br>+#define BIT8 BIT(8)<br>+#endif<br>+#ifndef BIT9<br>+#define BIT9 BIT(9)<br>+#endif<br>+#ifndef BIT10<br>+#define BIT10 BIT(10)<br>+#endif<br>+#ifndef BIT11<br>+#define BIT11 BIT(11)<br>+#endif<br>+#ifndef BIT12<br>+#define BIT12 BIT(12)<br>+#endif<br>+#ifndef BIT13<br>+#define BIT13 BIT(13)<br>+#endif<br>+#ifndef BIT14<br>+#define BIT14 BIT(14)<br>+#endif<br>+#ifndef BIT15<br>+#define BIT15 BIT(15)<br>+#endif<br>+#ifndef BIT16<br>+#define BIT16 BIT(16)<br>+#endif<br>+#ifndef BIT17<br>+#define BIT17 BIT(17)<br>+#endif<br>+#ifndef BIT18<br>+#define BIT18 BIT(18)<br>+#endif<br>+#ifndef BIT19<br>+#define BIT19 BIT(19)<br>+#endif<br>+#ifndef BIT20<br>+#define BIT20 BIT(20)<br>+#endif<br>+#ifndef BIT21<br>+#define BIT21 BIT(21)<br>+#endif<br>+#ifndef BIT22<br>+#define BIT22 BIT(22)<br>+#endif<br>+#ifndef BIT23<br>+#define BIT23 BIT(23)<br>+#endif<br>+#ifndef BIT24<br>+#define BIT24 BIT(24)<br>+#endif<br>+#ifndef BIT25<br>+#define BIT25 BIT(25)<br>+#endif<br>+#ifndef BIT26<br>+#define BIT26 BIT(26)<br>+#endif<br>+#ifndef BIT27<br>+#define BIT27 BIT(27)<br>+#endif<br>+#ifndef BIT28<br>+#define BIT28 BIT(28)<br>+#endif<br>+#ifndef BIT29<br>+#define BIT29 BIT(29)<br>+#endif<br>+#ifndef BIT30<br>+#define BIT30 BIT(30)<br>+#endif<br>+#ifndef BIT31<br>+#define BIT31 BIT(31)<br>+#endif<br>+<br> #define IO_APIC2_ADDR 0xfec20000<br> <br> /* Offsets from ACPI_MMIO_BASE<br>@@ -44,6 +147,17 @@<br> <br> #define PM_ACPI_MMIO_EN 0x24<br> #define PM_SERIRQ_CONF 0x54<br>+#define PM_SERIRQ_NUM_BITS_17 0x0000<br>+#define PM_SERIRQ_NUM_BITS_18 0x0004<br>+#define PM_SERIRQ_NUM_BITS_19 0x0008<br>+#define PM_SERIRQ_NUM_BITS_20 0x000c<br>+#define PM_SERIRQ_NUM_BITS_21 0x0010<br>+#define PM_SERIRQ_NUM_BITS_22 0x0014<br>+#define PM_SERIRQ_NUM_BITS_23 0x0018<br>+#define PM_SERIRQ_NUM_BITS_24 0x001c<br>+#define PM_SERIRQ_MODE BIT(6)<br>+#define PM_SERIRQ_ENABLE BIT(7)<br>+<br> #define PM_EVT_BLK 0x60<br> #define PM1_CNT_BLK 0x62<br> #define PM_TMR_BLK 0x64<br>@@ -56,6 +170,10 @@<br> #define PM_HUD_SD_FLASH_CTRL 0xe7<br> #define PM_YANG_SD_FLASH_CTRL 0xe8<br> #define PM_PCIB_CFG 0xea<br>+#define PM_LPC_GATING 0xec<br>+#define PM_LPC_AB_NO_BYPASS_EN BIT(2)<br>+#define PM_LPC_A20_EN BIT(1)<br>+#define PM_LPC_ENABLE BIT(0)<br> <br> #define SYS_RESET 0xcf9<br> <br>@@ -70,16 +188,22 @@<br> #define ACPI_SMI_CMD_CST_CONTROL 0xde<br> #define ACPI_SMI_CMD_PST_CONTROL 0xad<br> #define ACPI_SMI_CMD_DISABLE 0xbe<br>-#define ACPI_SMI_CMD_ENABLE 0xef<br>+#define ACPI_SMI_CMD_ENABLE 0xe1<br> #define ACPI_SMI_CMD_S4_REQ 0xc0<br> <br>-#define REV_STONEYRIDGE_A11 0x11<br>-#define REV_STONEYRIDGE_A12 0x12<br>+#define REV_STONEYRIDGE_A11 0x11<br>+#define REV_STONEYRIDGE_A12 0x12<br> <br> #define SPIROM_BASE_ADDRESS_REGISTER 0xa0<br> #define ROUTE_TPM_2_SPI BIT(3)<br>-#define SPI_ROM_ENABLE 0x02<br>+#define SPI_ABORT_ENABLE BIT(2)<br>+#define SPI_ROM_ENABLE BIT(1)<br>+#define SPI_ROM_ALT_ENABLE BIT(0)<br>+#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))<br> #define SPI_BASE_ADDRESS 0xfec10000<br>+<br>+#define LPC_PCI_CONTROL 0x40<br>+#define LEGACY_DMA_EN BIT(2)<br> <br> #define LPC_IO_PORT_DECODE_ENABLE 0x44<br> #define DECODE_ENABLE_PARALLEL_PORT0 BIT(0)<br>@@ -118,16 +242,55 @@<br> #define LPC_IO_OR_MEM_DECODE_ENABLE 0x48<br> #define LPC_WIDEIO2_ENABLE BIT(25)<br> #define LPC_WIDEIO1_ENABLE BIT(24)<br>+#define DECODE_IO_PORT_ENABLE6 BIT(23)<br>+#define DECODE_IO_PORT_ENABLE5 BIT(22)<br>+#define DECODE_IO_PORT_ENABLE4 BIT(21)<br>+#define DECODE_IO_PORT_ENABLE3 BIT(19)<br>+#define DECODE_IO_PORT_ENABLE2 BIT(18)<br>+#define DECODE_IO_PORT_ENABLE1 BIT(17)<br>+#define DECODE_IO_PORT_ENABLE0 BIT(16)<br>+#define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7)<br> #define LPC_WIDEIO0_ENABLE BIT(2)<br>+/* Assuming word access to higher word (register 0x4a) */<br>+#define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a<br>+#define LPC_WIDEIO2_ENABLE_H BIT(9)<br>+#define LPC_WIDEIO1_ENABLE_H BIT(8)<br>+#define DECODE_IO_PORT_ENABLE6_H BIT(7)<br>+#define DECODE_IO_PORT_ENABLE5_H BIT(6)<br>+#define DECODE_IO_PORT_ENABLE4_H BIT(5)<br>+#define DECODE_IO_PORT_ENABLE3_H BIT(3)<br>+#define DECODE_IO_PORT_ENABLE2_H BIT(2)<br>+#define DECODE_IO_PORT_ENABLE1_H BIT(1)<br>+#define DECODE_IO_PORT_ENABLE0_H BIT(0)<br> <br>+/* Register 0x64 is 32-bit, composed by two 16-bit sub-registers.<br>+ * For ease of access, each sub-register is declared separetely.<br>+ */<br> #define LPC_WIDEIO_GENERIC_PORT 0x64<br>+#define LPC_WIDEIO1_GENERIC_PORT 0x66<br>+#define ROM_ADDRESS_RANGE1_START 0x68<br>+#define ROM_ADDRESS_RANGE1_END 0x6a<br>+#define ROM_ADDRESS_RANGE2_START 0x6c<br>+#define ROM_ADDRESS_RANGE2_END 0x6e<br> <br> #define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74<br> #define LPC_ALT_WIDEIO2_ENABLE BIT(3)<br> #define LPC_ALT_WIDEIO1_ENABLE BIT(2)<br> #define LPC_ALT_WIDEIO0_ENABLE BIT(0)<br> <br>+#define LPC_MISC_CONTROL_BITS 0x78<br>+#define LPC_NOHOG BIT(0)<br>+<br> #define LPC_WIDEIO2_GENERIC_PORT 0x90<br>+<br>+/* LPC register 0xb8 is DWORD, here there are definition for byte<br>+ * access. For example, bits 31-24 are accessed through byte access<br>+ * at register 0xbb ().<br>+ */<br>+#define LPC_ROM_DMA_EC_HOST_CONTROL 0xb8<br>+<br>+#define LPC_HOST_CONTROL 0xbb<br>+#define SPI_FROM_HOST_PREFETCH_EN BIT(0)<br> <br> #define SPI_CNTRL0 0x00<br> #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))<br>@@ -165,6 +328,10 @@<br> #define SPI100_HOST_PREF_CONFIG 0x2c<br> #define SPI_RD4DW_EN_HOST BIT(15)<br> <br>+#define FCH_MISC_REG40_OSCOUT1_EN BIT(2)<br>+<br>+#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)<br>+<br> static inline int sb_sata_enable(void)<br> {<br> /* True if IDE or AHCI. */<br>diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c<br>index 9865191..f0dfd77 100644<br>--- a/src/soc/amd/stoneyridge/smihandler.c<br>+++ b/src/soc/amd/stoneyridge/smihandler.c<br>@@ -12,9 +12,8 @@<br> #include <amdblocks/psp_smm.h><br> #include <soc/smi.h><br> #include <soc/southbridge.h><br>-<br>-<br>-#define SMI_0x88_ACPI_COMMAND (1 << 11)<br>+#include <elog.h><br>+#include <arch/acpi.h><br> <br> enum smi_source {<br> SMI_SOURCE_SCI = (1 << 0),<br>@@ -24,6 +23,28 @@<br> SMI_SOURCE_IRQ_TRAP = (1 << 4),<br> SMI_SOURCE_0x90 = (1 << 5)<br> };<br>+<br>+<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>+static void southbridge_smi_gsmi(void)<br>+{<br>+ amd64_smm_state_save_area_t *state_save =<br>+ (amd64_smm_state_save_area_t *)SMM_AMD64_SAVE_STATE_OFFSET;<br>+ u32 *ret, *param;<br>+ uint8_t sub_command;<br>+<br>+ /* Command and return value in EAX */<br>+ ret = (u32 *)&state_save->rax;<br>+ sub_command = (uint8_t)(*ret >> 8);<br>+<br>+ /* Parameter buffer in EBX */<br>+ param = (u32 *)&state_save->rbx;<br>+<br>+ /* drivers/elog/gsmi.c */<br>+ *ret = gsmi_exec(sub_command, param);<br>+}<br>+#endif<br>+<br> <br> static void sb_apmc_smi_handler(void)<br> {<br>@@ -41,8 +62,12 @@<br> reg32 &= ~(1 << 0); /* clear SCI_EN */<br> outl(ACPI_PM1_CNT_BLK, reg32);<br> break;<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>+ case ELOG_GSMI_APM_CNT:<br>+ southbridge_smi_gsmi();<br>+ break;<br>+#endif<br> }<br>-<br> mainboard_smi_apmc(cmd);<br> }<br> <br>@@ -53,15 +78,15 @@<br> <br> static void process_smi_sci(void)<br> {<br>- const uint32_t status = smi_read32(0x10);<br>+ const uint32_t status = smi_read32(SMI_REG_SCI_STATUS);<br> <br> /* Clear events to prevent re-entering SMI if event isn't handled */<br>- smi_write32(0x10, status);<br>+ smi_write32(SMI_REG_SCI_STATUS, status);<br> }<br> <br> static void process_gpe_smi(void)<br> {<br>- const uint32_t status = smi_read32(0x80);<br>+ const uint32_t status = smi_read32(SMI_REG_SMISTAT0);<br> const uint32_t gevent_mask = (1 << 24) - 1;<br> <br> /* Only Bits [23:0] indicate GEVENT SMIs. */<br>@@ -71,52 +96,79 @@<br> }<br> <br> /* Clear events to prevent re-entering SMI if event isn't handled */<br>- smi_write32(0x80, status);<br>+ smi_write32(SMI_REG_SMISTAT0, status);<br> }<br> <br> static void process_smi_0x84(void)<br> {<br>- const uint32_t status = smi_read32(0x84);<br>+ const uint32_t status = smi_read32(SMI_REG_SMISTAT1);<br> <br> /* Clear events to prevent re-entering SMI if event isn't handled */<br>- smi_write32(0x84, status);<br>+ smi_write32(SMI_REG_SMISTAT1, status);<br> }<br>+<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>+static u8 smi_get_slp_typ(void)<br>+{<br>+ u32 reg32;<br>+<br>+ reg32 = inl(ACPI_PM1_CNT_BLK);<br>+ return (reg32 >> 10) & 0x03;<br>+}<br>+#endif<br> <br> static void process_smi_0x88(void)<br> {<br>- const uint32_t status = smi_read32(0x88);<br>+ const uint32_t status = smi_read32(SMI_REG_SMISTAT2);<br> <br>- if (status & SMI_0x88_ACPI_COMMAND) {<br>+ if (status & SMISTAT2_ACPI_CMD) {<br> /* Command received via ACPI SMI command port */<br> sb_apmc_smi_handler();<br> }<br>+<br>+ if (status & SMISTAT2_PWRBTN) {<br>+ /* Power Button pressed */<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>+ elog_add_event(ELOG_TYPE_POWER_BUTTON);<br>+#endif<br>+ }<br>+<br>+ if (status & SMISTAT2_SLPTYP) {<br>+ /* Sleep Type */<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>+ /* Log S3, S4, and S5 entry */<br>+ u8 slp_typ = smi_get_slp_typ();<br>+ if (slp_typ >= ACPI_S3)<br>+ elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);<br>+#endif<br>+ }<br>+<br> /* Clear events to prevent re-entering SMI if event isn't handled */<br>- smi_write32(0x88, status);<br>+ smi_write32(SMI_REG_SMISTAT2, status);<br> }<br> <br> static void process_smi_0x8c(void)<br> {<br>- const uint32_t status = smi_read32(0x8c);<br>+ const uint32_t status = smi_read32(SMI_REG_SMISTAT3);<br> <br> /* Clear events to prevent re-entering SMI if event isn't handled */<br>- smi_write32(0x8c, status);<br>+ smi_write32(SMI_REG_SMISTAT3, status);<br> }<br> <br> static void process_smi_0x90(void)<br> {<br>- const uint32_t status = smi_read32(0x90);<br>+ const uint32_t status = smi_read32(SMI_REG_SMISTAT4);<br> <br> /* Check for PSP mailbox initialization */<br>- if (status & SMISTAT4_MEMTRAP_EVT) {<br>+ if (status & SMISTAT4_MEMTRAP)<br> psp_smm_init(status);<br>- }<br> <br> /* Check for PSP mailbox event */<br> if (status & SMISTAT4_FAKESMI_0)<br> psp_p2cmbox_event(status);<br> <br> /* Clear events to prevent re-entering SMI if event isn't handled */<br>- smi_write32(0x90, status);<br>+ smi_write32(SMI_REG_SMISTAT4, status);<br> }<br> <br> void smm_southbridge_clear_state(void)<br>@@ -139,7 +191,7 @@<br> <br> void southbridge_smi_handler(void)<br> {<br>- const uint16_t smi_src = smi_read16(0x94);<br>+ const uint16_t smi_src = smi_read16(SMI_REG_SMI_POINTER);<br> <br> if (smi_src & SMI_SOURCE_SCI)<br> process_smi_sci();<br></pre><p>To view, visit <a href="https://review.coreboot.org/21728">change 21728</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21728"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I458babe1694f042215dd0e1c3277856e340de86f </div>
<div style="display:none"> Gerrit-Change-Number: 21728 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: John E. Kabat Jr. <john.kabat@scarletltd.com> </div>