<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21741">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Use generic SMM command port values<br><br>Remove the old Hudson-specific SMM command port definitions and use the<br>ones in cpu/x86/smm.h.<br><br>Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/acpi.c<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/smihandler.c<br>M src/soc/amd/stoneyridge/southbridge.c<br>4 files changed, 9 insertions(+), 16 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/21741/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c<br>index 78fd4b7..e6e785c 100644<br>--- a/src/soc/amd/stoneyridge/acpi.c<br>+++ b/src/soc/amd/stoneyridge/acpi.c<br>@@ -24,13 +24,13 @@<br> #include <arch/acpigen.h><br> #include <arch/io.h><br> #include <arch/ioapic.h><br>+#include <cpu/x86/smm.h><br> #include <cbmem.h><br> #include <device/device.h><br> #include <device/pci.h><br> #include <soc/acpi.h><br> #include <soc/southbridge.h><br> #include <soc/nvs.h><br>-#include <soc/smi.h><br> <br> unsigned long acpi_fill_madt(unsigned long current)<br> {<br>@@ -88,9 +88,9 @@<br> fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */<br> <br> if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {<br>- fadt->smi_cmd = ACPI_SMI_CTL_PORT;<br>- fadt->acpi_enable = ACPI_SMI_CMD_ENABLE;<br>- fadt->acpi_disable = ACPI_SMI_CMD_DISABLE;<br>+ fadt->smi_cmd = APM_CNT;<br>+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;<br>+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;<br> fadt->s4bios_req = 0; /* Not supported */<br> fadt->pstate_cnt = 0; /* Not supported */<br> fadt->cst_cnt = 0; /* Not supported */<br>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>index 20edf5f..9f353fb 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>@@ -66,13 +66,6 @@<br> #define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */<br> #define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */<br> <br>-#define ACPI_SMI_CTL_PORT 0xb2<br>-#define ACPI_SMI_CMD_CST_CONTROL 0xde<br>-#define ACPI_SMI_CMD_PST_CONTROL 0xad<br>-#define ACPI_SMI_CMD_DISABLE 0xbe<br>-#define ACPI_SMI_CMD_ENABLE 0xef<br>-#define ACPI_SMI_CMD_S4_REQ 0xc0<br>-<br> #define REV_STONEYRIDGE_A11 0x11<br> #define REV_STONEYRIDGE_A12 0x12<br> <br>diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c<br>index 9aff690..45dada5 100644<br>--- a/src/soc/amd/stoneyridge/smihandler.c<br>+++ b/src/soc/amd/stoneyridge/smihandler.c<br>@@ -27,15 +27,15 @@<br> static void sb_apmc_smi_handler(void)<br> {<br> u32 reg32;<br>- const uint8_t cmd = inb(ACPI_SMI_CTL_PORT);<br>+ const uint8_t cmd = inb(APM_CNT);<br> <br> switch (cmd) {<br>- case ACPI_SMI_CMD_ENABLE:<br>+ case APM_CNT_ACPI_ENABLE:<br> reg32 = inl(ACPI_PM1_CNT_BLK);<br> reg32 |= (1 << 0); /* SCI_EN */<br> outl(reg32, ACPI_PM1_CNT_BLK);<br> break;<br>- case ACPI_SMI_CMD_DISABLE:<br>+ case APM_CNT_ACPI_DISABLE:<br> reg32 = inl(ACPI_PM1_CNT_BLK);<br> reg32 &= ~(1 << 0); /* clear SCI_EN */<br> outl(ACPI_PM1_CNT_BLK, reg32);<br>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c<br>index 5e36100..1ca742f 100644<br>--- a/src/soc/amd/stoneyridge/southbridge.c<br>+++ b/src/soc/amd/stoneyridge/southbridge.c<br>@@ -18,7 +18,7 @@<br> #include <arch/io.h><br> #include <arch/acpi.h><br> #include <bootstate.h><br>-<br>+#include <cpu/x86/smm.h><br> #include <device/device.h><br> #include <device/pci.h><br> #include <device/pci_ids.h><br>@@ -79,7 +79,7 @@<br> pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);<br> <br> if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {<br>- pm_write16(PM_ACPI_SMI_CMD, ACPI_SMI_CTL_PORT);<br>+ pm_write16(PM_ACPI_SMI_CMD, APM_CNT);<br> enable_acpi_cmd_smi();<br> } else {<br> pm_write16(PM_ACPI_SMI_CMD, 0);<br></pre><p>To view, visit <a href="https://review.coreboot.org/21741">change 21741</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21741"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f </div>
<div style="display:none"> Gerrit-Change-Number: 21741 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>