<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21749">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge<br><br>Duplicate existing pm_read and pm_write and create 32-bit register<br>access functions.<br><br>Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 12 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/21749/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>index 054b36a..09dfb54 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>@@ -195,8 +195,10 @@<br> void lpc_wideio_16_window(uint16_t base);<br> u8 pm_read8(u8 reg);<br> u16 pm_read16(u8 reg);<br>+u32 pm_read32(u8 reg);<br> void pm_write8(u8 reg, u8 value);<br> void pm_write16(u8 reg, u16 value);<br>+void pm_write32(u8 reg, u32 value);<br> int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);<br> void s3_resume_init_data(void *FchParams);<br> int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);<br>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c<br>index 655a15a..a829575 100644<br>--- a/src/soc/amd/stoneyridge/southbridge.c<br>+++ b/src/soc/amd/stoneyridge/southbridge.c<br>@@ -60,6 +60,16 @@<br>        return read16((void *)(PM_MMIO_BASE + reg));<br> }<br> <br>+void pm_write32(u8 reg, u32 value)<br>+{<br>+ write32((void *)(PM_MMIO_BASE + reg), value);<br>+}<br>+<br>+u32 pm_read32(u8 reg)<br>+{<br>+     return read32((void *)(PM_MMIO_BASE + reg));<br>+}<br>+<br> void sb_enable(device_t dev)<br> {<br>        printk(BIOS_DEBUG, "%s\n", __func__);<br></pre><p>To view, visit <a href="https://review.coreboot.org/21749">change 21749</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21749"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979 </div>
<div style="display:none"> Gerrit-Change-Number: 21749 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>