<p>Naresh Solanki has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21701">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">arch/x86: CAR setup CQOS<br><br>Enable CQOS on Geminilake.<br><br>In Appololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF.<br><br>Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK.<br><br>Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right<br>bits.<br><br>BUG=None<br>TEST= Build for Geminilake platform i.e., glkrvp & check for successful<br>CAR setup. Even verified the same on APL platfrom i.e., on Reef<br><br>Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9<br>Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com<br>---<br>M src/soc/intel/common/block/cpu/car/cache_as_ram.S<br>1 file changed, 29 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/21701/4</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S<br>index 94e2694..9475c8c 100644<br>--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S<br>+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S<br>@@ -255,6 +255,25 @@<br> .global car_cqos<br> car_cqos:<br> /*<br>+ * Create CBM_LEN_MASK based on CBM_LEN<br>+ * Get CPUID.(EAX=10H, ECX=2H):EAX.CBM_LEN[bits 4:0]<br>+ */<br>+ mov $0x10, %eax<br>+ mov $0x2, %ecx<br>+ cpuid<br>+ and $0xF, %eax<br>+ add $1, %al<br>+<br>+ mov $1, %ebx<br>+ xor %ecx, %ecx<br>+ mov %al, %cl<br>+ shl %cl, %ebx<br>+ sub $1, %ebx<br>+<br>+ /* Store the CBM_LEN_MASK in mm3 for later use. */<br>+ movd %ebx, %mm3<br>+<br>+ /*<br> * Disable both L1 and L2 prefetcher. For yet-to-understood reason,<br> * prefetchers slow down filling cache with rep stos in CQOS mode.<br> */<br>@@ -284,7 +303,7 @@<br> /* Set this mask for initial cache fill */<br> mov $MSR_L2_QOS_MASK(0), %ecx<br> rdmsr<br>- mov %bl, %al<br>+ mov %ebx, %eax<br> wrmsr<br> <br> /* Set CLOS selector to 0 */<br>@@ -297,8 +316,15 @@<br> mov $MSR_L2_QOS_MASK(1), %ecx<br> rdmsr<br> /* Invert bits that are to be used for cache */<br>- mov %bl, %al<br>- xor $~0, %al /* invert 8 bits */<br>+ mov %ebx, %eax<br>+ xor $~0, %eax /* invert 32 bits */<br>+<br>+ /*<br>+ * Use CBM_LEN_MASK stored in mm3 to set bits based on Capacity Bit<br>+ * Mask Length.<br>+ */<br>+ movd %mm3, %ebx<br>+ and %ebx, %eax<br> wrmsr<br> <br> post_code(0x26)<br></pre><p>To view, visit <a href="https://review.coreboot.org/21701">change 21701</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21701"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9 </div>
<div style="display:none"> Gerrit-Change-Number: 21701 </div>
<div style="display:none"> Gerrit-PatchSet: 4 </div>
<div style="display:none"> Gerrit-Owner: Naresh Solanki <naresh.solanki@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: AndreX Andraos <andrex.andraos@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>