<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21742">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Add more SMM definitions<br><br>Change-Id: I4c8069a18ea430ec6e66d41879c8e77f1ef2b340<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/smi.h<br>1 file changed, 174 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/21742/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h<br>index 46004c9..c024c08 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/smi.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/smi.h<br>@@ -1,8 +1,17 @@<br> /*<br>- * Utilities for SMI handlers and SMM setup<br>+ * This file is part of the coreboot project.<br> *<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br> * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com><br>- * Subject to the GNU GPL v2, or (at your option) any later version.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br> */<br> <br> #ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__<br>@@ -10,17 +19,170 @@<br> <br> #include <arch/io.h><br> <br>-/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it.<br>- * This is defined by AGESA, but we dpn't include AGESA headers to avoid<br>- * polluting the namesace.<br>- */<br>-#define SMI_BASE 0xfed80200<br>+/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it. */<br>+#define SMI_BASE 0xfed80200<br> <br>-#define SMI_REG_SMITRIG0 0x98<br>-#define SMITRG0_EOS (1 << 28)<br>-#define SMITRG0_SMIENB (1 << 31)<br>+#define SMI_SCI_STATUS 0x10<br> <br>-#define SMI_REG_CONTROL0 0xa0<br>+/* SMI source and status */<br>+#define SMITYPE_AGPIO65 0<br>+#define SMITYPE_AGPIO66 1<br>+#define SMITYPE_AGPIO3 2<br>+#define SMITYPE_LPCPME_AGPIO22 3<br>+#define SMITYPE_GPIO4 4<br>+#define SMITYPE_LPCPD_AGPIOG21 5<br>+#define SMITYPE_IRTX1_G15 6<br>+#define SMITYPE_AGPIO5_DEVSLP0 7<br>+#define SMITYPE_WAKE_AGPIO2 8<br>+#define SMITYPE_APIO68_SGPIOCLK 9<br>+#define SMITYPE_AGPIO6 10<br>+#define SMITYPE_GPIO7 11<br>+#define SMITYPE_USBOC0_TRST_AGPIO16 12<br>+#define SMITYPE_USB0C1_TDI_AGPIO17 13<br>+#define SMITYPE_USBOC2_TCK_AGPIO18 14<br>+#define SMITYPE_TDO_USB0C3_AGPIO24 15<br>+#define SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23 16<br>+/* 17 Reserved */<br>+#define SMITYPE_BLINK_AGPIO11_USBOC7 18<br>+#define SMITYPE_SYSRESET_AGPIO1 19<br>+#define SMITYPE_IRRX1_AGPIO15 20<br>+#define SMITYPE_IRTX0_USBOC5_AGPIO13 21<br>+#define SMITYPE_GPIO9_SERPORTRX 22<br>+#define SMITYPE_GPIO8_SEPORTTX 23<br>+#define GEVENT_MASK ((1 << SMITYPE_AGPIO65) \<br>+ | (1 << SMITYPE_AGPIO66) \<br>+ | (1 << SMITYPE_AGPIO3) \<br>+ | (1 << SMITYPE_LPCPME_AGPIO22) \<br>+ | (1 << SMITYPE_GPIO4) \<br>+ | (1 << SMITYPE_LPCPD_AGPIOG21) \<br>+ | (1 << SMITYPE_IRTX1_G15) \<br>+ | (1 << SMITYPE_AGPIO5_DEVSLP0) \<br>+ | (1 << SMITYPE_WAKE_AGPIO2) \<br>+ | (1 << SMITYPE_APIO68_SGPIOCLK) \<br>+ | (1 << SMITYPE_AGPIO6) \<br>+ | (1 << SMITYPE_GPIO7) \<br>+ | (1 << SMITYPE_USBOC0_TRST_AGPIO16) \<br>+ | (1 << SMITYPE_USB0C1_TDI_AGPIO17) \<br>+ | (1 << SMITYPE_USBOC2_TCK_AGPIO18) \<br>+ | (1 << SMITYPE_TDO_USB0C3_AGPIO24) \<br>+ | (1 << SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23) \<br>+ | (1 << SMITYPE_BLINK_AGPIO11_USBOC7) \<br>+ | (1 << SMITYPE_SYSRESET_AGPIO1) \<br>+ | (1 << SMITYPE_IRRX1_AGPIO15) \<br>+ | (1 << SMITYPE_IRTX0_USBOC5_AGPIO13) \<br>+ | (1 << SMITYPE_GPIO9_SERPORTRX))<br>+#define SMITYPE_EHCI0_WAKE 24<br>+#define SMITYPE_EHCI1_WAKE 25<br>+#define SMITYPE_ESPI_SYS 26<br>+#define SMITYPE_ESPI_WAKE_PME 27<br>+/* 28-32 Reserved */<br>+#define SMITYPE_FCH_FAKE0 33<br>+#define SMITYPE_FCH_FAKE1 34<br>+#define SMITYPE_FCH_FAKE2 35<br>+/* 36 Reserved */<br>+#define SMITYPE_SATA_GEVENT0 37<br>+#define SMITYPE_SATA_GEVENT1 38<br>+#define SMITYPE_ACP_WAKE 39<br>+#define SMITYPE_ECG 40<br>+#define SMITYPE_GPIO_CTL 41<br>+#define SMITYPE_CIR_PME 42<br>+#define SMITYPE_ALT_HPET_ALARM 43<br>+#define SMITYPE_FAN_THERMAL 44<br>+#define SMITYPE_ASF_MASTER_SLAVE 45<br>+#define SMITYPE_I2S_WAKE 46<br>+#define SMITYPE_SMBUS0_MASTER 47<br>+#define SMITYPE_TWARN 48<br>+#define SMITYPE_TRAFFIC_MON 49<br>+#define SMITYPE_ILLB 50<br>+#define SMITYPE_PWRBUTTON_UP 51<br>+#define SMITYPE_PROCHOT 52<br>+#define SMITYPE_APU_HW 53<br>+#define SMITYPE_NB_SCI 54<br>+#define SMITYPE_RAS_SERR 55<br>+#define SMITYPE_XHC0_PME 56<br>+/* 57 Reserved */<br>+#define SMITYPE_ACDC_TIMER 58<br>+/* 59-62 Reserved */<br>+#define SMITYPE_TEMP_TSI 63<br>+#define SMITYPE_KB_RESET 64<br>+#define SMITYPE_SLP_TYP 65<br>+#define SMITYPE_AL2H_ACPI 66<br>+#define SMITYPE_AHCI 67<br>+/* 68-71 Reserved */<br>+#define SMITYPE_GBL_RLS 72<br>+#define SMITYPE_BIOS_RLS 73<br>+#define SMITYPE_PWRBUTTON_DOWN 74<br>+#define SMITYPE_SMI_CMD_PORT 75<br>+#define SMITYPE_USB_SMI 76<br>+#define SMITYPE_SERIRQ 77<br>+#define SMITYPE_SMBUS0_INTR 78<br>+#define SMITYPE_IMC 79<br>+#define SMITYPE_XHC_ERROR 80<br>+#define SMITYPE_INTRUDER 81<br>+#define SMITYPE_VBAT_LOW 82<br>+#define SMITYPE_PROTHOT 83<br>+#define SMITYPE_PCI_SERR 84<br>+#define SMITYPE_GPP_SERR 85<br>+/* 85-88 Reserved */<br>+#define SMITYPE_TMERTRIP 89<br>+#define SMITYPE_EMUL60_64 90<br>+#define SMITYPE_USB_FLR 91<br>+#define SMITYPE_SATA_FLR 92<br>+#define SMITYPE_AZ_FLR 93<br>+/* 94-132 Reserved */<br>+#define SMITYPE_FANIN0 133<br>+/* 134-137 Reserved */<br>+#define SMITYPE_FAKE0 138<br>+#define SMITYPE_FAKE1 139<br>+#define SMITYPE_FAKE2 140<br>+/* 141 Reserved */<br>+#define SMITYPE_SHORT_TIMER 142<br>+#define SMITYPE_LONG_TIMER 143<br>+#define SMITYPE_AB_SMI 144<br>+#define SMITYPE_SOFT_RESET 145<br>+/* 146-147 Reserved */<br>+#define SMITYPE_IOTRAP0 148<br>+/* 149-151 Reserved */<br>+#define SMITYPE_MEMTRAP0 152<br>+/* 153-155 Reserved */<br>+#define SMITYPE_CFGTRAP0 156<br>+/* 157-159 Reserved */<br>+#define NUMBER_SMITYPES 160<br>+#define TYPE_TO_MASK(X) (1 << (X) % 32)<br>+<br>+#define SMI_REG_SMISTS0 0x80<br>+#define SMI_REG_SMISTS1 0x84<br>+#define SMI_REG_SMISTS2 0x88<br>+#define SMI_REG_SMISTS3 0x8c<br>+#define SMI_REG_SMISTS4 0x90<br>+<br>+#define SMI_REG_POINTER 0x94<br>+# define SMI_STATUS_SRC_SCI (1 << 0)<br>+# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */<br>+# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */<br>+# define SMI_STATUS_SRC_2 (1 << 3)<br>+# define SMI_STATUS_SRC_3 (1 << 4)<br>+# define SMI_STATUS_SRC_4 (1 << 5)<br>+<br>+#define SMI_TIMER 0x96<br>+#define SMI_TIMER_MASK 0x7fff<br>+#define SMI_TIMER_EN (1 << 15)<br>+<br>+#define SMI_REG_SMITRIG0 0x98<br>+# define SMITRG0_EOS (1 << 28)<br>+# define SMI_TIMER_SEL (1 << 29)<br>+# define SMITRG0_SMIENB (1 << 31)<br>+<br>+#define SMI_REG_CONTROL0 0xa0<br>+#define SMI_REG_CONTROL1 0xa4<br>+#define SMI_REG_CONTROL2 0xa8<br>+#define SMI_REG_CONTROL3 0xac<br>+#define SMI_REG_CONTROL4 0xb0<br>+#define SMI_REG_CONTROL5 0xb4<br>+#define SMI_REG_CONTROL6 0xb8<br>+#define SMI_REG_CONTROL7 0xbc<br>+#define SMI_REG_CONTROL8 0xc0<br>+#define SMI_REG_CONTROL9 0xc4<br> <br> enum smi_mode {<br> SMI_MODE_DISABLE = 0,<br>@@ -54,6 +216,7 @@<br> write16((void *)(SMI_BASE + offset), value);<br> }<br> <br>+uint16_t pm_acpi_smi_cmd_port(void);<br> void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);<br> void disable_gevent_smi(uint8_t gevent);<br> void enable_acpi_cmd_smi(void);<br></pre><p>To view, visit <a href="https://review.coreboot.org/21742">change 21742</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21742"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4c8069a18ea430ec6e66d41879c8e77f1ef2b340 </div>
<div style="display:none"> Gerrit-Change-Number: 21742 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>