<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21704">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/cyan: fix variant memory/silicon init params overrride<br><br>The mainboard_memory_init_params() and mainboard_silicon_init_params()<br>methods already have weak declarations in drivers/intel/fsp1_1,<br>so having them declared as weak in the cyan baseboard has the effect<br>of them not being called at all unless overriden at the variant level.<br>Therefore, remove the weak declarations in the baseboard and ensure<br>that each variant has its own init functions if needed.<br><br>TEST: build/boot google/cyan<br><br>Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/google/cyan/ramstage.c<br>M src/mainboard/google/cyan/romstage.c<br>M src/mainboard/google/cyan/variants/celes/Makefile.inc<br>A src/mainboard/google/cyan/variants/celes/romstage.c<br>M src/mainboard/google/cyan/variants/cyan/Makefile.inc<br>A src/mainboard/google/cyan/variants/cyan/romstage.c<br>M src/mainboard/google/cyan/variants/edgar/Makefile.inc<br>A src/mainboard/google/cyan/variants/edgar/romstage.c<br>M src/mainboard/google/cyan/variants/reks/Makefile.inc<br>A src/mainboard/google/cyan/variants/reks/romstage.c<br>10 files changed, 112 insertions(+), 21 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/21704/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c<br>index 093a49b..1da5b44 100644<br>--- a/src/mainboard/google/cyan/ramstage.c<br>+++ b/src/mainboard/google/cyan/ramstage.c<br>@@ -12,10 +12,3 @@<br> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br> * GNU General Public License for more details.<br> */<br>-<br>-#include <soc/ramstage.h><br>-<br>-__attribute__ ((weak))<br>-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)<br>-{<br>-}<br>diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c<br>index 57c40e0..39088bb 100644<br>--- a/src/mainboard/google/cyan/romstage.c<br>+++ b/src/mainboard/google/cyan/romstage.c<br>@@ -15,7 +15,6 @@<br> */<br> <br> #include <soc/romstage.h><br>-#include <chip.h><br> <br> /* All FSP specific code goes in this block */<br> void mainboard_romstage_entry(struct romstage_params *rp)<br>@@ -26,17 +25,4 @@<br> <br> /* Call back into chipset code with platform values updated. */<br> romstage_common(rp);<br>-}<br>-<br>-__attribute__ ((weak))<br>-void mainboard_memory_init_params(struct romstage_params *params,<br>- MEMORY_INIT_UPD *memory_params)<br>-{<br>- /* Update SPD data */<br>- if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {<br>- memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;<br>- }<br>- memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;<br>- memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;<br>- memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;<br> }<br>diff --git a/src/mainboard/google/cyan/variants/celes/Makefile.inc b/src/mainboard/google/cyan/variants/celes/Makefile.inc<br>index 0fcc9ad..23d2c72 100644<br>--- a/src/mainboard/google/cyan/variants/celes/Makefile.inc<br>+++ b/src/mainboard/google/cyan/variants/celes/Makefile.inc<br>@@ -14,6 +14,7 @@<br> ## GNU General Public License for more details.<br> ##<br> <br>+romstage-y += romstage.c<br> romstage-y += spd_util.c<br> <br> ramstage-y += gpio.c<br>diff --git a/src/mainboard/google/cyan/variants/celes/romstage.c b/src/mainboard/google/cyan/variants/celes/romstage.c<br>new file mode 100644<br>index 0000000..b720e3d<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/celes/romstage.c<br>@@ -0,0 +1,27 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Google Inc.<br>+ * Copyright (C) 2015 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <soc/romstage.h><br>+#include <chip.h><br>+<br>+void mainboard_memory_init_params(struct romstage_params *params,<br>+ MEMORY_INIT_UPD *memory_params)<br>+{<br>+ memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;<br>+ memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;<br>+ memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;<br>+ memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;<br>+}<br>diff --git a/src/mainboard/google/cyan/variants/cyan/Makefile.inc b/src/mainboard/google/cyan/variants/cyan/Makefile.inc<br>index ea80446..76de7be 100644<br>--- a/src/mainboard/google/cyan/variants/cyan/Makefile.inc<br>+++ b/src/mainboard/google/cyan/variants/cyan/Makefile.inc<br>@@ -14,6 +14,7 @@<br> ## GNU General Public License for more details.<br> ##<br> <br>+romstage-y += romstage.c<br> romstage-y += spd_util.c<br> <br> ramstage-y += gpio.c<br>diff --git a/src/mainboard/google/cyan/variants/cyan/romstage.c b/src/mainboard/google/cyan/variants/cyan/romstage.c<br>new file mode 100644<br>index 0000000..717db35<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/cyan/romstage.c<br>@@ -0,0 +1,27 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Google Inc.<br>+ * Copyright (C) 2015 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <soc/romstage.h><br>+#include <chip.h><br>+<br>+void mainboard_memory_init_params(struct romstage_params *params,<br>+ MEMORY_INIT_UPD *memory_params)<br>+{<br>+ memory_params->PcdMemoryTypeEnable = MEM_DDR3;<br>+ memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;<br>+ memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;<br>+ memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;<br>+}<br>diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc<br>index e553c88..d9a7c7b 100644<br>--- a/src/mainboard/google/cyan/variants/edgar/Makefile.inc<br>+++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc<br>@@ -14,6 +14,7 @@<br> ## GNU General Public License for more details.<br> ##<br> <br>+romstage-y += romstage.c<br> romstage-y += spd_util.c<br> <br> ramstage-y += gpio.c<br>diff --git a/src/mainboard/google/cyan/variants/edgar/romstage.c b/src/mainboard/google/cyan/variants/edgar/romstage.c<br>new file mode 100644<br>index 0000000..b720e3d<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/edgar/romstage.c<br>@@ -0,0 +1,27 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Google Inc.<br>+ * Copyright (C) 2015 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <soc/romstage.h><br>+#include <chip.h><br>+<br>+void mainboard_memory_init_params(struct romstage_params *params,<br>+ MEMORY_INIT_UPD *memory_params)<br>+{<br>+ memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;<br>+ memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;<br>+ memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;<br>+ memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;<br>+}<br>diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc<br>index 6577124..db2eea3 100644<br>--- a/src/mainboard/google/cyan/variants/reks/Makefile.inc<br>+++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc<br>@@ -14,6 +14,7 @@<br> ## GNU General Public License for more details.<br> ##<br> <br>+romstage-y += romstage.c<br> romstage-y += spd_util.c<br> <br> ramstage-y += gpio.c<br>diff --git a/src/mainboard/google/cyan/variants/reks/romstage.c b/src/mainboard/google/cyan/variants/reks/romstage.c<br>new file mode 100644<br>index 0000000..b720e3d<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/reks/romstage.c<br>@@ -0,0 +1,27 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Google Inc.<br>+ * Copyright (C) 2015 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <soc/romstage.h><br>+#include <chip.h><br>+<br>+void mainboard_memory_init_params(struct romstage_params *params,<br>+ MEMORY_INIT_UPD *memory_params)<br>+{<br>+ memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;<br>+ memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;<br>+ memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;<br>+ memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21704">change 21704</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21704"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b </div>
<div style="display:none"> Gerrit-Change-Number: 21704 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>