<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21716">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Remove direct AGESA header includes<br><br>All AGESA headers should be included only through agesawrapper.h<br><br>Change-Id: Iadc516e11148048ed9bf43c7a46827793245027a<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/soc/amd/stoneyridge/dimmSpd.c<br>M src/soc/amd/stoneyridge/early_setup.c<br>M src/soc/amd/stoneyridge/imc.c<br>M src/soc/amd/stoneyridge/include/fchec.h<br>M src/soc/amd/stoneyridge/northbridge.c<br>M src/soc/amd/stoneyridge/smbus_spd.c<br>6 files changed, 7 insertions(+), 23 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/21716/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/dimmSpd.c b/src/soc/amd/stoneyridge/dimmSpd.c<br>index ace22bb..f306cf9 100644<br>--- a/src/soc/amd/stoneyridge/dimmSpd.c<br>+++ b/src/soc/amd/stoneyridge/dimmSpd.c<br>@@ -16,12 +16,8 @@<br> #include <device/pci_def.h><br> #include <device/device.h><br> #include <stdlib.h><br>-<br>-/* warning: Porting.h includes an open #pragma pack(1) */<br>-#include <Porting.h><br>-#include <AGESA.h><br>-#include <amdlib.h><br> #include "chip.h"<br>+#include <agesawrapper.h><br> #include <dimmSpd.h><br> <br> AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2,<br>diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c<br>index 5166a7f..cb4183c 100644<br>--- a/src/soc/amd/stoneyridge/early_setup.c<br>+++ b/src/soc/amd/stoneyridge/early_setup.c<br>@@ -23,7 +23,7 @@<br> #include <cbmem.h><br> #include <soc/southbridge.h><br> #include <soc/pci_devs.h><br>-#include <Fch/Fch.h><br>+#include <agesawrapper.h><br> #include <cpu/x86/msr.h><br> #include <delay.h><br> <br>diff --git a/src/soc/amd/stoneyridge/imc.c b/src/soc/amd/stoneyridge/imc.c<br>index e7c6fac..d3dc496 100644<br>--- a/src/soc/amd/stoneyridge/imc.c<br>+++ b/src/soc/amd/stoneyridge/imc.c<br>@@ -19,12 +19,7 @@<br> #include <arch/io.h><br> #include <device/device.h><br> #include <delay.h><br>-#include <Porting.h><br>-#include <AGESA.h><br>-#include <Lib/amdlib.h><br>-#include <Proc/Fch/Common/FchCommonCfg.h><br>-#include <Proc/Fch/Fch.h><br>-#include <Proc/Fch/FchPlatform.h><br>+#include <agesawrapper.h><br> <br> #define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE)<br> <br>diff --git a/src/soc/amd/stoneyridge/include/fchec.h b/src/soc/amd/stoneyridge/include/fchec.h<br>index acbc138..3409be9 100644<br>--- a/src/soc/amd/stoneyridge/include/fchec.h<br>+++ b/src/soc/amd/stoneyridge/include/fchec.h<br>@@ -17,9 +17,7 @@<br> #define __AMD_STONEY_FCHEC__<br> <br> #include <soc/imc.h><br>-#include "Porting.h"<br>-#include "AGESA.h"<br>-#include "FchCommonCfg.h"<br>+#include <agesawrapper.h><br> <br> extern VOID FchECfancontrolservice (IN VOID *FchDataPtr);<br> void agesawrapper_fchecfancontrolservice(void);<br>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c<br>index 049bcd0..796a0c9 100644<br>--- a/src/soc/amd/stoneyridge/northbridge.c<br>+++ b/src/soc/amd/stoneyridge/northbridge.c<br>@@ -39,10 +39,7 @@<br>  * AMD vendorcode files. Place at the end so coreboot defaults and maintained<br>  * and not set by vendorcode<br>  */<br>-#include <AGESA.h><br>-#include <FieldAccessors.h><br>-#include <Porting.h><br>-#include <Topology.h><br>+#include <agesawrapper.h><br> <br> typedef struct dram_base_mask {<br>    u32 base; /* [47:27] at [28:8] */<br>@@ -532,7 +529,7 @@<br>        }<br> <br>  /* Get max and actual number of cores */<br>-     pccount = cpuid_ecx(0x80000008);<br>+     pccount = cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT);<br>         core_max = 1 << ((pccount >> 12) & 0xf);<br>      core_nums = (pccount & 0xF);<br> <br>diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c<br>index 6669ccb..9ec7040 100644<br>--- a/src/soc/amd/stoneyridge/smbus_spd.c<br>+++ b/src/soc/amd/stoneyridge/smbus_spd.c<br>@@ -16,9 +16,7 @@<br> #include <device/pci_def.h><br> #include <device/device.h><br> <br>-/* warning: Porting.h includes an open #pragma pack(1) */<br>-#include <Porting.h><br>-#include <AGESA.h><br>+#include <agesawrapper.h><br> #include <amdlib.h><br> #include <soc/southbridge.h><br> #include <dimmSpd.h><br></pre><p>To view, visit <a href="https://review.coreboot.org/21716">change 21716</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21716"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iadc516e11148048ed9bf43c7a46827793245027a </div>
<div style="display:none"> Gerrit-Change-Number: 21716 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>