<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21705">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/fsp: Update CannonLake FSP header<br><br>Updated FSP header file to latest version 7.0.14.11<br><br>Change-Id: Iac8db8403b0f909f32049329f867c28c68e3b830<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h<br>3 files changed, 220 insertions(+), 195 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/21705/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>index 0e2bd99..fe9933f 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>@@ -41,8 +41,7 @@<br> #include <MemInfoHob.h><br> <br> ///<br>-/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS<br>-/// ChipsetInit CRC.<br>+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.<br> ///<br> typedef struct {<br> UINT8 Revision; ///< Chipset Init Info Revision<br>@@ -202,9 +201,10 @@<br> /** Offset 0x00AA - Platform Debug Consent<br> To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.<br> Enabling this BIOS option may alter the default value of other debug-related BIOS<br>- options. Note: DCI OOB (aka BSSB) uses CCA probe<br>- 0:Disabled, 1:Enabled (DCI OOB+DbC), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),<br>- 4:Enabled (XDP/MIPI60)<br>+ options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC]<br>+ have the same setting<br>+ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),<br>+ 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC)<br> **/<br> UINT8 PlatformDebugConsent;<br> <br>@@ -272,7 +272,7 @@<br> /** Offset 0x00BC - SA GV<br> System Agent dynamic frequency support and when enabled memory will be training<br> at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,<br>- 2=FixedHigh, and 3=Enabled.<br>+ 2=FixedMid, 3=FixedHigh, and 4=Enabled.<br> 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled<br> **/<br> UINT8 SaGv;<br>@@ -326,25 +326,25 @@<br> **/<br> UINT8 ScramblerSupport;<br> <br>-/** Offset 0x00C8 - MMA Test Content Pointer<br>- Pointer to MMA Test Content in Memory<br>+/** Offset 0x00C8 - EV Loader Test Content Pointer<br>+ Pointer to EV Loader Test Content in Memory<br> **/<br>- UINT32 MmaTestContentPtr;<br>+ UINT32 EvTestContentPtr;<br> <br>-/** Offset 0x00CC - MMA Test Content Size<br>- Size of MMA Test Content in Memory<br>+/** Offset 0x00CC - EV Loader Test Content Size<br>+ Size of EV Loader Test Content in Memory<br> **/<br>- UINT32 MmaTestContentSize;<br>+ UINT32 EvTestContentSize;<br> <br>-/** Offset 0x00D0 - MMA Test Config Pointer<br>- Pointer to MMA Test Config in Memory<br>+/** Offset 0x00D0 - EV Loader Test Config Pointer<br>+ Pointer to EV Loader Test Config in Memory<br> **/<br>- UINT32 MmaTestConfigPtr;<br>+ UINT32 EvTestConfigPtr;<br> <br>-/** Offset 0x00D4 - MMA Test Config Size<br>- Size of MMA Test Config in Memory<br>+/** Offset 0x00D4 - EV Loader Test Config Size<br>+ Size of EV Loader Test Config in Memory<br> **/<br>- UINT32 MmaTestConfigSize;<br>+ UINT32 EvTestConfigSize;<br> <br> /** Offset 0x00D8 - SPD Profile Selected<br> Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP<br>@@ -354,8 +354,8 @@<br> UINT8 SpdProfileSelected;<br> <br> /** Offset 0x00D9 - Memory Reference Clock<br>- Automatic, 100MHz, 133MHz.<br>- 0:Auto, 1:133MHz, 2:100MHz<br>+ 100MHz, 133MHz.<br>+ 0:133MHz, 1:100MHz<br> **/<br> UINT8 RefClk;<br> <br>@@ -702,7 +702,7 @@<br> UINT8 DmiGen3EndPointHint[8];<br> <br> /** Offset 0x0140 - DMI Gen3 RxCTLEp per-Bundle control<br>- Range: 0-15, 12 is default for each bundle, must be specified based upon platform design<br>+ Range: 0-15, 0 is default for each bundle, must be specified based upon platform design<br> **/<br> UINT8 DmiGen3RxCtlePeaking[4];<br> <br>@@ -713,45 +713,45 @@<br> /** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control<br> Range: 0-15, 12 is default for each bundle, must be specified based upon platform design<br> **/<br>- UINT8 PegGen3RxCtlePeaking[8];<br>+ UINT8 PegGen3RxCtlePeaking[10];<br> <br>-/** Offset 0x0150 - Memory data pointer for saved preset search results<br>+/** Offset 0x0152 - Memory data pointer for saved preset search results<br> The reference code will store the Gen3 Preset Search results in the SaDataHob's<br> PegData structure (SA_PEG_DATA) and platform code can save/restore this data to<br> skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0<br> **/<br> UINT32 PegDataPtr;<br> <br>-/** Offset 0x0154 - PEG PERST# GPIO information<br>+/** Offset 0x0156 - PEG PERST# GPIO information<br> The reference code will use the information in this structure in order to reset<br> PCIe Gen3 devices during equalization, if necessary<br> **/<br> UINT8 PegGpioData[28];<br> <br>-/** Offset 0x0170 - PCIe Hot Plug Enable/Disable per port<br>+/** Offset 0x0172 - PCIe Hot Plug Enable/Disable per port<br> 0(Default): Disable, 1: Enable<br> **/<br> UINT8 PegRootPortHPE[4];<br> <br>-/** Offset 0x0174 - DeEmphasis control for DMI<br>+/** Offset 0x0176 - DeEmphasis control for DMI<br> DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB<br> 0: -6dB, 1: -3.5dB<br> **/<br> UINT8 DmiDeEmphasis;<br> <br>-/** Offset 0x0175 - Selection of the primary display device<br>+/** Offset 0x0177 - Selection of the primary display device<br> 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics<br> 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics<br> **/<br> UINT8 PrimaryDisplay;<br> <br>-/** Offset 0x0176 - Selection of iGFX GTT Memory size<br>+/** Offset 0x0178 - Selection of iGFX GTT Memory size<br> 1=2MB, 2=4MB, 3=8MB, Default is 3<br> 1:2MB, 2:4MB, 3:8MB<br> **/<br> UINT16 GttSize;<br> <br>-/** Offset 0x0178 - Temporary MMIO address for GMADR<br>+/** Offset 0x017A - Temporary MMIO address for GMADR<br> The reference code will use this as Temporary MMIO address space to access GMADR<br> Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to<br> (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress<br>@@ -759,7 +759,7 @@<br> **/<br> UINT32 GmAdr;<br> <br>-/** Offset 0x017C - Temporary MMIO address for GTTMMADR<br>+/** Offset 0x017E - Temporary MMIO address for GTTMMADR<br> The reference code will use this as Temporary MMIO address space to access GTTMMADR<br> Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr<br> to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO<br>@@ -767,112 +767,111 @@<br> **/<br> UINT32 GttMmAdr;<br> <br>-/** Offset 0x0180 - Selection of PSMI Region size<br>+/** Offset 0x0182 - Selection of PSMI Region size<br> 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0<br> 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB<br> **/<br> UINT8 PsmiRegionSize;<br> <br>-/** Offset 0x0181 - Switchable Graphics GPIO information for PEG 0<br>+/** Offset 0x0183 - Switchable Graphics GPIO information for PEG 0<br> Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs<br> **/<br> UINT8 SaRtd3Pcie0Gpio[24];<br> <br>-/** Offset 0x0199 - Switchable Graphics GPIO information for PEG 1<br>+/** Offset 0x019B - Switchable Graphics GPIO information for PEG 1<br> Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs<br> **/<br> UINT8 SaRtd3Pcie1Gpio[24];<br> <br>-/** Offset 0x01B1 - Switchable Graphics GPIO information for PEG 2<br>+/** Offset 0x01B3 - Switchable Graphics GPIO information for PEG 2<br> Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs<br> **/<br> UINT8 SaRtd3Pcie2Gpio[24];<br> <br>-/** Offset 0x01C9 - Switchable Graphics GPIO information for PEG 3<br>+/** Offset 0x01CB - Switchable Graphics GPIO information for PEG 3<br> Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs<br> **/<br> UINT8 SaRtd3Pcie3Gpio[24];<br> <br>-/** Offset 0x01E1 - Enable/Disable MRC TXT dependency<br>- When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)<br>- (Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT<br>- initialization $EN_DIS<br>+/** Offset 0x01E3 - Enable/Disable MRC TXT dependency<br>+ When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):<br>+ MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization<br>+ $EN_DIS<br> **/<br> UINT8 TxtImplemented;<br> <br>-/** Offset 0x01E2 - Enable/Disable SA OcSupport<br>+/** Offset 0x01E4 - Enable/Disable SA OcSupport<br> Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport<br> $EN_DIS<br> **/<br> UINT8 SaOcSupport;<br> <br>-/** Offset 0x01E3 - GT slice Voltage Mode<br>+/** Offset 0x01E5 - GT slice Voltage Mode<br> 0(Default): Adaptive, 1: Override<br> 0: Adaptive, 1: Override<br> **/<br> UINT8 GtVoltageMode;<br> <br>-/** Offset 0x01E4 - Maximum GTs turbo ratio override<br>+/** Offset 0x01E6 - Maximum GTs turbo ratio override<br> 0(Default)=Minimal/Auto, 60=Maximum<br> **/<br> UINT8 GtMaxOcRatio;<br> <br>-/** Offset 0x01E5 - The voltage offset applied to GT slice<br>+/** Offset 0x01E7 - The voltage offset applied to GT slice<br> 0(Default)=Minimal, 1000=Maximum<br> **/<br> UINT16 GtVoltageOffset;<br> <br>-/** Offset 0x01E7 - The GT slice voltage override which is applied to the entire range of GT<br>- frequencies<br>+/** Offset 0x01E9 - The GT slice voltage override which is applied to the entire range of GT frequencies<br> 0(Default)=Minimal, 2000=Maximum<br> **/<br> UINT16 GtVoltageOverride;<br> <br>-/** Offset 0x01E9 - adaptive voltage applied during turbo frequencies<br>+/** Offset 0x01EB - adaptive voltage applied during turbo frequencies<br> 0(Default)=Minimal, 2000=Maximum<br> **/<br> UINT16 GtExtraTurboVoltage;<br> <br>-/** Offset 0x01EB - voltage offset applied to the SA<br>+/** Offset 0x01ED - voltage offset applied to the SA<br> 0(Default)=Minimal, 1000=Maximum<br> **/<br> UINT16 SaVoltageOffset;<br> <br>-/** Offset 0x01ED - PCIe root port Function number for Switchable Graphics dGPU<br>+/** Offset 0x01EF - PCIe root port Function number for Switchable Graphics dGPU<br> Root port Index number to indicate which PCIe root port has dGPU<br> **/<br> UINT8 RootPortIndex;<br> <br>-/** Offset 0x01EE - Realtime Memory Timing<br>+/** Offset 0x01F0 - Realtime Memory Timing<br> 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform<br> realtime memory timing changes after MRC_DONE.<br> 0: Disabled, 1: Enabled<br> **/<br> UINT8 RealtimeMemoryTiming;<br> <br>-/** Offset 0x01EF - Enable/Disable SA IPU<br>+/** Offset 0x01F1 - Enable/Disable SA IPU<br> Enable(Default): Enable SA IPU, Disable: Disable SA IPU<br> $EN_DIS<br> **/<br> UINT8 SaIpuEnable;<br> <br>-/** Offset 0x01F0 - IPU IMR Configuration<br>+/** Offset 0x01F2 - IPU IMR Configuration<br> 0:IPU Camera, 1:IPU Gen Default is 0<br> 0:IPU Camera, 1:IPU Gen<br> **/<br> UINT8 SaIpuImrConfiguration;<br> <br>-/** Offset 0x01F1 - Selection of PSMI Support On/Off<br>+/** Offset 0x01F3 - Selection of PSMI Support On/Off<br> 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support<br> $EN_DIS<br> **/<br> UINT8 GtPsmiSupport;<br> <br>-/** Offset 0x01F2 - SaPreMemProductionRsvd<br>+/** Offset 0x01F4 - SaPreMemProductionRsvd<br> Reserved for SA Pre-Mem Production<br> $EN_DIS<br> **/<br>- UINT8 SaPreMemProductionRsvd[14];<br>+ UINT8 SaPreMemProductionRsvd[12];<br> <br> /** Offset 0x0200 - BIST on Reset<br> Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.<br>@@ -1063,8 +1062,8 @@<br> UINT8 BiosGuardToolsInterface;<br> <br> /** Offset 0x0225 - EnableSgx<br>- Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable<br>- $EN_DIS<br>+ Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control<br>+ 0: Disable, 1: Enable, 2: Software Control<br> **/<br> UINT8 EnableSgx;<br> <br>@@ -1079,7 +1078,7 @@<br> UINT8 UnusedUpdSpace6;<br> <br> /** Offset 0x0228 - PrmrrSize<br>- Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable<br>+ 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000<br> **/<br> UINT32 PrmrrSize;<br> <br>@@ -2233,9 +2232,25 @@<br> **/<br> UINT8 CleanMemory;<br> <br>-/** Offset 0x050D<br>+/** Offset 0x050D - LpDdrDqDqsReTraining<br>+ Enables/Disable LpDdrDqDqsReTraining<br>+ $EN_DIS<br> **/<br>- UINT8 ReservedFspmUpd[19];<br>+ UINT8 LpDdrDqDqsReTraining;<br>+<br>+/** Offset 0x050E - Post Code Output Port<br>+ This option configures Post Code Output Port<br>+**/<br>+ UINT16 PostCodeOutputPort;<br>+<br>+/** Offset 0x0510 - RMTLoopCount<br>+ Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO<br>+**/<br>+ UINT8 RMTLoopCount;<br>+<br>+/** Offset 0x0511<br>+**/<br>+ UINT8 ReservedFspmUpd[15];<br> } FSP_M_CONFIG;<br> <br> /** Fsp M Test Configuration<br>@@ -2489,11 +2504,17 @@<br> **/<br> UINT8 PanelPowerEnable;<br> <br>-/** Offset 0x0583 - SaPreMemTestRsvd<br>+/** Offset 0x0583 - BdatTestType<br>+ Indicates the type of Memory Training data to populate into the BDAT ACPI table.<br>+ 0:Rank Marign Tool, 1:Margin2D<br>+**/<br>+ UINT8 BdatTestType;<br>+<br>+/** Offset 0x0584 - SaPreMemTestRsvd<br> Reserved for SA Pre-Mem Test<br> $EN_DIS<br> **/<br>- UINT8 SaPreMemTestRsvd[13];<br>+ UINT8 SaPreMemTestRsvd[12];<br> <br> /** Offset 0x0590 - TotalFlashSize<br> Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable<br>@@ -2544,8 +2565,8 @@<br> UINT8 BypassPhySyncReset;<br> <br> /** Offset 0x059D - Force ME DID Init Status<br>- Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, 4:<br>- Memory not preserved across reset, Set ME DID init stat value<br>+ Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set<br>+ ME DID init stat value<br> $EN_DIS<br> **/<br> UINT8 DidInitStat;<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>index ab48513..ac660eb 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>@@ -437,11 +437,25 @@<br> **/<br> UINT8 SataRstLegacyOrom;<br> <br>-/** Offset 0x011B - PchPostMemRsvd<br>+/** Offset 0x011B - Trace Hub Memory Base<br>+ If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate<br>+ trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub<br>+ memory is configured properly.<br>+**/<br>+ UINT32 TraceHubMemBase;<br>+<br>+/** Offset 0x011F - PMC Debug Message Enable<br>+ When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW<br>+ will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix<br>+ $EN_DIS<br>+**/<br>+ UINT8 PmcDbgMsgEn;<br>+<br>+/** Offset 0x0120 - PchPostMemRsvd<br> Reserved for PCH Post-Mem<br> $EN_DIS<br> **/<br>- UINT8 PchPostMemRsvd[42];<br>+ UINT8 PchPostMemRsvd[37];<br> <br> /** Offset 0x0145 - Enable Ufs Controller<br> Enable/disable Ufs 2.0 Controller.<br>@@ -458,13 +472,7 @@<br> <br> /** Offset 0x0147<br> **/<br>- UINT8 UnusedUpdSpace3;<br>-<br>-/** Offset 0x0148 - CNVi BT Interface<br>- This option configures BT device interface to either USB or UART<br>- 0:UART, 1:USB<br>-**/<br>- UINT8 PchCnviBtInterface;<br>+ UINT8 UnusedUpdSpace3[2];<br> <br> /** Offset 0x0149 - PCH USB OverCurrent mapping enable<br> 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin<br>@@ -473,11 +481,9 @@<br> **/<br> UINT8 PchUsbOverCurrentEnable;<br> <br>-/** Offset 0x014A - CNVi BT Uart Type<br>- This is a test option which allows configuration of UART type for BT communication<br>- 0:Serial IO Uart0, 1:ISH Uart0, 2:Uart over external pads<br>+/** Offset 0x014A<br> **/<br>- UINT8 PchCnviBtUartType;<br>+ UINT8 UnusedUpdSpace4;<br> <br> /** Offset 0x014B - CNVi MfUart1 Type<br> This option configures Uart type which connects to MfUart1<br>@@ -500,7 +506,7 @@<br> <br> /** Offset 0x014E<br> **/<br>- UINT8 UnusedUpdSpace4;<br>+ UINT8 UnusedUpdSpace5;<br> <br> /** Offset 0x014F - PCHHOT# pin<br> Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable<br>@@ -590,7 +596,7 @@<br> <br> /** Offset 0x015F<br> **/<br>- UINT8 UnusedUpdSpace5[4];<br>+ UINT8 UnusedUpdSpace6[4];<br> <br> /** Offset 0x0163 - PCH PCIe root port connection type<br> 0: built-in device, 1:slot<br>@@ -627,7 +633,7 @@<br> <br> /** Offset 0x01FB<br> **/<br>- UINT8 UnusedUpdSpace6[5];<br>+ UINT8 UnusedUpdSpace7[5];<br> <br> /** Offset 0x0200 - Enable/Disable SA CRID<br> Enable: SA CRID, Disable (Default): SA CRID<br>@@ -636,8 +642,8 @@<br> UINT8 CridEnable;<br> <br> /** Offset 0x0201 - DMI ASPM<br>- 0=Disable, 2(Default)=L1<br>- 0:Disable, 2:L1<br>+ 0=Disable, 3(Default)=L0sL1<br>+ 0:Disable, 3:L0sL1<br> **/<br> UINT8 DmiAspm;<br> <br>@@ -683,7 +689,7 @@<br> <br> /** Offset 0x0219<br> **/<br>- UINT8 UnusedUpdSpace7;<br>+ UINT8 UnusedUpdSpace8;<br> <br> /** Offset 0x021A - Enable or disable GNA device<br> 0=Disable, 1(Default)=Enable<br>@@ -760,7 +766,13 @@<br> Reserved for SA Post-Mem Production<br> $EN_DIS<br> **/<br>- UINT8 SaPostMemProductionRsvd[70];<br>+ UINT8 SaPostMemProductionRsvd[46];<br>+<br>+/** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable<br>+ PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for<br>+ Alpine ridge <br>+**/<br>+ UINT8 PcieRootPortGen2PllL1CgDisable[24];<br> <br> /** Offset 0x0277 - Advanced Encryption Standard (AES) feature<br> Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable<br>@@ -876,7 +888,7 @@<br> <br> /** Offset 0x02BB<br> **/<br>- UINT8 UnusedUpdSpace8[10];<br>+ UINT8 UnusedUpdSpace9[10];<br> <br> /** Offset 0x02C5 - DcLoadline<br> PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is<br>@@ -931,11 +943,10 @@<br> **/<br> UINT8 SendVrMbxCmd;<br> <br>-/** Offset 0x0304 - Enable or Disable VMX<br>- Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.<br>- $EN_DIS<br>+/** Offset 0x0304 - Reserved<br>+ Reserved<br> **/<br>- UINT8 VmxEnable;<br>+ UINT8 Reserved2;<br> <br> /** Offset 0x0305 - Enable or Disable TXT<br> Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.<br>@@ -945,7 +956,7 @@<br> <br> /** Offset 0x0306<br> **/<br>- UINT8 UnusedUpdSpace9[6];<br>+ UINT8 UnusedUpdSpace10[6];<br> <br> /** Offset 0x030C - Skip Multi-Processor Initialization<br> When this is skipped, boot loader must initialize processors before SilicionInit<br>@@ -1012,7 +1023,7 @@<br> <br> /** Offset 0x032B<br> **/<br>- UINT8 UnusedUpdSpace10[27];<br>+ UINT8 UnusedUpdSpace11[27];<br> <br> /** Offset 0x0346 - Enable DMI ASPM<br> ASPM on PCH side of the DMI Link.<br>@@ -1055,7 +1066,7 @@<br> <br> /** Offset 0x0367<br> **/<br>- UINT8 UnusedUpdSpace11;<br>+ UINT8 UnusedUpdSpace12;<br> <br> /** Offset 0x0368 - VC Type<br> Virtual Channel Type Select: 0: VC0, 1: VC1.<br>@@ -1094,34 +1105,9 @@<br> **/<br> UINT8 PchHdaIDispCodecDisconnect;<br> <br>-/** Offset 0x036E - DSP DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum)<br>- 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array.<br>- 0: Disable, 1: 2ch array, 2: 4ch array, 3: 1ch array<br>+/** Offset 0x036E<br> **/<br>- UINT8 PchHdaDspEndpointDmic;<br>-<br>-/** Offset 0x036F - DSP Bluetooth enablement<br>- 0: Disable; 1: Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 PchHdaDspEndpointBluetooth;<br>-<br>-/** Offset 0x0370 - DSP I2S enablement<br>- 0: Disable; 1: Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 PchHdaDspEndpointI2s;<br>-<br>-/** Offset 0x0371 - Bitmask of supported DSP features<br>- [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6]<br>- - BT Intel A2DP; [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0:<br>- Intel WoV, 1: Windows Voice Activation.<br>-**/<br>- UINT32 PchHdaDspFeatureMask;<br>-<br>-/** Offset 0x0375<br>-**/<br>- UINT8 UnusedUpdSpace12[8];<br>+ UINT8 UnusedUpdSpace13[15];<br> <br> /** Offset 0x037D - Enable PCH Io Apic Entry 24-119<br> 0: Disable; 1: Enable.<br>@@ -1136,7 +1122,7 @@<br> <br> /** Offset 0x037F<br> **/<br>- UINT8 UnusedUpdSpace13;<br>+ UINT8 UnusedUpdSpace14;<br> <br> /** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned<br> 0: Disable; 1: Enable.<br>@@ -1236,7 +1222,7 @@<br> <br> /** Offset 0x0390<br> **/<br>- UINT8 UnusedUpdSpace14[3];<br>+ UINT8 UnusedUpdSpace15[3];<br> <br> /** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK<br> Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region<br>@@ -1363,7 +1349,7 @@<br> <br> /** Offset 0x05BE<br> **/<br>- UINT8 UnusedUpdSpace15[10];<br>+ UINT8 UnusedUpdSpace16[10];<br> <br> /** Offset 0x05C8 - PCIE RP Aspm<br> The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is<br>@@ -1422,7 +1408,7 @@<br> <br> /** Offset 0x0664<br> **/<br>- UINT8 UnusedUpdSpace16;<br>+ UINT8 UnusedUpdSpace17;<br> <br> /** Offset 0x0665 - PCIE Compliance Test Mode<br> Compliance Test Mode shall be enabled when using Compliance Load Board.<br>@@ -1439,7 +1425,7 @@<br> <br> /** Offset 0x0667<br> **/<br>- UINT8 UnusedUpdSpace17[2];<br>+ UINT8 UnusedUpdSpace18[2];<br> <br> /** Offset 0x0669 - PCH Pm PME_B0_S5_DIS<br> When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.<br>@@ -1465,7 +1451,7 @@<br> <br> /** Offset 0x066F<br> **/<br>- UINT8 UnusedUpdSpace18;<br>+ UINT8 UnusedUpdSpace19;<br> <br> /** Offset 0x0670 - PCH Pm Wol Enable Override<br> Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.<br>@@ -1554,7 +1540,7 @@<br> <br> /** Offset 0x067D<br> **/<br>- UINT8 UnusedUpdSpace19[3];<br>+ UINT8 UnusedUpdSpace20[3];<br> <br> /** Offset 0x0680 - PCH Pm Lpc Clock Run<br> This member describes whether or not the LPC ClockRun feature of PCH should be enabled.<br>@@ -1587,7 +1573,7 @@<br> <br> /** Offset 0x0685<br> **/<br>- UINT8 UnusedUpdSpace20;<br>+ UINT8 UnusedUpdSpace21;<br> <br> /** Offset 0x0686 - PCH Pm Disable Native Power Button<br> Power button native mode disable.<br>@@ -1627,7 +1613,7 @@<br> <br> /** Offset 0x068C<br> **/<br>- UINT8 UnusedUpdSpace21;<br>+ UINT8 UnusedUpdSpace22;<br> <br> /** Offset 0x068D - PCH Sata Pwr Opt Enable<br> SATA Power Optimizer on PCH side.<br>@@ -1806,9 +1792,17 @@<br> **/<br> UINT8 PchScsEmmcHs400DriverStrength;<br> <br>-/** Offset 0x06FA<br>+/** Offset 0x06FA - PCH SerialIo I2C Pads Termination<br>+ 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak<br>+ pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination<br>+ respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.<br>+ 0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU<br> **/<br>- UINT8 UnusedUpdSpace22[7];<br>+ UINT8 PchSerialIoI2cPadsTermination[6];<br>+<br>+/** Offset 0x0700<br>+**/<br>+ UINT8 UnusedUpdSpace23;<br> <br> /** Offset 0x0701 - PcdSerialIoUart0PinMuxing<br> Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled.<br>@@ -1818,7 +1812,7 @@<br> <br> /** Offset 0x0702<br> **/<br>- UINT8 UnusedUpdSpace23[1];<br>+ UINT8 UnusedUpdSpace24[1];<br> <br> /** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines<br> Enables UART hardware flow control, CTS and RTS linesh.<br>@@ -2075,9 +2069,15 @@<br> **/<br> UINT8 SataRstOptaneMemory;<br> <br>-/** Offset 0x0751<br>+/** Offset 0x0751 - PCH Sata Rst CPU Attached Storage<br>+ CPU Attached Storage<br>+ $EN_DIS<br> **/<br>- UINT8 UnusedUpdSpace24[3];<br>+ UINT8 SataRstCpuAttachedStorage;<br>+<br>+/** Offset 0x0752<br>+**/<br>+ UINT8 UnusedUpdSpace25[2];<br> <br> /** Offset 0x0754 - Pch PCIE device override table pointer<br> The PCIe device table is being used to override PCIe device ASPM settings. This<br>@@ -2171,14 +2171,23 @@<br> UINT8 MeUnconfigOnRtcClear;<br> <br> /** Offset 0x07A9 - Enable PS_ON.<br>- When FALSE, PS_ON is to be disabled.<br>+ PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power<br>+ target that will be required by the California Energy Commission (CEC). When FALSE,<br>+ PS_ON is to be disabled.<br> $EN_DIS<br> **/<br> UINT8 PsOnEnable;<br> <br>-/** Offset 0x07AA<br>+/** Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable<br>+ Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO<br>+ and VccSTG rails instead of SLP_S0# pin.<br>+ $EN_DIS<br> **/<br>- UINT8 ReservedFspsUpd[3];<br>+ UINT8 PmcCpuC10GatePinEnable;<br>+<br>+/** Offset 0x07AB<br>+**/<br>+ UINT8 ReservedFspsUpd[2];<br> } FSP_S_CONFIG;<br> <br> /** Fsp S Test Configuration<br>@@ -2742,10 +2751,9 @@<br> **/<br> UINT16 PsysPmax;<br> <br>-/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0<br>- Interrupt Response Time Limit of C-State LatencyContol0. Range of value 0 to 0x3FF<br>+/** Offset 0x0858<br> **/<br>- UINT16 CstateLatencyControl0Irtl;<br>+ UINT8 Reserved0[2];<br> <br> /** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1<br> Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF<br>@@ -3059,35 +3067,29 @@<br> **/<br> UINT8 PchPmDisableEnergyReport;<br> <br>-/** Offset 0x0A5F - PCH Pm Pmc Read Disable<br>- When set to true, this bit disallows host reads to PMC XRAM.<br>- $EN_DIS<br>-**/<br>- UINT8 PchPmPmcReadDisable;<br>-<br>-/** Offset 0x0A60 - PCH Sata Test Mode<br>+/** Offset 0x0A5F - PCH Sata Test Mode<br> Allow entrance to the PCH SATA test modes.<br> $EN_DIS<br> **/<br> UINT8 SataTestMode;<br> <br>-/** Offset 0x0A61 - PCH USB OverCurrent mapping lock enable<br>+/** Offset 0x0A60 - PCH USB OverCurrent mapping lock enable<br> If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning<br> that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.<br> $EN_DIS<br> **/<br> UINT8 PchXhciOcLock;<br> <br>-/** Offset 0x0A62 - PCH USB Access Control setting<br>+/** Offset 0x0A61 - PCH USB Access Control setting<br> This policy option controls setting the Access Control (ACCTRL) bit in XHCC1 which<br> will lock write access to registers controlled by its functionality.<br> $EN_DIS<br> **/<br> UINT8 PchXhciAcLock;<br> <br>-/** Offset 0x0A63<br>+/** Offset 0x0A62<br> **/<br>- UINT8 UnusedUpdSpace25[15];<br>+ UINT8 UnusedUpdSpace26[16];<br> <br> /** Offset 0x0A72 - Skip POSTBOOT SAI<br> This skip the Post Boot Sai programming. 0: Set Post Boot Sai; 1: Skip Post Boot Sai.<br>@@ -3095,9 +3097,15 @@<br> **/<br> UINT8 SkipPostBootSai;<br> <br>-/** Offset 0x0A73<br>+/** Offset 0x0A73 - Mctp Broadcast Cycle<br>+ Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.<br>+ $EN_DIS<br> **/<br>- UINT8 ReservedFspsTestUpd[13];<br>+ UINT8 MctpBroadcastCycle;<br>+<br>+/** Offset 0x0A74<br>+**/<br>+ UINT8 ReservedFspsTestUpd[12];<br> } FSP_S_TEST_CONFIG;<br> <br> /** Fsp S Restricted Configuration<br>@@ -3110,7 +3118,7 @@<br> <br> /** Offset 0x0A84<br> **/<br>- UINT8 UnusedUpdSpace26;<br>+ UINT8 UnusedUpdSpace27;<br> <br> /** Offset 0x0A85 - Enable or disable GNA Error Check Disable Bit<br> 0=Disable, 1(Default)=Enable<br>@@ -3378,7 +3386,7 @@<br> <br> /** Offset 0x0ACB<br> **/<br>- UINT8 UnusedUpdSpace27[49];<br>+ UINT8 UnusedUpdSpace28[49];<br> <br> /** Offset 0x0AFC - SaPostMemRestrictedRsvd<br> Reserved for SA Post-Mem Restricted<br>@@ -3490,7 +3498,7 @@<br> <br> /** Offset 0x0B5E<br> **/<br>- UINT8 UnusedUpdSpace28;<br>+ UINT8 UnusedUpdSpace29;<br> <br> /** Offset 0x0B5F - Pch Tc Lock Down<br> Pch Tc Lock Down.<br>@@ -3518,7 +3526,7 @@<br> <br> /** Offset 0x0B63<br> **/<br>- UINT8 UnusedUpdSpace29;<br>+ UINT8 UnusedUpdSpace30;<br> <br> /** Offset 0x0B64 - Configuration Lockdown (BCLD)<br> 0: POR (Enable), 1: Enable, 2: Disable.<br>@@ -3532,11 +3540,9 @@<br> **/<br> UINT8 PchHdaTestLowFreqLinkClkSrc;<br> <br>-/** Offset 0x0B66 - I2s Configuration<br>- 0: Disabled, 1: Realtek ALC298, 2: Realtek ALC286S, 3: Analog Devices, 4: I2S_24b_48kHz_Master,<br>- 5: I2S_24b_48kHz_Slave, 6: PCM_16b_8kHz_Master, 7: PCM_16b_8kHz_Slave.<br>+/** Offset 0x0B66<br> **/<br>- UINT32 PchHdaTestI2sConfiguration;<br>+ UINT8 UnusedUpdSpace31[4];<br> <br> /** Offset 0x0B6A - PCH Lan Test WOL Fast Support<br> Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm.<br>@@ -3578,7 +3584,7 @@<br> <br> /** Offset 0x0BE4<br> **/<br>- UINT8 UnusedUpdSpace30[72];<br>+ UINT8 UnusedUpdSpace32[72];<br> <br> /** Offset 0x0C2C - PCH Pcie bem<br> PCH Pcie bem.<br>@@ -3808,7 +3814,7 @@<br> <br> /** Offset 0x0C6F<br> **/<br>- UINT8 UnusedUpdSpace31[2];<br>+ UINT8 UnusedUpdSpace33[2];<br> <br> /** Offset 0x0C71 - This locks down Enables the thermal sensor<br> 0: Disabled, 1: Enabled.<br>@@ -3830,7 +3836,7 @@<br> <br> /** Offset 0x0C74<br> **/<br>- UINT8 UnusedUpdSpace32[10];<br>+ UINT8 UnusedUpdSpace34[10];<br> <br> /** Offset 0x0C7E - USB EP Type Lock Policy<br> USB EP Type Lock Policy.<br>@@ -3849,7 +3855,7 @@<br> <br> /** Offset 0x0C8A<br> **/<br>- UINT8 UnusedUpdSpace33[4];<br>+ UINT8 UnusedUpdSpace35[4];<br> <br> /** Offset 0x0C8E - Xhci Controller Enable<br> 0: Disable; 1: Enable.<br>@@ -3858,7 +3864,7 @@<br> <br> /** Offset 0x0C8F<br> **/<br>- UINT8 UnusedUpdSpace34;<br>+ UINT8 UnusedUpdSpace36;<br> <br> /** Offset 0x0C90 - Unlock to enable NOA for SV usage<br> 1: Unlock to enable NOA usage. 0: Set Xhci OC registers, Set Xhci OCCDone bit, XHCI<br>@@ -3885,22 +3891,16 @@<br> <br> /** Offset 0x0C94<br> **/<br>- UINT8 UnusedUpdSpace35[2];<br>+ UINT8 UnusedUpdSpace37[2];<br> <br> /** Offset 0x0C96 - Restricted Flash Lock Down<br> Restricted Flash Lock Down.<br> **/<br> UINT8 PchTestFlashLockDown;<br> <br>-/** Offset 0x0C97 - Restricted Mctp Broad cast Cycle<br>- Determine if MCTP Broadcast is enabled. 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.<br>- 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE<br>+/** Offset 0x0C97<br> **/<br>- UINT8 PchTestMctpBroadcastCycle;<br>-<br>-/** Offset 0x0C98<br>-**/<br>- UINT8 UnusedUpdSpace36;<br>+ UINT8 UnusedUpdSpace38[2];<br> <br> /** Offset 0x0C99 - PCH PMC ER Debug mode<br> Disable/Enable Energy Reporting Debug Mode.<br>@@ -3908,15 +3908,9 @@<br> **/<br> UINT8 TestPchPmErDebugMode;<br> <br>-/** Offset 0x0C9A - PCH ACPI Timer Disable<br>- 0: False, Acpi Timer is enabled; 1: True, Acpi Timer is disabled<br>- $EN_DIS<br>+/** Offset 0x0C9A<br> **/<br>- UINT8 TestAcpiTmrDisable;<br>-<br>-/** Offset 0x0C9B<br>-**/<br>- UINT8 UnusedUpdSpace37;<br>+ UINT8 UnusedUpdSpace39[2];<br> <br> /** Offset 0x0C9C - USB2/TS LDO Dynamic Shutdown<br> Enable/Disable USB2/TS LDO Dynamic Shutdown<br>@@ -3974,25 +3968,42 @@<br> **/<br> UINT8 PcieAllowL0sWithGen3;<br> <br>-/** Offset 0x0CA5 - PchSiliconRestrictedRsvd<br>- Reserved for CPU Post-Mem Restricted<br>+/** Offset 0x0CA5 - CNVi BT Interface<br>+ This option configures BT device interface to either USB or UART<br>+ 0:UART, 1:USB<br>+**/<br>+ UINT8 TestCnviBtInterface;<br>+<br>+/** Offset 0x0CA6 - CNVi BT Uart Type<br>+ This is a test option which allows configuration of UART type for BT communication<br>+ 0:Serial IO Uart0, 1:ISH Uart0, 2:Uart over external pads<br>+**/<br>+ UINT8 TestCnviBtUartType;<br>+<br>+/** Offset 0x0CA7 - Enable/Disable DMI L1 entry disable mode <br>+ Enable/Disable DMI L1 entry disable mode.<br>+**/<br>+ UINT8 PcieRpTestDmiL1Edm[24];<br>+<br>+/** Offset 0x0CBF - PchSiliconRestrictedRsvd<br>+ Reserved for PCH Post-Mem Restricted<br> $EN_DIS<br> **/<br>- UINT8 PchSiliconRestrictedRsvd[5];<br>+ UINT8 PchSiliconRestrictedRsvd[3];<br> <br>-/** Offset 0x0CAA - Si Config SvPolicyEnable.<br>+/** Offset 0x0CC2 - Si Config SvPolicyEnable.<br> Platform specific common policies that used by several silicon components. SvPolicyEnable.<br> $EN_DIS<br> **/<br> UINT8 SiSvPolicyEnable;<br> <br>-/** Offset 0x0CAB - Si Config HsleWorkaround<br>+/** Offset 0x0CC3 - Si Config HsleWorkaround<br> Enable/Disable HSLE model specific workarounds<br> $EN_DIS<br> **/<br> UINT8 HsleWorkaround;<br> <br>-/** Offset 0x0CAC<br>+/** Offset 0x0CC4<br> **/<br> UINT8 ReservedFspsRestrictedUpd[4];<br> } FSP_S_RESTRICTED_CONFIG;<br>@@ -4017,7 +4028,7 @@<br> **/<br> FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig;<br> <br>-/** Offset 0x0CB0<br>+/** Offset 0x0CC8<br> **/<br> UINT16 UpdTerminator;<br> } FSPS_UPD;<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h<br>index 7927e23..24f0883 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h<br>@@ -260,13 +260,6 @@<br> UINT32 GdxcMotBase;<br> UINT32 GdxcMotSize;<br> #endif //CPU_CFL<br>-//<br>-// CPU:RestrictedBegin<br>-//<br>- UINT32 SharedMailboxBase;<br>-//<br>-// CPU:RestrictedEnd<br>-//<br> } MEMORY_PLATFORM_DATA;<br> <br> typedef struct {<br></pre><p>To view, visit <a href="https://review.coreboot.org/21705">change 21705</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21705"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iac8db8403b0f909f32049329f867c28c68e3b830 </div>
<div style="display:none"> Gerrit-Change-Number: 21705 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>