<p>Rizwan Qureshi would like Balaji Manigandan to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/21679">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">FSP.2.7.2 :[WIP] Update of header files<br><br>Updating the variable changed in meminfo hob<br><br>Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151<br>Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com><br>Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com><br>---<br>M src/soc/intel/skylake/romstage/romstage_fsp20.c<br>M src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h<br>M src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h<br>5 files changed, 187 insertions(+), 89 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/21679/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c<br>index c43bdc3..cbf934e 100644<br>--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c<br>+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c<br>@@ -80,11 +80,11 @@<br> dimm_max = ARRAY_SIZE(mem_info->dimm);<br> ctrlr_info = &memory_info_hob->Controller[0];<br> for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {<br>- channel_info = &ctrlr_info->Channel[channel];<br>+ channel_info = &ctrlr_info->ChannelInfo[channel];<br> if (channel_info->Status != 2)<br> continue;<br> for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {<br>- src_dimm = &channel_info->Dimm[dimm];<br>+ src_dimm = &channel_info->DimmInfo[dimm];<br> dest_dimm = &mem_info->dimm[index];<br> <br> if (src_dimm->Status != DIMM_PRESENT)<br>@@ -93,8 +93,8 @@<br> /* Populate the DIMM information */<br> dimm_info_fill(dest_dimm,<br> src_dimm->DimmCapacity,<br>- memory_info_hob->DdrType,<br>- memory_info_hob->Frequency,<br>+ memory_info_hob->MemoryType,<br>+ memory_info_hob->ConfiguredMemoryClockSpeed,<br> channel_info->ChannelId,<br> src_dimm->DimmId,<br> (const char *)src_dimm->ModulePartNum,<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h<br>index c8cdc5f..5a32d78 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h<br>@@ -1,20 +1,34 @@<br> /** @file<br> FSP CPU Data Config Block.<br> <br>-@copyright<br>- Copyright (c) 2016 Intel Corporation. All rights reserved<br>- This software and associated documentation (if any) is furnished<br>- under a license and may only be used or copied in accordance<br>- with the terms of the license. Except as permitted by the<br>- license, no part of this software or documentation may be<br>- reproduced, stored in a retrieval system, or transmitted in any<br>- form or by any means without the express written consent of<br>- Intel Corporation.<br>- This file contains an 'Intel Peripheral Driver' and is uniquely<br>- identified as "Intel Reference Module" and is licensed for Intel<br>- CPUs and chipsets under the terms of your license agreement with<br>- Intel or your vendor. This file may be modified by the user, subject<br>- to additional terms of the license agreement.<br>+ @copyright<br>+ INTEL CONFIDENTIAL<br>+ Copyright 2016 Intel Corporation.<br>+<br>+ The source code contained or described herein and all documents related to the<br>+ source code ("Material") are owned by Intel Corporation or its suppliers or<br>+ licensors. Title to the Material remains with Intel Corporation or its suppliers<br>+ and licensors. The Material may contain trade secrets and proprietary and<br>+ confidential information of Intel Corporation and its suppliers and licensors,<br>+ and is protected by worldwide copyright and trade secret laws and treaty<br>+ provisions. No part of the Material may be used, copied, reproduced, modified,<br>+ published, uploaded, posted, transmitted, distributed, or disclosed in any way<br>+ without Intel's prior express written permission.<br>+<br>+ No license under any patent, copyright, trade secret or other intellectual<br>+ property right is granted to or conferred upon you by disclosure or delivery<br>+ of the Materials, either expressly, by implication, inducement, estoppel or<br>+ otherwise. Any license under such intellectual property rights must be<br>+ express and approved by Intel in writing.<br>+<br>+ Unless otherwise agreed by Intel in writing, you may not remove or alter<br>+ this notice or any other notice embedded in Materials by Intel or<br>+ Intel's suppliers or licensors in any way.<br>+<br>+ This file contains an 'Intel Peripheral Driver' and is uniquely identified as<br>+ "Intel Reference Module" and is licensed for Intel CPUs and chipsets under<br>+ the terms of your license agreement with Intel or your vendor. This file may<br>+ be modified by the user, subject to additional terms of the license agreement.<br> <br> @par Specification Reference:<br> **/<br>@@ -63,9 +77,10 @@<br> UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.<br> UINT32 RsvdBits : 15; ///< Reserved for future use<br> UINT32 Reserved;<br>- } Bits;<br>- UINT32 Uint32[2];<br>-} CPU_CONFIG_FSP_DATA;<br>+ } Bits;<br>+ UINT32 Uint32[2];<br>+ } CPU_CONFIG_FSP_DATA;<br>+<br> #pragma pack (pop)<br> <br> #endif // _CPU_CONFIG_FSP_DATA_H_<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h<br>index 1916e4e..f3aa4c8 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h<br>@@ -844,7 +844,7 @@<br> <br> /** Offset 0x02E3 - Ring Downbin<br> Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always<br>- lower than the core ratio.<b>0: Disable</b>; 1: Enable.<br>+ lower than the core ratio. 0: Disable; <b>1: Enable.</b><br> $EN_DIS<br> **/<br> UINT8 RingDownBin;<br>@@ -1255,9 +1255,15 @@<br> **/<br> UINT8 Avx3RatioOffset;<br> <br>-/** Offset 0x051B<br>+/** Offset 0x051B - Ask MRC to clear memory content<br>+ Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.<br>+ $EN_DIS<br> **/<br>- UINT8 ReservedFspmUpd[5];<br>+ UINT8 CleanMemory;<br>+<br>+/** Offset 0x051C<br>+**/<br>+ UINT8 ReservedFspmUpd[4];<br> } FSP_M_CONFIG;<br> <br> /** Fsp M Test Configuration<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h<br>index b3c7698..f4f4bad 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h<br>@@ -167,7 +167,7 @@<br> <br> /** Offset 0x0036 - Flash Configuration Lock Down<br> Enable/disable flash lock down. If platform decides to skip this programming, it<br>- must lock SPI flash register before end of post.<br>+ must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post.<br> $EN_DIS<br> **/<br> UINT8 SpiFlashCfgLockDown;<br>@@ -484,7 +484,7 @@<br> <br> /** Offset 0x020C - PCIe DeEmphasis control per root port<br> 0: -6dB, 1(Default): -3.5dB<br>- 0:Disable, 2:L1<br>+ 0:-6dB, 1:-3.5dB<br> **/<br> UINT8 PegDeEmphasis[3];<br> <br>@@ -2060,9 +2060,15 @@<br> **/<br> UINT8 MeUnconfigIsValid;<br> <br>-/** Offset 0x077A<br>+/** Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues.<br>+ Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox<br>+ command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.<br> **/<br>- UINT8 ReservedFspsUpd[6];<br>+ UINT8 IslVrCmd;<br>+<br>+/** Offset 0x077B<br>+**/<br>+ UINT8 ReservedFspsUpd[5];<br> } FSP_S_CONFIG;<br> <br> /** Fsp S Test Configuration<br>@@ -2107,7 +2113,7 @@<br> UINT8 DmiIot;<br> <br> /** Offset 0x0789 - PEG Max Payload size per root port<br>- 0xFF(Default):Auto, 0x1: Force 128B, 0X2: Force 256B<br>+ 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B<br> 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B<br> **/<br> UINT8 PegMaxPayload[3];<br>@@ -2520,25 +2526,25 @@<br> /** Offset 0x07DA - Enable or Disable Package C-State Demotion<br> Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; <b>2: Auto</b><br> (Auto: Enabled for Skylake; Disabled for Kabylake)<br>- $EN_DIS<br>+ 0:Disable, 1:Enable, 2:Auto<br> **/<br> UINT8 PkgCStateDemotion;<br> <br> /** Offset 0x07DB - Enable or Disable Package C-State UnDemotion<br> Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; <b>2: Auto</b><br> (Auto: Enabled for Skylake; Disabled for Kabylake)<br>- $EN_DIS<br>+ 0:Disable, 1:Enable, 2:Auto<br> **/<br> UINT8 PkgCStateUnDemotion;<br> <br> /** Offset 0x07DC - Enable or Disable CState-Pre wake<br>- Enable or Disable CState-Pre wake. Disable; <b>1: Enable</b><br>+ Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b><br> $EN_DIS<br> **/<br> UINT8 CStatePreWake;<br> <br> /** Offset 0x07DD - Enable or Disable TimedMwait Support.<br>- Enable or Disable TimedMwait Support. <b>Disable</b>; 1: Enable<br>+ Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable<br> $EN_DIS<br> **/<br> UINT8 TimedMwait;<br>@@ -2606,7 +2612,7 @@<br> <br> /** Offset 0x07E8 - Configuration for boot TDP selection<br> Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP<br>- Up;0xFF : Deactivate<br>+ Up; 0xFF: Deactivate<br> 0:TDP Nominal, 1:TDP Down, 2:TDP Up, 0xFF:Deactivate<br> **/<br> UINT8 ConfigTdpLevel;<br>@@ -2632,12 +2638,14 @@<br> UINT16 StateRatio[40];<br> <br> /** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol0<br>- Interrupt Response Time Limit of C-State LatencyContol0. Range of value 0 to 0x3FF<br>+ Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF,<br>+ Default is 0x4E, Server Platform is 0x4B<br> **/<br> UINT16 CstateLatencyControl0Irtl;<br> <br> /** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol1<br>- Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF<br>+ Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF,<br>+ Default is 0x76, Server Platform is 0x6B<br> **/<br> UINT16 CstateLatencyControl1Irtl;<br> <br>@@ -2783,11 +2791,18 @@<br> **/<br> UINT8 EightCoreRatioLimit;<br> <br>-/** Offset 0x0888 - ReservedCpuPostMemTest<br>+/** Offset 0x0888 - Set Three Strike Counter Disable<br>+ False (default): Three Strike counter will be incremented and True: Prevents Three<br>+ Strike counter from incrementing; <b>0: False</b>; 1: True.<br>+ 0: False, 1: True<br>+**/<br>+ UINT8 ThreeStrikeCounterDisable;<br>+<br>+/** Offset 0x0889 - ReservedCpuPostMemTest<br> Reserved for CPU Post-Mem Test<br> $EN_DIS<br> **/<br>- UINT8 ReservedCpuPostMemTest[2];<br>+ UINT8 ReservedCpuPostMemTest[1];<br> <br> /** Offset 0x088A - SgxSinitDataFromTpm<br> SgxSinitDataFromTpm default values<br>@@ -2923,7 +2938,7 @@<br> UINT8 PchPmDisableEnergyReport;<br> <br> /** Offset 0x0A2F - PCH Pm Pmc Read Disable<br>- When set to true, this bit disallows host reads to PMC XRAM.<br>+ Deprecated<br> $EN_DIS<br> **/<br> UINT8 PchPmPmcReadDisable;<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h<br>index 8dc2db9..11f79ca 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h<br>@@ -1,33 +1,38 @@<br> /** @file<br>+ This file contains definitions required for creation of<br>+ Memory S3 Save data, Memory Info data and Memory Platform<br>+ data hobs.<br> <br>-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR><br>+ @copyright<br>+ INTEL CONFIDENTIAL<br>+ Copyright 1999 - 2017 Intel Corporation.<br> <br>-Redistribution and use in source and binary forms, with or without modification,<br>-are permitted provided that the following conditions are met:<br>+ The source code contained or described herein and all documents related to the<br>+ source code ("Material") are owned by Intel Corporation or its suppliers or<br>+ licensors. Title to the Material remains with Intel Corporation or its suppliers<br>+ and licensors. The Material may contain trade secrets and proprietary and<br>+ confidential information of Intel Corporation and its suppliers and licensors,<br>+ and is protected by worldwide copyright and trade secret laws and treaty<br>+ provisions. No part of the Material may be used, copied, reproduced, modified,<br>+ published, uploaded, posted, transmitted, distributed, or disclosed in any way<br>+ without Intel's prior express written permission.<br> <br>-* Redistributions of source code must retain the above copyright notice, this<br>- list of conditions and the following disclaimer.<br>-* Redistributions in binary form must reproduce the above copyright notice, this<br>- list of conditions and the following disclaimer in the documentation and/or<br>- other materials provided with the distribution.<br>-* Neither the name of Intel Corporation nor the names of its contributors may<br>- be used to endorse or promote products derived from this software without<br>- specific prior written permission.<br>+ No license under any patent, copyright, trade secret or other intellectual<br>+ property right is granted to or conferred upon you by disclosure or delivery<br>+ of the Materials, either expressly, by implication, inducement, estoppel or<br>+ otherwise. Any license under such intellectual property rights must be<br>+ express and approved by Intel in writing.<br> <br>- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF<br>- THE POSSIBILITY OF SUCH DAMAGE.<br>+ Unless otherwise agreed by Intel in writing, you may not remove or alter<br>+ this notice or any other notice embedded in Materials by Intel or<br>+ Intel's suppliers or licensors in any way.<br> <br>- This file is automatically generated. Please do NOT modify !!!<br>+ This file contains an 'Intel Peripheral Driver' and is uniquely identified as<br>+ "Intel Reference Module" and is licensed for Intel CPUs and chipsets under<br>+ the terms of your license agreement with Intel or your vendor. This file may<br>+ be modified by the user, subject to additional terms of the license agreement.<br> <br>+@par Specification Reference:<br> **/<br> #ifndef _MEM_INFO_HOB_H_<br> #define _MEM_INFO_HOB_H_<br>@@ -52,6 +57,25 @@<br> #define B_RANK1_PRS BIT1<br> #define B_RANK2_PRS BIT4<br> #define B_RANK3_PRS BIT5<br>+<br>+// @todo remove and use the MdePkg\Include\Pi\PiHob.h<br>+#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)<br>+#ifndef __HOB__H__<br>+typedef struct _EFI_HOB_GENERIC_HEADER {<br>+ UINT16 HobType;<br>+ UINT16 HobLength;<br>+ UINT32 Reserved;<br>+} EFI_HOB_GENERIC_HEADER;<br>+<br>+typedef struct _EFI_HOB_GUID_TYPE {<br>+ EFI_HOB_GENERIC_HEADER Header;<br>+ EFI_GUID Name;<br>+ ///<br>+ /// Guid specific data goes here<br>+ ///<br>+} EFI_HOB_GUID_TYPE;<br>+#endif<br>+#endif<br> <br> ///<br> /// Defines taken from MRC so avoid having to include MrcInterface.h<br>@@ -122,7 +146,7 @@<br> #define MRC_DDR_TYPE_UNKNOWN 3<br> #endif<br> <br>-#define MAX_PROFILE_NUM 4 // number of memory profiles supported<br>+#define MAX_PROFILE_NUM 4 // number of memory profiles supported<br> #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported<br> <br> //<br>@@ -151,64 +175,102 @@<br> UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.<br> } MRC_CH_TIMING;<br> <br>+typedef struct {<br>+ UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.<br>+ UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.<br>+ UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).<br>+ UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.<br>+} MRC_TA_TIMING;<br>+<br> ///<br> /// Memory SMBIOS & OC Memory Data Hob<br> ///<br> typedef struct {<br>- UINT8 Status; ///< See MrcDimmStatus for the definition of this field.<br>- UINT8 DimmId;<br>- UINT32 DimmCapacity; ///< DIMM size in MBytes.<br>- UINT16 MfgId;<br>- UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes<br>- UINT8 RankInDimm; ///< The number of ranks in this DIMM.<br>- UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.<br>- UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.<br>- UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.<br>- UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.<br>+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.<br>+ UINT8 DimmId;<br>+ UINT32 DimmCapacity; ///< DIMM size in MBytes.<br>+ UINT16 MfgId;<br>+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes<br>+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.<br>+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.<br>+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.<br>+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.<br>+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.<br> } DIMM_INFO;<br> <br> typedef struct {<br>- UINT8 Status; ///< Indicates whether this channel should be used.<br>- UINT8 ChannelId;<br>- UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.<br>- MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.<br>- DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics.<br>+ UINT8 Status; ///< Indicates whether this channel should be used.<br>+ UINT8 ChannelId;<br>+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.<br>+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.<br>+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.<br> } CHANNEL_INFO;<br> <br> typedef struct {<br>- UINT8 Status; ///< Indicates whether this controller should be used.<br>- UINT16 DeviceId; ///< The PCI device id of this memory controller.<br>- UINT8 RevisionId; ///< The PCI revision id of this memory controller.<br>- UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.<br>- CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions.<br>+ UINT8 Status; ///< Indicates whether this controller should be used.<br>+ UINT16 DeviceId; ///< The PCI device id of this memory controller.<br>+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.<br>+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.<br>+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.<br>+ MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings<br>+ MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings<br>+ MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings<br>+ MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings<br> } CONTROLLER_INFO;<br> <br> typedef struct {<br> UINT8 Revision;<br>- UINT16 DataWidth;<br>+ UINT16 DataWidth; ///< Data width, in bits, of this memory device<br> /** As defined in SMBIOS 3.0 spec<br> Section 7.18.2 and Table 75<br> **/<br>- UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3<br>- UINT32 Frequency; ///< The system's common memory controller frequency in MT/s.<br>+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3<br>+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)<br>+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)<br> /** As defined in SMBIOS 3.0 spec<br> Section 7.17.3 and Table 72<br> **/<br> UINT8 ErrorCorrectionType;<br> <br> SiMrcVersion Version;<br>- UINT32 FreqMax;<br> BOOLEAN EccSupport;<br> UINT8 MemoryProfile;<br> UINT32 TotalPhysicalMemorySize;<br>- UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM]; // Stores the tCK value read from SPD XMP profiles if they exist.<br>- UINT8 XmpProfileEnable; // If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.<br>+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.<br>+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.<br> UINT8 Ratio;<br> UINT8 RefClk;<br> UINT32 VddVoltage[MAX_PROFILE_NUM];<br> CONTROLLER_INFO Controller[MAX_NODE];<br> } MEMORY_INFO_DATA_HOB;<br> <br>+/**<br>+ Memory Platform Data Hob<br>+<br>+ <b>Revision 1:</b><br>+ - Initial version.<br>+ <b>Revision 2:</b><br>+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields<br>+**/<br>+typedef struct {<br>+ UINT8 Revision;<br>+ UINT8 Reserved[3];<br>+ UINT32 BootMode;<br>+ UINT32 TsegSize;<br>+ UINT32 TsegBase;<br>+ UINT32 PrmrrSize;<br>+ UINT32 PrmrrBase;<br>+ UINT32 GttBase;<br>+ UINT32 MmioSize;<br>+ UINT32 PciEBaseAddress;<br>+} MEMORY_PLATFORM_DATA;<br>+<br>+typedef struct {<br>+ EFI_HOB_GUID_TYPE EfiHobGuidType;<br>+ MEMORY_PLATFORM_DATA Data;<br>+ UINT8 *Buffer;<br>+} MEMORY_PLATFORM_DATA_HOB;<br>+<br> #pragma pack (pop)<br> <br> #endif // _MEM_INFO_HOB_H_<br></pre><p>To view, visit <a href="https://review.coreboot.org/21679">change 21679</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21679"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 </div>
<div style="display:none"> Gerrit-Change-Number: 21679 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan@intel.com> </div>