<p>Keith Hui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21670">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP] winbond/w83977tf: Add ACPI DSDT table<br><br>Add DSDT table for this superio to be incorporated into ACPI tables for<br>mainboards with this superio.<br><br>Part of the in-progress work to add ACPI support to asus/p[23]b* family<br>of mainboards.<br><br>Change-Id: If113807901619bc0f4250607546be415f9e5e45b<br>Signed-off-by: Keith Hui <buurin@gmail.com><br>---<br>A src/superio/winbond/w83977tf/acpi/superio.asl<br>1 file changed, 424 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/21670/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/superio/winbond/w83977tf/acpi/superio.asl b/src/superio/winbond/w83977tf/acpi/superio.asl<br>new file mode 100644<br>index 0000000..030ba86<br>--- /dev/null<br>+++ b/src/superio/winbond/w83977tf/acpi/superio.asl<br>@@ -0,0 +1,424 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Keith Hui <buurin@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/*<br>+ * Include this file into a southbridge ASL block and it will<br>+ * expose the W83977TF/EF SuperIO and some of its functionality.<br>+ *<br>+ * It allows the change of IO ports, IRQs and DMA settings on logical<br>+ * devices, disabling and reenabling logical devices and controlling power<br>+ * saving mode on logical devices or the whole chip.<br>+ *<br>+ * Controllable through preprocessor defines:<br>+ * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)<br>+ * SUPERIO_PNP_BASE I/O address of the first PnP configuration register<br>+ * WINBOND_SHOW_UARTA If defined, UARTA will be exposed.<br>+ * WINBOND_SHOW_UARTB If defined, UARTB will be exposed.<br>+ * WINBOND_SHOW_FDC If defined, floppy controller will be exposed.<br>+ * WINBOND_SHOW_LPT If defined, parallel port will be exposed.<br>+ */<br>+<br>+#undef SUPERIO_CHIP_NAME<br>+#define SUPERIO_CHIP_NAME W83977TF<br>+#include <superio/acpi/pnp.asl><br>+#include <superio/winbond/w83977tf/w83977tf.h><br>+/*<br>+Device(SUPERIO_DEV) {<br>+ Name (_HID, EisaId("PNP0A05"))<br>+ Name (_STR, Unicode("Winbond W83977TF/EF Super I/O"))<br>+ Name (_UID, SUPERIO_UID(SUPERIO_DEV,))<br>+*/<br>+ /* Mutex for accesses to the configuration ports */<br>+<br>+ Mutex(CRMX, 1)<br>+<br>+ /* SuperIO configuration ports */<br>+ OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)<br>+ Field (CREG, ByteAcc, NoLock, Preserve)<br>+ {<br>+ PNP_ADDR_REG, 8,<br>+ PNP_DATA_REG, 8<br>+ }<br>+ IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)<br>+ {<br>+ Offset (0x07),<br>+ PNP_LOGICAL_DEVICE, 8, /* Logical device selector */<br>+ Offset (0x20),<br>+ DID, 8, /* Device ID: TF=0x97, EF=0x52 */<br>+ DREV, 8, /* Device revision */<br>+ FDPW, 1, /* FDC Power Down */<br>+ , 2,<br>+ PRPW, 1, /* PRT Power Down */<br>+ UAPW, 1, /* UART A Power Down */<br>+ UBPW, 1, /* UART B Power Down */<br>+ Offset (0x23),<br>+ IPD, 1, /* Immediate Chip Power Down */<br>+ Offset (0x30),<br>+ PNP_DEVICE_ACTIVE, 8, /* PNP_DEVICE_ACTIVE = "ACTR" to match common ASLs */<br>+ Offset (0x60),<br>+ PNP_IO0_HIGH_BYTE, 8,<br>+ PNP_IO0_LOW_BYTE, 8,<br>+ PNP_IO1_HIGH_BYTE, 8,<br>+ PNP_IO1_LOW_BYTE, 8,<br>+ PNP_IO2_HIGH_BYTE, 8,<br>+ PNP_IO2_LOW_BYTE, 8,<br>+ Offset (0x70),<br>+ PNP_IRQ0, 8, /* First IRQ */<br>+ Offset (0x72),<br>+ PNP_IRQ1, 8, /* Second IRQ */<br>+ Offset (0x74),<br>+ PNP_DMA0, 8, /* DMA */<br>+ Offset (0xE0),<br>+ MSWK, 8,<br>+ Offset (0xE4),<br>+ KBWK, 8,<br>+ Offset (0xF0),<br>+ OPT1, 8,<br>+ OPT2, 8<br>+ }<br>+<br>+#undef PNP_ENTER_MAGIC_1ST<br>+#undef PNP_ENTER_MAGIC_2ND<br>+#undef PNP_ENTER_MAGIC_3RD<br>+#undef PNP_ENTER_MAGIC_4TH<br>+#undef PNP_EXIT_MAGIC_1ST<br>+#undef PNP_EXIT_SPECIAL_REG<br>+#undef PNP_EXIT_SPECIAL_VAL<br>+#define PNP_ENTER_MAGIC_1ST 0x87<br>+#define PNP_ENTER_MAGIC_2ND 0x87<br>+#define PNP_EXIT_MAGIC_1ST 0xaa<br>+#include <superio/acpi/pnp_config.asl><br>+<br>+/* This version from OEM bios waits up to 17 cycles till superio identifies itself<br>+Method (ENFG, 0, NotSerialized)<br>+{<br>+ Store (0x00, Local0)<br>+ Store (0x11, Local1)<br>+ While (LNotEqual (Local0, 0x71))<br>+ {<br>+ Store (0x87, ADDR)<br>+ Store (0x87, ADDR)<br>+ If (LOr (LEqual (DEVI, 0x97), LEqual (DEVI, 0x52)))<br>+ {<br>+ Store (0x71, Local0)<br>+ }<br>+<br>+ Decrement (Local1)<br>+ If (LEqual (Local1, 0x00))<br>+ {<br>+ Store (0x71, Local0)<br>+ }<br>+ }<br>+}<br>+*/<br>+ /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */<br>+ Method (_PSC) {<br>+ ENCM (0xFF)<br>+ Store (IPD, Local0)<br>+ EXCM ()<br>+ If (Local0) { Return (2) }<br>+ Else { Return (0) }<br>+ }<br>+<br>+#ifdef WINBOND_SHOW_FDC<br>+Device (FDC0)<br>+{<br>+ Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID<br>+ Method (_STA, 0, NotSerialized) // _STA: Status<br>+ {<br>+ PNP_GENERIC_STA(W83977TF_FDC)<br>+ }<br>+<br>+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device<br>+ {<br>+ PNP_GENERIC_DIS(W83977TF_FDC)<br>+ }<br>+<br>+ Method (_CRS, 0) // _CRS: Current Resource Settings<br>+ {<br>+ Name (BUF0, ResourceTemplate ()<br>+ {<br>+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04, IO0)<br>+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01, IO1)<br>+ IRQ (Edge, ActiveHigh, Exclusive, Y08) {6}<br>+ DMA (Compatibility, NotBusMaster, Transfer8, Y09) {2}<br>+ })<br>+ CreateWordField (BUF0, IO1._MIN, IO1I)<br>+ CreateWordField (BUF0, IO1._MAX, IO1A)<br>+<br>+ ENTER_CONFIG_MODE(W83977TF_FDC)<br>+ /* OEM BIOS does not report actual programmed base port */<br>+ /* xx0 is read from superio */<br>+ PNP_READ_IO(PNP_IO0, BUF0, IO0)<br>+ /* Store xx7 range first so the value isn't overwritten<br>+ * for below */<br>+ Add(IO0I, 7, IO1I)<br>+ Store(IO1I, IO1A)<br>+ /* Store xx2 range */<br>+ Add(IO0I, 2, IO0I)<br>+ Store(IO0I, IO0A)<br>+ /* End OEM BIOS deficiency */<br>+ PNP_READ_IRQ(PNP_IRQ0, BUF0, Y08)<br>+ PNP_READ_DMA(PNP_DMA0, BUF0, Y09)<br>+ EXIT_CONFIG_MODE()<br>+ Return (BUF0)<br>+ }<br>+<br>+ Name (_PRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04, )<br>+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01, )<br>+ IRQ (Edge, ActiveHigh, Exclusive, ) {6}<br>+ DMA (Compatibility, NotBusMaster, Transfer8, ) {2}<br>+ })<br>+ Method (_SRS, 1, NotSerialized)<br>+ {<br>+ CreateByteField (Arg0, 0x02, IOLO)<br>+ CreateByteField (Arg0, 0x03, IOHI)<br>+ CreateWordField (Arg0, 0x11, IRQW)<br>+ CreateByteField (Arg0, 0x15, DMAV)<br>+ ENTER_CONFIG_MODE(W83977TF_FDC)<br>+ /* FDC base port on 8-byte boundary. */<br>+ And (IOLO, 0xF8, PNP_IO0_LOW_BYTE)<br>+ Store (IOHI, PNP_IO0_HIGH_BYTE)<br>+ Subtract (FindSetLeftBit (IRQW), 1, PNP_IRQ0)<br>+ Subtract (FindSetLeftBit (DMAV), 1, PNP_DMA0)<br>+ Store (One, PNP_DEVICE_ACTIVE)<br>+ EXIT_CONFIG_MODE()<br>+ }<br>+}<br>+#endif<br>+#ifdef WINBOND_SHOW_LPT<br>+Device (LPT)<br>+{<br>+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID<br>+ Method (_STA, 0, NotSerialized) // _STA: Status<br>+ {<br>+ ENTER_CONFIG_MODE(W83977TF_PP)<br>+ And (OPT1, 0x02, Local0)<br>+ If (LOr (IO0H, IO0L))<br>+ {<br>+ If (LEqual (Local0, 0x02)) /* Report device not present if ECP is enabled */<br>+ {<br>+ EXIT_CONFIG_MODE()<br>+ Return (0x00)<br>+ }<br>+ ElseIf (ACTR)<br>+ {<br>+ EXIT_CONFIG_MODE()<br>+ Return (0x0F)<br>+ }<br>+ Else<br>+ {<br>+ EXIT_CONFIG_MODE()<br>+ Return (0x0D)<br>+ }<br>+ }<br>+<br>+ EXIT_CONFIG_MODE()<br>+ Return (0)<br>+ }<br>+<br>+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device<br>+ {<br>+ PNP_GENERIC_DIS(W83977TF_PP)<br>+ }<br>+<br>+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings<br>+ {<br>+ Name (BUF5, ResourceTemplate ()<br>+ {<br>+ IO (Decode16,0x0378,0x0378,0x00,0x04,Y0A)<br>+ IRQ (Edge, ActiveHigh, Exclusive, Y0B)<br>+ {7}<br>+ })<br>+ ENTER_CONFIG_MODE(W83977TF_PP)<br>+ PNP_READ_IO(PNP_IO0,BUF5,Y0A)<br>+ PNP_READ_IRQ(PNP_IRQ0,BUF5,Y0B)<br>+ EXIT_CONFIG_MODE()<br>+ Return (BUF5)<br>+ }<br>+<br>+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings<br>+ {<br>+ StartDependentFn (0x01, 0x01)<br>+ {<br>+ IO (Decode16,0x0378,0x0378,0x00,0x08,)<br>+ IRQ (Edge, ActiveHigh, Exclusive, )<br>+ {5,7}<br>+ }<br>+ StartDependentFn (0x01, 0x01)<br>+ {<br>+ IO (Decode16,0x0278,0x0278,0x00,0x08,)<br>+ IRQ (Edge, ActiveHigh, Exclusive, )<br>+ {5,7}<br>+ }<br>+ StartDependentFn (0x01, 0x01)<br>+ {<br>+ IO (Decode16,0x03BC,0x03BC,0x00,0x04,)<br>+ IRQ (Edge, ActiveHigh, Exclusive, )<br>+ {5,7}<br>+ }<br>+ EndDependentFn ()<br>+ })<br>+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings<br>+ {<br>+ CreateByteField (Arg0, 0x02, IOLO)<br>+ CreateByteField (Arg0, 0x03, IOHI)<br>+ CreateWordField (Arg0, 0x09, IRQW)<br>+ ENTER_CONFIG_MODE(W83977TF_PP)<br>+ Store (IOLO, PNP_IO0_LOW_BYTE)<br>+ Store (IOHI, PNP_IO0_HIGH_BYTE)<br>+ Subtract (FindSetLeftBit (IRQW), 1, PNP_IRQ0)<br>+ Store (One, PNP_DEVICE_ACTIVE)<br>+ EXIT_CONFIG_MODE()<br>+ }<br>+}<br>+/* ECP Parallel Port */<br>+Device (ECP)<br>+{<br>+ Name (_HID, EisaId ("PNP0401"))<br>+ Method (_STA, 0, NotSerialized)<br>+ {<br>+ ENTER_CONFIG_MODE(W83977TF_PP)<br>+ And (OPT1, 0x02, Local0)<br>+ If (LOr (IO0H, IO0L))<br>+ {<br>+ If (LEqual (Local0, 0x02))<br>+ {<br>+ If (ACTR)<br>+ {<br>+ EXIT_CONFIG_MODE()<br>+ Return (0x0F)<br>+ }<br>+ Else<br>+ {<br>+ EXIT_CONFIG_MODE()<br>+ Return (0x05)<br>+ }<br>+ }<br>+ }<br>+<br>+ EXIT_CONFIG_MODE()<br>+ Return (0x00)<br>+ }<br>+<br>+ Method (_DIS, 0, NotSerialized)<br>+ {<br>+ PNP_GENERIC_DIS(W83977TF_PP)<br>+ }<br>+<br>+ Method (_CRS, 0, NotSerialized)<br>+ {<br>+ Name (BUF6, ResourceTemplate ()<br>+ {<br>+ IO (Decode16,0x0378,0x0378,0,4,IO0)<br>+ IO (Decode16,0x0778,0x0778,0,4,IO1)<br>+ IRQ (Edge, ActiveHigh, Exclusive, IR1) {7}<br>+ DMA (Compatibility, NotBusMaster, Transfer8, Y0F) {1}<br>+ })<br>+ ENTER_CONFIG_MODE(W83977TF_PP)<br>+ PNP_READ_IO(PNP_IO0, BUF6, IO0)<br>+ PNP_READ_IO(PNP_IO1, BUF6, IO1)<br>+ PNP_READ_IRQ(PNP_IRQ0, BUF6, IR1)<br>+ PNP_READ_DMA(PNP_DMA0, BUF6, Y0F)<br>+<br>+ /* Report a second port range that is 0x400 above base port. */<br>+ CreateByteField (BUF6, 0x03, IOHI)<br>+ CreateByteField (BUF6, 0x0B, I2HI)<br>+ CreateByteField (BUF6, 0x0D, I2RH)<br>+ Add (IOHI, 0x04, I2HI)<br>+ Add (IOHI, 0x04, I2RH)<br>+ EXIT_CONFIG_MODE()<br>+ Return (BUF6)<br>+ }<br>+<br>+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings<br>+ {<br>+ StartDependentFn (0x01, 0x01)<br>+ {<br>+ IO (Decode16,0x0378,0x0378,0,4,)<br>+ IO (Decode16,0x0778,0x0778,0,4,)<br>+ IRQ (Edge, ActiveHigh, Exclusive, ) {5,7}<br>+ DMA (Compatibility, NotBusMaster, Transfer8, ) {0,1,3}<br>+ }<br>+ StartDependentFn (0x01, 0x01)<br>+ {<br>+ IO (Decode16,0x0278,0x0278,0,4,)<br>+ IO (Decode16,0x0678,0x0678,0,4,)<br>+ IRQ (Edge, ActiveHigh, Exclusive, ) {5,7}<br>+ DMA (Compatibility, NotBusMaster, Transfer8, ) {0,1,3}<br>+ }<br>+ StartDependentFn (0x01, 0x01)<br>+ {<br>+ IO (Decode16,0x03BC,0x03BC,0,4,)<br>+ IO (Decode16,0x07BC,0x07BC,0,4,)<br>+ IRQ (Edge, ActiveHigh, Exclusive, ) {5,7}<br>+ DMA (Compatibility, NotBusMaster, Transfer8, ) {0,1,3}<br>+ }<br>+ EndDependentFn ()<br>+ })<br>+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings<br>+ {<br>+ CreateByteField (Arg0, 0x02, IOLO)<br>+ CreateByteField (Arg0, 0x03, IOHI)<br>+ CreateWordField (Arg0, 0x11, IRQW)<br>+ CreateByteField (Arg0, 0x15, DMAC)<br>+<br>+ ENTER_CONFIG_MODE(W83977TF_PP)<br>+ Store (IOLO, PNP_IO0_LOW_BYTE)<br>+ Store (IOHI, PNP_IO0_HIGH_BYTE)<br>+ Subtract (FindSetLeftBit (IRQW), 1, PNP_IRQ0)<br>+ Subtract (FindSetLeftBit (DMAC), 1, PNP_DMA0)<br>+ Store (One, PNP_DEVICE_ACTIVE)<br>+ EXIT_CONFIG_MODE()<br>+}<br>+}<br>+#endif<br>+<br>+#undef SUPERIO_UART_PM_VAL<br>+#undef SUPERIO_UART_PM_LDN<br>+#undef SUPERIO_UART_DDN<br>+#define SUPERIO_UART_PM_VAL 0<br>+#define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE<br>+<br>+#ifdef WINBOND_SHOW_UARTA<br>+ #undef SUPERIO_UART_LDN<br>+ #undef SUPERIO_UART_PM_REG<br>+ #define SUPERIO_UART_LDN W83977TF_SP1<br>+ #define SUPERIO_UART_PM_REG UAPW<br>+ #include <superio/acpi/pnp_uart.asl><br>+#endif<br>+<br>+#ifdef WINBOND_SHOW_UARTB<br>+ #undef SUPERIO_UART_LDN<br>+ #undef SUPERIO_UART_PM_REG<br>+ #define SUPERIO_UART_LDN W83977TF_SP2<br>+ #define SUPERIO_UART_PM_REG UBPW<br>+ #include <superio/acpi/pnp_uart.asl><br>+#endif<br>+<br>+/* TODO: IrDA device;<br>+ * '977EF=LDN 3 aka UARTB<br>+ * Some revisions of TF=LDN 6<br>+ */<br>+<br>+#define SUPERIO_KBC_LDN W83977TF_KBC<br>+#define SUPERIO_KBC_PS2M /* Mouse shares same LDN */<br>+#undef SUPERIO_KBC_PS2LDN<br>+#include <superio/acpi/pnp_kbc.asl><br>+/*<br>+}<br>+*/<br></pre><p>To view, visit <a href="https://review.coreboot.org/21670">change 21670</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If113807901619bc0f4250607546be415f9e5e45b </div>
<div style="display:none"> Gerrit-Change-Number: 21670 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>